index
:
riscv-isa-manual.git
1437-update-generated-filenames-to-be-more-desciptive
1454-fix-merge-and-release-workflow
1532-lack-of-list-of-figures-tables
Sv57
Svinval
Svnapot
Svpbmt
antora-refactor
aswaterman-patch-1
atomics-wording-v2
bonzini-hpmdelta
cnop
convert2adoc_rvwmo
csr-wip
dev/beeman/smctr-ssctr
fix-adoc-IDs
fix-fedora-build
hypervisor
kersten1-patch-3
latex
lrsc
main
misa-ztso
msip
mtime-optional
n-ext
pmp
ratified-priv-v1.11-sans-hypervisor-draft
sail-inclusion-example
sfence-asid
smpmpmt
svkt
tmp
trap
v20240411
virtual-memory
wfmi
zam
zfb
ztso-ratification
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2021-09-17
Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adoc
elisa
6
-24
/
+45
2021-09-17
adding missing image files and placing bibtex file in location where asciidoc...
elisa
3
-0
/
+513
2021-09-15
Priv-1.12 spec for public review
riscv-privileged-20210915-public-review
Andrew Waterman
2
-8
/
+7
2021-09-15
JohnH is an editor of the priv spec
Andrew Waterman
1
-1
/
+1
2021-09-15
RISC-V Foundation -> RISC-V International
Andrew Waterman
5
-10
/
+10
2021-09-15
Freeze the hypervisor extension, version 1.0.0-rc (#739)
John Hauser
2
-4
/
+7
2021-09-15
mip.MSIP and mie.MSIE may be hardwired zeros (#738)
John Hauser
1
-0
/
+4
2021-09-14
Hypervisor extension requires page-based address translation (#737)
John Hauser
1
-1
/
+2
2021-09-14
Fix apparent typo re hpmcounter*h (#735)
Scott Johnson
1
-1
/
+1
2021-09-14
State behavior of uncacheable accesses to cacheable locations
Andrew Waterman
1
-0
/
+13
2021-09-14
Clarify that WARL fields contain legal values after reset (#734)
Andrew Waterman
1
-0
/
+1
2021-09-13
Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adoc
elisa
2
-4
/
+4
2021-09-11
begin adding graphviz files
elisa
1
-0
/
+40
2021-09-11
adding fonts and theme to use in local builds
elisa
27
-0
/
+877
2021-09-11
Rename STCE to STCD to reverse its polarity
Andrew Waterman
2
-4
/
+4
2021-09-10
adding converted adoc files
elisa
38
-0
/
+12831
2021-09-10
adding build images and wavedrom source files
elisa
45
-0
/
+1034
2021-09-10
adding pdf from adoc conversion
elisa
1
-0
/
+0
2021-09-10
Generalize SSIP to support forthcoming interrupt controllers (#726)
Andrew Waterman
2
-23
/
+4
2021-09-10
Speculative implicit reads, v2 (#724)
Andrew Waterman
3
-2
/
+18
2021-09-09
Fix a typo in Figure A.13. (#733)
Daniel Lustig
1
-1
/
+1
2021-09-08
Merge pull request #727 from riscv/mseccfg
Andrew Waterman
5
-2
/
+393
2021-09-08
FIOM may be hardwired when satp is hardwired
Andrew Waterman
2
-1
/
+4
2021-09-05
Make virtual instruction exceptions more consistent for VU mode (#730)
John Hauser
1
-3
/
+13
2021-09-02
Describe purpose of FIOM mechanism
Andrew Waterman
2
-0
/
+45
2021-09-02
Pedantically clarify behavior of writing lo/hi parts of counters
Andrew Waterman
1
-4
/
+5
2021-09-01
Remove errant preface entry
Andrew Waterman
1
-1
/
+0
2021-09-01
Clarify widths of privileged CSRs (#728)
John Hauser
3
-44
/
+49
2021-09-01
FIOM may optionally not exist in M/U systems
Andrew Waterman
1
-0
/
+2
2021-08-30
Revert "Replace "EEI" with "execution environment" (#723)"
Andrew Waterman
4
-49
/
+33
2021-08-30
Fix constraint on existence of menvcfg[h]/FIOM
Andrew Waterman
1
-2
/
+3
2021-08-29
FIOM affects aq/rl, too
Andrew Waterman
3
-0
/
+16
2021-08-29
Add henvcfg/senvcfg CSRs
Andrew Waterman
3
-0
/
+165
2021-08-29
Minor changes to JohnH's henvcfg spec
Andrew Waterman
1
-30
/
+36
2021-08-29
Add *envcfg CSR allocations
Andrew Waterman
1
-0
/
+11
2021-08-29
Add CSRs henvcfg/henvcfgh to hypervisor extension
John Hauser
1
-2
/
+88
2021-08-29
Add mseccfg CSR
Andrew Waterman
3
-0
/
+56
2021-08-29
Add preface entry
Andrew Waterman
1
-0
/
+2
2021-08-29
Designate some of SYSTEM opcode for custom use
Andrew Waterman
1
-0
/
+40
2021-08-28
Add mconfigptr CSR (#697)
Andrew Waterman
3
-0
/
+49
2021-08-28
Replace "EEI" with "execution environment" (#723)
John Hauser
4
-33
/
+49
2021-08-27
Fix (again) non-normative CSR side-effect text
Andrew Waterman
1
-2
/
+1
2021-08-25
Remove historical remark on MRET definition
Andrew Waterman
1
-9
/
+0
2021-08-24
Fix non-normative text about CSR ordering (#720)
Andrew Waterman
1
-9
/
+12
2021-08-18
Update H chapter table of synchronous exception priorities (#717)
John Hauser
1
-20
/
+19
2021-08-18
Tweak table of synchronous exception priorities (#716)
John Hauser
1
-5
/
+6
2021-08-17
Make explicit the priorities of synch. exceptions of H extension (#711)
John Hauser
1
-0
/
+53
2021-08-17
Clarify priorities of synchronous exceptions (#715)
John Hauser
1
-14
/
+30
2021-08-16
stval already cannot be zero on breakpoints, misaligned addresses (#714)
John Hauser
1
-5
/
+2
2021-08-16
VS mode should not see exception code 10 (#712)
John Hauser
1
-0
/
+1
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