6 files changed, 45 insertions, 24 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex
index d53441e..1448ad9 100644
--- a/src/hypervisor.tex
+++ b/src/hypervisor.tex
@@ -1,8 +1,11 @@
-\chapter{Hypervisor Extension, Version 0.6.2}
+\chapter{Hypervisor Extension, Version 1.0.0-rc}
 \label{hypervisor}
 
-{\bf Warning! This draft specification may change before being
-accepted as standard by the RISC-V Foundation.}
+This chapter is in the Frozen state.
+A substantive change that is not backward-compatible is highly
+unlikely, and will occur only as the result of some truly critical
+issue being identified.
+For more info see:  \texttt{http://riscv.org/spec-state}.
 
 This chapter describes the RISC-V hypervisor extension, which virtualizes the
 supervisor-level architecture to support the efficient hosting of guest
@@ -27,7 +30,8 @@ implement the SBI for its VS-mode guest.
 The hypervisor extension depends on an ``I'' base integer ISA with
 32 {\tt x} registers (RV32I or RV64I), not RV32E, which has only
 16 {\tt x} registers.
-CSR {\tt mtval} must not be hardwired to zero.
+CSR {\tt mtval} must not be hardwired to zero, and
+{\tt satp}.MODE must not be hardwired to Bare.
 
 The hypervisor extension is enabled by setting bit 7 in the {\tt misa} CSR,
 which corresponds to the letter H.
diff --git a/src/intro.tex b/src/intro.tex
index 4acdd42..330902b 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -311,8 +311,8 @@ For this purpose, we divide each RISC-V
 instruction-set encoding space (and related encoding spaces such as
 the CSRs) into three disjoint categories: {\em standard}, {\em
   reserved}, and {\em custom}.  Standard extensions and encodings
-are defined by the Foundation; any extensions not defined by the
-Foundation are {\em non-standard}.
+are defined by RISC-V International; any extensions not defined by
+RISC-V International are {\em non-standard}.
 Each base ISA and its standard extensions use only standard encodings,
 and shall not conflict with each other in their uses of these encodings.
 Reserved encodings are currently not defined but are saved for future
diff --git a/src/machine.tex b/src/machine.tex
index fece762..3472d44 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -231,8 +231,8 @@ that is one less than the JEDEC bank number.
 \end{commentary}
 
 \begin{commentary}
-Previously the vendor ID was to be a number allocated by the RISC-V
-Foundation, but this duplicates the work of JEDEC in maintaining a
+Previously the vendor ID was to be a number allocated by RISC-V
+International, but this duplicates the work of JEDEC in maintaining a
 manufacturer ID standard.  At time of writing, registering a
 manufacturer ID with JEDEC has a one-time cost of \$500.
 \end{commentary}
@@ -263,8 +263,8 @@ MXLEN \\
 \label{marchreg}
 \end{figure*}
 
-Open-source project architecture IDs are allocated globally by the
-RISC-V Foundation, and have non-zero architecture IDs with a zero
+Open-source project architecture IDs are allocated globally by
+RISC-V International, and have non-zero architecture IDs with a zero
 most-significant-bit (MSB).  Commercial architecture IDs are allocated
 by each commercial vendor independently, but must have the MSB set and
 cannot contain zero in the remaining MXLEN-1 bits.
@@ -276,7 +276,7 @@ occurs rather than a particular organization.  Commercial fabrications
 of open-source designs should (and might be required by the license
 to) retain the original architecture ID.  This will aid in reducing
 fragmentation and tool support costs, as well as provide attribution.
-Open-source architecture IDs should be administered by the Foundation
+Open-source architecture IDs are administered by RISC-V International
 and should only be allocated to released, functioning open-source
 projects.  Commercial architecture IDs can be managed independently by
 any registered vendor but are required to have IDs disjoint from the
@@ -1528,6 +1528,10 @@ to memory-mapped control registers, which are used by remote harts to
 provide machine-level interprocessor interrupts.
 A hart can write its
 own MSIP bit using the same memory-mapped control register.
+If a system has only one hart, or if a platform standard supports the
+delivery of machine-level interprocessor interrupts through external
+interrupts (MEI) instead, then {\tt mip}.MSIP and {\tt mie}.MSIE may
+both be hardwired to zeros.
 
 If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of
 {\tt mip} and SEIE, STIE, and SSIE of {\tt mie} are hardwired to zeros.
@@ -1770,7 +1774,7 @@ The {\tt cycle}, {\tt instret}, and {\tt hpmcounter{\em n}} CSRs are
 read-only shadows of {\tt mcycle}, {\tt minstret}, and {\tt mhpmcounter{\em
 n}}, respectively.  The {\tt time} CSR is a read-only shadow of the
 memory-mapped {\tt mtime} register.  Analogously, on RV32I the {\tt cycleh},
-{\tt instreth} and {\tt hpmcounter{\em n}} CSRs are read-only shadows of
+{\tt instreth} and {\tt hpmcounter{\em n}h} CSRs are read-only shadows of
 {\tt mcycleh}, {\tt minstreth} and {\tt mhpmcounter{\em n}h}, respectively.
 On RV32I the {\tt timeh} CSR is a read-only shadow of the upper 32 bits of
 the memory-mapped {\tt mtime} register, while {\tt time} shadows only the
@@ -2817,6 +2821,7 @@ reset vector.  The {\tt mcause} register is set to a value indicating the
 cause of the reset.
 Writable PMP registers' A and L fields are set to 0, unless the platform
 mandates a different reset value for some PMP registers' A and L fields.
+No \warl\ field contains an illegal value.
 All other hart state is \unspecified.
 
 The {\tt mcause} values after reset have implementation-specific
@@ -3231,6 +3236,19 @@ because they will be fixed as either uncached, read-only, hardware
 cache-coherent, or only accessed by one agent.
 \end{commentary}
 
+If a PMA indicates non-cacheability, then accesses to that region must
+be satisfied by the memory itself, not by any caches.
+
+\begin{commentary}
+For implementations with a cacheability-control mechanism, the situation
+may arise that a program uncacheably accesses a memory location that is
+currently cache-resident.
+In this situation, the cached copy must be ignored.
+This constraint is necessary to prevent more-privileged modes' speculative
+cache refills from affecting the behavior of less-privileged modes'
+uncacheable accesses.
+\end{commentary}
+
 \subsection{Idempotency PMAs}
 
 Idempotency PMAs describe whether reads and writes to an address
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index a1a0848..44cfc29 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -1,9 +1,8 @@
 \chapter{Preface}
 
-This is {\bf a draft of} version 1.12 of the RISC-V privileged
-architecture proposal.
-The document contains the following versions of the RISC-V ISA
-modules:
+This document describes the RISC-V privileged architecture.  This
+release, version \privrev, will be used for public review of the
+following modules:
 
 {
 \begin{table}[hbt]
@@ -12,16 +11,16 @@ modules:
     \hline
     Module             & Version  & Status\\
     \hline
-    \em Machine ISA    & \em 1.12 & \em Draft \\
-    \em Supervisor ISA & \em 1.12 & \em Draft \\
-    \em Hypervisor ISA & \em 0.6  & \em Draft \\
+    \em Machine ISA    & \em 1.12 & \em Frozen \\
+    \em Supervisor ISA & \em 1.12 & \em Frozen \\
+    \em Hypervisor ISA & \em 1.0  & \em Frozen \\
     \hline
   \end{tabular}
 \end{table}
 }
 
 The Machine and Supervisor ISAs, version 1.11, have been ratified by
-the RISC-V Foundation.  Version 1.12 of these modules, described in
+RISC-V International.  Version 1.12 of these modules, described in
 this document, is a minor revision to version 1.11.
 
 The following changes have been made since version 1.11, which, while not
diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex
index 9933ae8..bf71aed 100644
--- a/src/riscv-privileged.tex
+++ b/src/riscv-privileged.tex
@@ -10,8 +10,8 @@
 
 \input{preamble}
 
-\newcommand{\privrev}{1.12-draft}
-\newcommand{\privmonthyear}{June 2019}
+\newcommand{\privrev}{20210915-Public-Review-{\em draft}}
+\newcommand{\privmonthyear}{September 2021}
 
 \setcounter{secnumdepth}{3}
 \setcounter{tocdepth}{3}
@@ -57,7 +57,7 @@ Creative Commons Attribution 4.0 International License.
 
 Please cite as: ``The RISC-V Instruction Set
 Manual, Volume II: Privileged Architecture, Document Version \privrev'', Editors
-Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, \privmonthyear.
+Andrew Waterman, Krste Asanovi\'{c}, and John Hauser, RISC-V International, \privmonthyear.
 
 \markboth{Volume II: RISC-V Privileged Architectures V\privrev}
 {Volume II: RISC-V Privileged Architectures V\privrev}
diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex
index a67cfd8..1b0e3b6 100644
--- a/src/riscv-spec.tex
+++ b/src/riscv-spec.tex
@@ -59,7 +59,7 @@ Creative Commons Attribution 4.0 International License.
 
 Please cite as: ``The RISC-V Instruction Set
 Manual, Volume I: User-Level ISA, Document Version \specrev'', Editors
-Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, \specmonthyear.
+Andrew Waterman and Krste Asanovi\'{c}, RISC-V International, \specmonthyear.
 
 
 \markboth{Volume I: RISC-V Unprivileged ISA V\specrev}