riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-01-24	Change SweRV EH1 URL (#330)	tmw-wdc	1	-1/+1
2019-01-23	Change contact for SweRV EH1 (#329)	tmw-wdc	1	-1/+1
2019-01-22	Nest mstatus subsections	Andrew Waterman	2	-5/+8
2019-01-21	Add tentative HFENCE.BVMA and HFENCE.GVMA encodings	Andrew Waterman	1	-1/+28
2019-01-21	Add hypervisor CSR listing	Andrew Waterman	1	-43/+42
2019-01-21	A/D updates are globally ordered	Andrew Waterman	1	-1/+4
2019-01-21	Fix typo. (#326)	Prashanth Mundkur	1	-1/+1
2019-01-18	Clarify that FMV.X.W doesn't canonicalize NaN payloads	Andrew Waterman	2	-1/+7
2019-01-17	JALR is not allowed within LR/SC sequences	Andrew Waterman	1	-1/+1
2019-01-16	Update marchid.md (#325)	tmw-wdc	1	-0/+1
2018-12-27	Clarify that writing pmpcfg does not alter pmpaddr's underlying value	Andrew Waterman	1	-0/+4
2018-12-26	Rephrase NA4 restriction	Andrew Waterman	1	-1/+1
2018-12-21	tweaks	Andrew Waterman	2	-4/+3
2018-12-21	Address space is circular	Andrew Waterman	1	-1/+7
2018-12-21	Add extension dependences to table	Andrew Waterman	1	-32/+34
2018-12-21	Specify ordering of privileged and non-standard extensions	Andrew Waterman	1	-16/+45
2018-12-20	Add old v1.0 and v2.0 spec PDFs	Andrew Waterman	2	-0/+0
2018-12-20	Specify ordering of Z extensions	Andrew Waterman	1	-0/+7
2018-12-20	Clean up naming and define G = IMAFDZicsr_Zifencei	Andrew Waterman	3	-22/+18
2018-12-20	tweaks	Andrew Waterman	1	-4/+5
2018-12-20	Merge pull request #311 from brucehoult/ra-sp-cleanup	Krste Asanovic	1	-6/+22
2018-12-20	Improve description of IEEE exception-flag setting	Andrew Waterman	1	-10/+9
2018-12-20	Add contributor	Andrew Waterman	1	-1/+1
2018-12-20	Clarify that PTE updates aren't atomic w.r.t. the ultimate access (#308)	Andrew Waterman	1	-3/+9
2018-12-20	Clarify sign extension of W and D instructions (#313)	Bruce Hoult	1	-5/+7
2018-12-20	Add contributor (#314)	Bruce Hoult	1	-1/+1
2018-12-20	ABIs could dedicate other JALR base registers	Andrew Waterman	1	-1/+3
2018-12-20	Clean up description of x registers. Add commentary about ABI	Bruce Hoult	1	-6/+22
2018-12-19	Merge branch 'brucehoult-mips-compact-branches'	Andrew Waterman	1	-2/+2
2018-12-19	Update commentary to reflect MIPS r6 conditional branches	Bruce Hoult	1	-2/+2
2018-12-19	Improve description of C opcode map	Andrew Waterman	1	-1/+3
2018-12-19	Improve rd'/rs1'/rs2' typesetting	Andrew Waterman	2	-118/+122
2018-12-14	Disambiguate P extension in ISA strings	Andrew Waterman	1	-0/+5
2018-12-14	ISA extension dependences can be assumed in ISA name strings	Andrew Waterman	2	-10/+4
2018-12-14	cleanup	Andrew Waterman	1	-2/+2
2018-12-13	Make branch immediate description more similar to jumps	Andrew Waterman	1	-2/+3
2018-12-12	Fix some incorrect references to RV32IF (as opposed to RV32IFZicsr)	Andrew Waterman	2	-4/+4
2018-12-11	Restate that conditional branches can raise misaligned exceptions in RVI	Andrew Waterman	1	-0/+12
2018-12-10	Remark that F depends on Zicsr	Andrew Waterman	1	-6/+7
2018-12-10	ISA strings can't leverage extension-dependence properties	Andrew Waterman	1	-0/+10
2018-12-10	subset -> extension	Andrew Waterman	5	-21/+21
2018-12-10	X/S/Z* names must be fully alphabetical	Andrew Waterman	1	-6/+6
2018-12-10	fix typos	Andrew Waterman	1	-2/+2
2018-12-04	Debug registers 7A0-7AF are accessible to M-mode	Andrew Waterman	1	-3/+5
2018-12-04	Re-version priv spec	Andrew Waterman	1	-1/+1
2018-12-04	Version of priv spec ready for ratification process	Andrew Waterman	3	-8/+22
2018-12-03	Mostly remove RV128 from priv spec, for now	Andrew Waterman	3	-32/+36
2018-12-03	Made clear this document written as if only privileged architecture.	Krste Asanovic	1	-13/+15
2018-12-03	Update version number	Andrew Waterman	1	-1/+1
2018-12-03	Adding an marchid for the RVBS open source project (#292)	Alexandre Joannou	1	-1/+2