Clarify sign extension of W and D instructions (#313)

1 files changed, 7 insertions, 5 deletions

diff --git a/src/rv128.tex b/src/rv128.tex
index 64515e3..7ba3cf7 100644
--- a/src/rv128.tex
+++ b/src/rv128.tex
@@ -41,11 +41,13 @@ RV128I builds upon RV64I in the same way RV64I builds upon RV32I, with
 integer registers extended to 128 bits (i.e., XLEN=128).  Most integer
 computational instructions are unchanged as they are defined to
 operate on XLEN bits.  The RV64I ``*W'' integer instructions that
-operate on 32-bit values in the low bits of a register are retained,
-and a new set of ``*D'' integer instructions that operate on 64-bit
-values held in the low bits of the 128-bit integer registers are
-added.  The ``*D'' instructions consume two major opcodes (OP-IMM-64
-and OP-64) in the standard 32-bit encoding.
+operate on 32-bit values in the low bits of a register are retained
+but now sign extend their results from bit 31 to bit 127. A new set of
+``*D'' integer instructions are added that operate on 64-bit values
+held in the low bits of the 128-bit integer registers and sign extend
+their results from bit 63 to bit 127.  The ``*D'' instructions consume
+two major opcodes (OP-IMM-64 and OP-64) in the standard 32-bit
+encoding.
 
 \begin{commentary}
   To improve compatibility with RV64, in a reverse of how RV32 to RV64