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| author | Andrew Waterman <andrew@sifive.com> | 2019-01-21 19:14:14 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-01-21 19:14:14 -0800 |
| commit | 516b9ed10b7c3bf17593034b66bd2c203d26a510 (patch) | |
| tree | e5c1cc8246fd44baa225a7a945a097abccb00d9c | |
| parent | 01ac22d38796114d88ef2547e24129facbc9a8e1 (diff) | |
| download | riscv-isa-manual-516b9ed10b7c3bf17593034b66bd2c203d26a510.zip riscv-isa-manual-516b9ed10b7c3bf17593034b66bd2c203d26a510.tar.gz riscv-isa-manual-516b9ed10b7c3bf17593034b66bd2c203d26a510.tar.bz2 | |
Add hypervisor CSR listing
| -rw-r--r-- | src/priv-csrs.tex | 85 |
1 files changed, 42 insertions, 43 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 3941b0b..714c3c2 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -64,18 +64,15 @@ less-privileged software. \tt 11 &\tt 01 &\tt 00-10 & \tt 0xD00-0xDBF & Standard read-only \\ \tt 11 &\tt 01 &\tt 11 & \tt 0xDC0-0xDFF & Custom read-only \\ \hline -\multicolumn{5}{|c|}{Reserved CSRs} \\ +\multicolumn{5}{|c|}{Hypervisor CSRs} \\ \hline -\tt XX &\tt 10 &\tt XX & Reserved & \\ -%% \multicolumn{5}{|c|}{Hypervisor CSRs} \\ -%% \hline -%% \tt 00 &\tt 10 &\tt XX & \tt 0x200-0x2FF & Standard read/write \\ -%% \tt 01 &\tt 10 &\tt 00-10 & \tt 0x600-0x6BF & Standard read/write \\ -%% \tt 01 &\tt 10 &\tt 11 & \tt 0x6C0-0x6FF & Custom read/write \\ -%% \tt 10 &\tt 10 &\tt 00-10 & \tt 0xA00-0xABF & Standard read/write \\ -%% \tt 10 &\tt 10 &\tt 11 & \tt 0xAC0-0xAFF & Custom read/write \\ -%% \tt 11 &\tt 10 &\tt 00-10 & \tt 0xE00-0xEBF & Standard read-only \\ -%% \tt 11 &\tt 10 &\tt 11 & \tt 0xEC0-0xEFF & Custom read-only \\ +\tt 00 &\tt 10 &\tt XX & \tt 0x200-0x2FF & Standard read/write \\ +\tt 01 &\tt 10 &\tt 00-10 & \tt 0x600-0x6BF & Standard read/write \\ +\tt 01 &\tt 10 &\tt 11 & \tt 0x6C0-0x6FF & Custom read/write \\ +\tt 10 &\tt 10 &\tt 00-10 & \tt 0xA00-0xABF & Standard read/write \\ +\tt 10 &\tt 10 &\tt 11 & \tt 0xAC0-0xAFF & Custom read/write \\ +\tt 11 &\tt 10 &\tt 00-10 & \tt 0xE00-0xEBF & Standard read-only \\ +\tt 11 &\tt 10 &\tt 11 & \tt 0xEC0-0xEFF & Custom read-only \\ \hline \multicolumn{5}{|c|}{Machine CSRs} \\ \hline @@ -215,38 +212,40 @@ Number & Privilege & Name & Description \\ \label{scsrnames} \end{table} -%% \begin{table}[htb!] -%% \begin{center} -%% \begin{tabular}{|l|l|l|l|} -%% \hline -%% Number & Privilege & Name & Description \\ -%% \hline -%% \multicolumn{4}{|c|}{Hypervisor Trap Setup} \\ -%% \hline -%% \tt 0x200 & HRW &\tt hstatus & Hypervisor status register. \\ -%% \tt 0x202 & HRW &\tt hedeleg & Hypervisor exception delegation register. \\ -%% \tt 0x203 & HRW &\tt hideleg & Hypervisor interrupt delegation register. \\ -%% \tt 0x204 & HRW &\tt hie & Hypervisor interrupt-enable register. \\ -%% \tt 0x205 & HRW &\tt htvec & Hypervisor trap handler base address. \\ -%% \tt 0x206 & HRW &\tt hcounteren & Hypervisor counter enable. \\ -%% \hline -%% \multicolumn{4}{|c|}{Hypervisor Trap Handling} \\ -%% \hline -%% \tt 0x240 & HRW &\tt hscratch & Scratch register for hypervisor trap handlers. \\ -%% \tt 0x241 & HRW &\tt hepc & Hypervisor exception program counter. \\ -%% \tt 0x242 & HRW &\tt hcause & Hypervisor trap cause. \\ -%% \tt 0x243 & HRW &\tt htval & Hypervisor bad address or instruction. \\ -%% \tt 0x244 & HRW &\tt hip & Hypervisor interrupt pending. \\ -%% \hline -%% \multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\ -%% \hline -%% \tt 0x28X & TBD & TBD & TBD. \\ -%% \hline -%% \end{tabular} -%% \end{center} -%% \caption{Currently allocated RISC-V hypervisor-level CSR addresses.} -%% \label{hcsrnames} -%% \end{table} +\begin{table}[htb!] +\begin{center} +\begin{tabular}{|l|l|l|l|} +\hline +Number & Privilege & Name & Description \\ +\hline +\multicolumn{4}{|c|}{Hypervisor Trap Setup} \\ +\hline +\hline +\tt 0xA00 & HRW &\tt hstatus & Hypervisor status register. \\ +\tt 0xA02 & HRW &\tt hedeleg & Hypervisor exception delegation register. \\ +\tt 0xA03 & HRW &\tt hideleg & Hypervisor interrupt delegation register. \\ +\hline +\multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\ +\hline +\tt 0xA80 & HRW &\tt hgatp & Hypervisor guest address translation and protection. \\ +\hline +\multicolumn{4}{|c|}{Hypervisor Background Supervisor Registers} \\ +\hline +\tt 0x200 & HRW &\tt bsstatus & Background supervisor status register. \\ +\tt 0x204 & HRW &\tt bsie & Background supervisor interrupt-enable register. \\ +\tt 0x205 & HRW &\tt bstvec & Background supervisor trap handler base address. \\ +\tt 0x240 & HRW &\tt bsscratch & Background supervisor scratch register. \\ +\tt 0x241 & HRW &\tt bsepc & Background supervisor exception program counter. \\ +\tt 0x242 & HRW &\tt bscause & Background supervisor trap cause. \\ +\tt 0x243 & HRW &\tt bstval & Background supervisor bad address or instruction. \\ +\tt 0x244 & HRW &\tt bsip & Background supervisor interrupt pending. \\ +\tt 0x280 & HRW &\tt bsatp & Background supervisor address translation and protection. \\ +\hline +\end{tabular} +\end{center} +\caption{Currently allocated RISC-V hypervisor-level CSR addresses.} +\label{hcsrnames} +\end{table} \begin{table}[htb!] |