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author | Andrew Waterman <andrew@sifive.com> | 2018-12-12 17:06:10 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-12-12 17:06:10 -0800 |
commit | cfd8395ce137406ef34f41539962a0907c2bd3a4 (patch) | |
tree | 03657297bcbe1d841fb08908ca61a6af4c7fc2b8 | |
parent | 5eb0b27c814037999fcf74b6b4e13c15782d2089 (diff) | |
download | riscv-isa-manual-cfd8395ce137406ef34f41539962a0907c2bd3a4.zip riscv-isa-manual-cfd8395ce137406ef34f41539962a0907c2bd3a4.tar.gz riscv-isa-manual-cfd8395ce137406ef34f41539962a0907c2bd3a4.tar.bz2 |
Fix some incorrect references to RV32IF (as opposed to RV32IFZicsr)
-rw-r--r-- | src/naming.tex | 6 | ||||
-rw-r--r-- | src/q.tex | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/naming.tex b/src/naming.tex index ad0ba09..31c994f 100644 --- a/src/naming.tex +++ b/src/naming.tex @@ -33,7 +33,7 @@ extensions to the integer bases are: ``D'' for double-precision floating-point instructions. Any RISC-V instruction-set variant can be succinctly described by concatenating the base integer prefix with the names of the included -extensions. For example, ``RV64IMAFD''. +extensions. For example, ``RV64IMA''. We have also defined an abbreviation ``G'' to represent the ``IMAFD'' base and extensions, as this is intended to represent our standard @@ -77,7 +77,7 @@ time of this document, e.g., ``RV32G'' is equivalent to \section{Underscores} Underscores ``\_'' may be used to separate ISA extensions to -improve readability and to provide disambiguation. For example, ``RV32I2\_M2\_A2\_F2\_D2''. +improve readability and to provide disambiguation. For example, ``RV32I2\_M2\_A2''. \section{Additional Standard Extension Names} @@ -165,7 +165,7 @@ Supervisor extension ``ghi'' & SXghi \\ \caption{Standard ISA extension names. The table also defines the canonical order in which extension names must appear in the name string, with top-to-bottom in table indicating first-to-last in the - name string, e.g., RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not.} + name string, e.g., RV32IMACV is legal, whereas RV32IMAVC is not.} \label{isanametable} \end{table} @@ -5,7 +5,7 @@ This chapter describes the Q standard extension for 128-bit quad-precision binar floating-point instructions compliant with the IEEE 754-2008 arithmetic standard. The quad-precision binary floating-point instruction-set extension is named ``Q'', and requires -RV64IFD. The floating-point registers are now extended to hold either +RV64IFDZicsr. The floating-point registers are now extended to hold either a single, double, or quad-precision floating-point value (FLEN=128). The NaN-boxing scheme described in Section~\ref{nanboxing} is now extended recursively to allow a single-precision value to be NaN-boxed |