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Diffstat (limited to 'src')
-rw-r--r-- | src/hypervisor.tex | 90 |
1 files changed, 88 insertions, 2 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 44edab3..193189f 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -98,7 +98,7 @@ interrupt, and address-translation subsystems. Additional CSRs are provided to HS-mode, but not to VS-mode, to manage two-stage address translation and to control the behavior of a VS-mode guest: {\tt hstatus}, {\tt hedeleg}, {\tt hideleg}, {\tt hvip}, {\tt hip}, {\tt hie}, -{\tt hgeip}, {\tt hgeie}, +{\tt hgeip}, {\tt hgeie}, {\tt henvcfg}, {\tt henvcfgh}, {\tt hcounteren}, {\tt htimedelta}, {\tt htimedeltah}, {\tt htval}, {\tt htinst}, and {\tt hgatp}. @@ -124,7 +124,8 @@ do so. Conversely, when V=0, the VS CSRs do not ordinarily affect the behavior of the machine other than being readable and writable by CSR instructions. -Some standard supervisor CSRs ({\tt scounteren} and {\tt scontext}, +Some standard supervisor CSRs ({\tt senvcfg}, +{\tt scounteren}, and {\tt scontext}, possibly others) have no matching VS CSR. These supervisor CSRs continue to have their usual function and accessibility even when V=1, except with VS-mode and VU-mode substituting for @@ -808,6 +809,91 @@ cause a supervisor-level (HS-level) guest external interrupt. The enable bits in {\tt hgeie} do not affect the VS-level external interrupt signal selected from {\tt hgeip} by {\tt hstatus}.VGEIN. +\subsection{% + Hypervisor Environment Configuration Registers + ({\tt henvcfg} and {\tt henvcfgh})% +} + +The {\tt henvcfg} CSR is an HSXLEN-bit read/write register, +formatted as shown in Figure~\ref{fig:henvcfg}, that controls certain +characteristics of the execution environment when virtualization mode +V=1. +Only one bit of {\tt henvcfg} is used, but standard \mbox{RISC-V} ISA +extensions may define other fields in this register. + +\begin{figure}[h!] +{\footnotesize +\begin{center} +\begin{tabular}{@{}Jc} +\instbitrange{HSXLEN-1}{1} & +\instbit{0} \\ +\hline +\multicolumn{1}{|c|}{\wpri} & +\multicolumn{1}{c|}{FIOM} \\ +\hline +HSXLEN-1 & 1 \\ +\end{tabular} +\end{center} +} +\vspace{-0.1in} +\caption{Hypervisor environment configuration register ({\tt henvcfg}).} +\label{fig:henvcfg} +\end{figure} + +If bit FIOM (Fence of I/O implies Memory) is set to one in +{\tt henvcfg}, FENCE instructions executed when V=1 are modified +so the requirement to order accesses to device I/O implies also the +requirement to order main memory accesses. +Table~\ref{tab:henvcfg-FIOM} details the modified interpretation of +FENCE instruction bits PI, PO, SI, and SO when FIOM=1 and V=1. + +\begin{table}[h!] +\begin{center} +\begin{tabular}{|c|l|} +\hline +Instruction bit & Meaning when set \\ +\hline +PI & Predecessor device input and memory reads (PR implied) \\ +PO & Predecessor device output and memory writes (PW implied) \\ +\hline +SI & Successor device input and memory reads (SR implied) \\ +SO & Successor device output and memory writes (SW implied) \\ +\hline +\end{tabular} +\end{center} +\vspace{-0.1in} +\caption{% +Modified interpretation of FENCE predecessor and successor sets when +FIOM=1 and virtualization mode V=1.% +} +\label{tab:henvcfg-FIOM} +\end{table} + +When HSXLEN=32, {\tt henvcfgh} is a 32-bit read/write register that +generally contains the same fields as bits 63:32 of {\tt henvcfg} when +HSXLEN=64. +Register {\tt henvcfgh} does not exist when HSXLEN=64. + +\begin{figure}[h!] +{\footnotesize +\begin{center} +\begin{tabular}{@{}J} +\instbitrange{31}{0} \\ +\hline +\multicolumn{1}{|c|}{\wpri} \\ +\hline +32 \\ +\end{tabular} +\end{center} +} +\vspace{-0.1in} +\caption{% +High-half hypervisor environment configuration register +({\tt henvcfgh}), if HSXLEN=32.% +} +\label{fig:henvcfgh} +\end{figure} + \subsection{Hypervisor Counter-Enable Register ({\tt hcounteren})} The counter-enable register {\tt hcounteren} is a 32-bit register that |