diff options
Diffstat (limited to 'src')
133 files changed, 1587 insertions, 1615 deletions
diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc index 0dfb273..fa26a78 100644 --- a/src/b-st-ext.adoc +++ b/src/b-st-ext.adoc @@ -836,7 +836,7 @@ a single bit in a register. The bit is specified by its index. |=== -[#zbkb,reftext="Bit-manipulation for Cryptography"] +[[zbkb,Bit-manipulation for Cryptography]] ==== Zbkb: Bit-manipulation for Cryptography This extension contains instructions essential for implementing @@ -912,8 +912,8 @@ common operations in cryptographic workloads. | ✓ | ✓ -| rev.b -| <<insns-revb>> +| brev8 +| <<insns-brev8>> | ✓ | ✓ @@ -932,7 +932,7 @@ common operations in cryptographic workloads. |=== -[#zbkc,reftext="Carry-less multiplication for Cryptography"] +[[zbkc,Carry-less multiplication for Cryptography]] ==== Zbkc: Carry-less multiplication for Cryptography Carry-less multiplication is the multiplication in the polynomial ring over @@ -960,7 +960,7 @@ efficiently implement the GHASH operation, which is part of this workload. |=== -[#zbkx,reftext="Crossbar permutations"] +[[zbkx,Crossbar permutations]] ==== Zbkx: Crossbar permutations These instructions implement a "lookup table" for 4 and 8 bit elements @@ -984,13 +984,13 @@ latency does not depend on the (secret) data being operated on. |✓ |✓ -|xperm.n _rd_, _rs1_, _rs2_ -|<<#insns-xpermn>> +|xperm4 _rd_, _rs1_, _rs2_ +|<<#insns-xperm4>> |✓ |✓ -|xperm.b _rd_, _rs1_, _rs2_ -|<<#insns-xpermb>> +|xperm8 _rd_, _rs1_, _rs2_ +|<<#insns-xperm8>> |=== @@ -2568,14 +2568,14 @@ Included in:: |=== <<< -[#insns-revb,reftext="Reverse bits in bytes"] -==== rev.b +[#insns-brev8,reftext="Reverse bits in bytes"] +==== brev8 Synopsis:: Reverse the bits in each byte of a source register. Mnemonic:: -rev.b _rd_, _rs_ +brev8 _rd_, _rs_ Encoding:: [wavedrom, , svg] @@ -3471,14 +3471,14 @@ Included in:: |=== <<< -[#insns-xpermb,reftext="Crossbar permutation (bytes)"] -==== xperm.b +[#insns-xperm8,reftext="Crossbar permutation (bytes)"] +==== xperm8 Synopsis:: Byte-wise lookup of indices into a vector in registers. Mnemonic:: -xperm.b _rd_, _rs1_, _rs2_ +xperm8 _rd_, _rs1_, _rs2_ Encoding:: [wavedrom, , svg] @@ -3495,7 +3495,7 @@ Encoding:: .... Description:: -The xperm.b instruction operates on bytes. +The xperm8 instruction operates on bytes. The _rs1_ register contains a vector of XLEN/8 8-bit elements. The _rs2_ register contains a vector of XLEN/8 8-bit indexes. The result is each element in _rs2_ replaced by the indexed element in _rs1_, @@ -3504,15 +3504,15 @@ or zero if the index into _rs2_ is out of bounds. Operation:: [source,sail] -- -val xpermb_lookup : (bits(8), xlenbits) -> bits(8) -function xpermb_lookup (idx, lut) = { +val xperm8_lookup : (bits(8), xlenbits) -> bits(8) +function xperm8_lookup (idx, lut) = { (lut >> (idx @ 0b000))[7..0] } -function clause execute ( XPERM_B (rs2,rs1,rd)) = { +function clause execute ( XPERM8 (rs2,rs1,rd)) = { result : xlenbits = EXTZ(0b0); foreach(i from 0 to xlen by 8) { - result[i+7..i] = xpermn_lookup(X(rs2)[i+7..i], X(rs1)); + result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1)); }; X(rd) = result; RETIRE_SUCCESS @@ -3532,14 +3532,14 @@ Included in:: |=== <<< -[#insns-xpermn,reftext="Crossbar permutation (nibbles)"] -==== xperm.n +[#insns-xperm4,reftext="Crossbar permutation (nibbles)"] +==== xperm4 Synopsis:: Nibble-wise lookup of indices into a vector. Mnemonic:: -xperm.n _rd_, _rs1_, _rs2_ +xperm4 _rd_, _rs1_, _rs2_ Encoding:: [wavedrom, , svg] @@ -3556,7 +3556,7 @@ Encoding:: .... Description:: -The xperm.n instruction operates on nibbles. +The xperm4 instruction operates on nibbles. The _rs1_ register contains a vector of XLEN/4 4-bit elements. The _rs2_ register contains a vector of XLEN/4 4-bit indexes. The result is each element in _rs2_ replaced by the indexed element in _rs1_, @@ -3565,15 +3565,15 @@ or zero if the index into _rs2_ is out of bounds. Operation:: [source,sail] -- -val xpermn_lookup : (bits(4), xlenbits) -> bits(4) -function xpermn_lookup (idx, lut) = { +val xperm4_lookup : (bits(4), xlenbits) -> bits(4) +function xperm4_lookup (idx, lut) = { (lut >> (idx @ 0b00))[3..0] } -function clause execute ( XPERM_N (rs2,rs1,rd)) = { +function clause execute ( XPERM4 (rs2,rs1,rd)) = { result : xlenbits = EXTZ(0b0); foreach(i from 0 to xlen by 4) { - result[i+3..i] = xpermn_lookup(X(rs2)[i+3..i], X(rs1)); + result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1)); }; X(rd) = result; RETIRE_SUCCESS diff --git a/src/colophon.adoc b/src/colophon.adoc index b7b52af..5f9ef72 100644 --- a/src/colophon.adoc +++ b/src/colophon.adoc @@ -34,6 +34,7 @@ h|Extension h|Version h|Status |*A* |*2.1* |*Ratified* |*Zawrs* |*1.01* |*Ratified* |*Zacas* |*1.0* |*Ratifed* +|*Zabha* |*1.0* |*Ratifed* |*RVWMO* |*2.0* |*Ratified* |*Ztso* |*1.0* |*Ratified* |*CMO* |*1.0* |*Ratified* @@ -65,6 +66,8 @@ h|Extension h|Version h|Status |*Zvksed* |*1.0* |*Ratified* |*Zvksh* |*1.0* |*Ratified* |*Zvkt* |*1.0* |*Ratified* +|*Zicfiss* |*1.0* |*Ratified* +|*Zicfilp* |*1.0* |*Ratified* |=== The changes in this version of the document include: diff --git a/src/example/sgemm.S b/src/example/sgemm.S index e29cc8d..0567bf6 100644 --- a/src/example/sgemm.S +++ b/src/example/sgemm.S @@ -73,7 +73,7 @@ c_row_loop: # Loop across rows of C blocks mv cnp, cp # Initialize C n-loop pointer c_col_loop: # Loop across one row of C blocks - vsetvli nvl, nt, e32, ta, ma # 32-bit vectors, LMUL=1 + vsetvli nvl, nt, e32, m1, ta, ma # 32-bit vectors, LMUL=1 mv akp, ap # reset pointer into A to beginning mv bkp, bnp # step to next column in B matrix diff --git a/src/example/vvaddint32.s b/src/example/vvaddint32.s index 22305d9..34d849b 100644 --- a/src/example/vvaddint32.s +++ b/src/example/vvaddint32.s @@ -8,7 +8,7 @@ # a0 = n, a1 = x, a2 = y, a3 = z # Non-vector instructions are indented vvaddint32: - vsetvli t0, a0, e32, ta, ma # Set vector length based on 32-bit vectors + vsetvli t0, a0, e32, m1, ta, ma # Set vector length based on 32-bit vectors vle32.v v0, (a1) # Get first vector sub a0, a0, t0 # Decrement number done slli t0, t0, 2 # Multiply number done by 4 bytes diff --git a/src/extending.adoc b/src/extending.adoc index 9124a26..6a322dc 100644 --- a/src/extending.adoc +++ b/src/extending.adoc @@ -31,7 +31,7 @@ categories: _standard_ versus _non-standard_. * A standard extension is one that is generally useful and that is designed to not conflict with any other standard extension. Currently, -"MAFDQLCBTPV", described in other chapters of this manual, are either +"MAFDQCBTPV", described in other chapters of this manual, are either complete or planned standard extensions. * A non-standard extension may be highly specialized and may conflict with other standard or non-standard extensions. We anticipate a wide diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 3a3a3a9..167a809 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -726,6 +726,9 @@ When XLEN=32, `htimedeltah` is a 32-bit read/write register that aliases bits 63:32 of `htimedelta`. Register `htimedeltah` does not exist when XLEN=64. +If the `time` CSR is implemented, `htimedelta` (and `htimedeltah` for XLEN=32) +must be implemented. + ==== Hypervisor Trap Value (`htval`) Register The `htval` register is an HSXLEN-bit read/write register formatted as @@ -935,7 +938,7 @@ in <<vsstatusreg-rv32>> when VSXLEN=32 and normally read or modify `sstatus` actually access `vsstatus` instead. [[vsstatusreg-rv32]] -.Virtual supervisor status (`vstatus`) register when VSXLEN=32. +.Virtual supervisor status (`vsstatus`) register when VSXLEN=32. [wavedrom, ,svg] .... {reg: [ @@ -2544,3 +2547,7 @@ privilege mode as previously determined, and sets `pc`=`sepc`. When executed in VS-mode (i.e., V=1), SRET sets the privilege mode according to <<h-vspp>>, in `vsstatus` sets SPP=0, SIE=SPIE, and SPIE=1, and lastly sets `pc`=`vsepc`. + +If the Ssdbltrp extension is implemented, when `SRET` is executed in HS-mode, +if the new privilege mode is VU, the `SRET` instruction sets `vsstatus.SDT` +to 0. When executed in VS-mode, `vsstatus.SDT` is set to 0. diff --git a/src/images/bytefield/hypv-miereg-standard.edn b/src/images/bytefield/hypv-miereg-standard.edn index 154983d..e2b60ab 100644 --- a/src/images/bytefield/hypv-miereg-standard.edn +++ b/src/images/bytefield/hypv-miereg-standard.edn @@ -8,9 +8,9 @@ (def boxes-per-row 32) (draw-box "15" {:borders {}}) -(draw-box nil {:span 2 :borders {}}) -(draw-box "13" {:borders {}}) -(draw-box "12" {:span 3 :borders {}}) +(draw-box "14" {:borders {}}) +(draw-box "13" {:span 3 :borders {}}) +(draw-box "12" {:span 2 :borders {}}) (draw-box "11" {:span 2 :borders {}}) (draw-box "10" {:span 3 :borders {}}) (draw-box "9" {:span 2 :borders {}}) @@ -24,8 +24,9 @@ (draw-box "1" {:span 2 :borders {}}) (draw-box "0" {:span 2 :borders {}}) -(draw-box "0" {:span 4}) -(draw-box "SGEIE" {:span 3}) +(draw-box "0" {:span 2}) +(draw-box "LCOFIE" {:span 3}) +(draw-box "SGEIE" {:span 2}) (draw-box "MEIE" {:span 2}) (draw-box "VSEIE" {:span 3}) (draw-box "SEIE" {:span 2}) @@ -39,8 +40,9 @@ (draw-box "SSIE" {:span 2}) (draw-box "0" {:span 2}) -(draw-box "3" {:span 4 :borders {}}) -(draw-box "1" {:span 3:borders {}}) +(draw-box "2" {:span 2 :borders {}}) +(draw-box "1" {:span 3 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 3 :borders {}}) (draw-box "1" {:span 2 :borders {}}) diff --git a/src/images/bytefield/hypv-mipreg-standard.edn b/src/images/bytefield/hypv-mipreg-standard.edn index c75ec02..f41a1ba 100644 --- a/src/images/bytefield/hypv-mipreg-standard.edn +++ b/src/images/bytefield/hypv-mipreg-standard.edn @@ -8,9 +8,9 @@ (def boxes-per-row 32) (draw-box "15" {:borders {}}) -(draw-box nil {:span 2 :borders {}}) -(draw-box "13" {:borders {}}) -(draw-box "12" {:span 3 :borders {}}) +(draw-box "14" {:borders {}}) +(draw-box "13" {:span 3 :borders {}}) +(draw-box "12" {:span 2 :borders {}}) (draw-box "11" {:span 2 :borders {}}) (draw-box "10" {:span 3 :borders {}}) (draw-box "9" {:span 2 :borders {}}) @@ -24,8 +24,9 @@ (draw-box "1" {:span 2 :borders {}}) (draw-box "0" {:span 2 :borders {}}) -(draw-box "0" {:span 4}) -(draw-box "SGEIP" {:span 3}) +(draw-box "0" {:span 2}) +(draw-box "LCOFIP" {:span 3}) +(draw-box "SGEIP" {:span 2}) (draw-box "MEIP" {:span 2}) (draw-box "VSEIP" {:span 3}) (draw-box "SEIP" {:span 2}) @@ -39,8 +40,9 @@ (draw-box "SSIP" {:span 2}) (draw-box "0" {:span 2}) -(draw-box "3" {:span 4 :borders {}}) -(draw-box "1" {:span 3:borders {}}) +(draw-box "2" {:span 2 :borders {}}) +(draw-box "1" {:span 3 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 3 :borders {}}) (draw-box "1" {:span 2 :borders {}}) diff --git a/src/images/bytefield/rvc-instr-quad1.adoc b/src/images/bytefield/rvc-instr-quad1.adoc index e0f6073..3aebd40 100644 --- a/src/images/bytefield/rvc-instr-quad1.adoc +++ b/src/images/bytefield/rvc-instr-quad1.adoc @@ -14,7 +14,7 @@ (draw-box "0" {:span 5}) (draw-box "imm[4:0]" {:span 5}) (draw-box "01" {:span 2}) -(draw-box (text "C.NOP" :math [:sub "(HINT, imm=0)"]) {:span 3 :text-anchor "start" :borders {}}) +(draw-box (text "C.NOP" :math [:sub "(HINT, imm≠0)"]) {:span 3 :text-anchor "start" :borders {}}) (draw-box "000" {:span 3}) (draw-box "imm[5]") {:span 1} diff --git a/src/images/wavedrom/atomic-mem.adoc b/src/images/wavedrom/atomic-mem.adoc index ef66028..1e95eb4 100644 --- a/src/images/wavedrom/atomic-mem.adoc +++ b/src/images/wavedrom/atomic-mem.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']}, - {bits: 5, name: 'rd', type: 2, attr: ['5','dest','dest','dest','dest','dest','dest','dest']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','width','width','width','width','width','width','width']}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','addr','addr','addr','addr','addr','addr','addr']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','src','src','src','src','src','src','src']}, - {bits: 1, name: 'rl', type: 8, attr: ['1']}, - {bits: 1, name: 'aq', type: 8, attr: ['1']}, - {bits: 6, name: 'funct5', type: 8, attr: ['5','AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D','AMOMIN[U].W/D']}, + {bits: 7, name: 'opcode', attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest','dest','dest','dest']}, + {bits: 3, name: 'funct3', attr: ['3','width','width','width','width','width','width','width']}, + {bits: 5, name: 'rs1', attr: ['5','addr','addr','addr','addr','addr','addr','addr']}, + {bits: 5, name: 'rs2', attr: ['5','src','src','src','src','src','src','src']}, + {bits: 1, name: 'rl', attr: ['1']}, + {bits: 1, name: 'aq', attr: ['1']}, + {bits: 6, name: 'funct5', attr: ['5','AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D','AMOMIN[U].W/D']}, ], config: {bits: 32}} .... diff --git a/src/images/wavedrom/c-andi.adoc b/src/images/wavedrom/c-andi.adoc index 5eca644..3ea3206 100644 --- a/src/images/wavedrom/c-andi.adoc +++ b/src/images/wavedrom/c-andi.adoc @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 5, attr: ['2','C1'],}, - {bits: 5, name: 'imm[4:0]', type: 5, attr: ['5','imm[4:0]']}, - {bits: 3, name: 'rd′/rs1′', type: 5, attr: ['3','dest'],}, - {bits: 2, name: 'funct2', type: 5, attr: ['2','C.ANDI'],}, - {bits: 1, name: 'imm[5]', type: 1, attr: ['1','imm[5]'],}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.ANDI'],}, + {bits: 2, name: 'op', attr: ['2','C1'],}, + {bits: 5, name: 'imm[4:0]', attr: ['5','imm[4:0]']}, + {bits: 3, name: 'rd′/rs1′', attr: ['3','dest'],}, + {bits: 2, name: 'funct2', attr: ['2','C.ANDI'],}, + {bits: 1, name: 'imm[5]', attr: ['1','imm[5]'],}, + {bits: 3, name: 'funct3', attr: ['3','C.ANDI'],}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/c-breakpoint-instr.adoc b/src/images/wavedrom/c-breakpoint-instr.adoc index 99ae2d5..6ae1890 100644 --- a/src/images/wavedrom/c-breakpoint-instr.adoc +++ b/src/images/wavedrom/c-breakpoint-instr.adoc @@ -4,8 +4,8 @@ .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C2'],}, - {bits: 10, name: '0', type: 4, attr: ['10','0'],}, - {bits: 4, name: 'funct4', type: 8, attr: ['4','C.EBREAK'],}, + {bits: 2, name: 'op', attr: ['2','C2'],}, + {bits: 10, name: '0', attr: ['10','0'],}, + {bits: 4, name: 'funct4', attr: ['4','C.EBREAK'],}, ], config: {bits: 16}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/c-cb-format-ls.adoc b/src/images/wavedrom/c-cb-format-ls.adoc index daf2248..5c90133 100644 --- a/src/images/wavedrom/c-cb-format-ls.adoc +++ b/src/images/wavedrom/c-cb-format-ls.adoc @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C1', 'C1']}, - {bits: 5, name: 'imm', type: 3, attr: ['5','offset[7:6|2:1|5]', 'offset[7:6|2:1|5]']}, - {bits: 3, name: 'rs1′', type: 4, attr: ['3','src', 'src']}, - {bits: 3, name: 'imm', type: 3, attr: ['3','offset[8|4:3]', 'offset[8|4:3]'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','C.BEQZ', 'C.BNEZ'],}, + {bits: 2, name: 'op', attr: ['2','C1', 'C1']}, + {bits: 5, name: 'imm', attr: ['5','offset[7:6|2:1|5]', 'offset[7:6|2:1|5]']}, + {bits: 3, name: 'rs1′', attr: ['3','src', 'src']}, + {bits: 3, name: 'imm', attr: ['3','offset[8|4:3]', 'offset[8|4:3]'],}, + {bits: 3, name: 'funct3', attr: ['3','C.BEQZ', 'C.BNEZ'],}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-ci.adoc b/src/images/wavedrom/c-ci.adoc index 7dae51e..aacf2be 100644 --- a/src/images/wavedrom/c-ci.adoc +++ b/src/images/wavedrom/c-ci.adoc @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2', 'C2']}, - {bits: 5, name: 'shamt[4:0]', type: 1, attr: ['5', 'shamt[4:0]']}, - {bits: 5, name: 'rd/rs1', type: 5, attr: ['5', 'dest != 0']}, - {bits: 1, name: 'shamt[5]', type: 5, attr: ['1', 'shamt[5]']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3', 'C.SLLI']}, + {bits: 2, name: 'op', attr: ['2', 'C2']}, + {bits: 5, name: 'shamt[4:0]', attr: ['5', 'shamt[4:0]']}, + {bits: 5, name: 'rd/rs1', attr: ['5', 'dest != 0']}, + {bits: 1, name: 'shamt[5]', attr: ['1', 'shamt[5]']}, + {bits: 3, name: 'funct3', attr: ['3', 'C.SLLI']}, ]} .... diff --git a/src/images/wavedrom/c-ciw.adoc b/src/images/wavedrom/c-ciw.adoc index 111b272..b167e1f 100644 --- a/src/images/wavedrom/c-ciw.adoc +++ b/src/images/wavedrom/c-ciw.adoc @@ -3,10 +3,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2','C0'],}, - {bits: 3, name: 'rd′', type: 5, attr: ['3','dest'],}, - {bits: 8, name: 'imm', type: 5, attr: ['8','nzuimm[5:4|9:6|2|3]']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.ADDI4SPN']}, + {bits: 2, name: 'op', attr: ['2','C0'],}, + {bits: 3, name: 'rd′', attr: ['3','dest'],}, + {bits: 8, name: 'imm', attr: ['8','nzuimm[5:4|9:6|2|3]']}, + {bits: 3, name: 'funct3', attr: ['3','C.ADDI4SPN']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-cj-format-ls.adoc b/src/images/wavedrom/c-cj-format-ls.adoc index 1ecbd35..d5fa6d1 100644 --- a/src/images/wavedrom/c-cj-format-ls.adoc +++ b/src/images/wavedrom/c-cj-format-ls.adoc @@ -3,9 +3,9 @@ //[wavedrom, ,svg] //.... //{reg: [ -// {bits: 2, name: 'op', type: 4, attr: ['2','CI','CI']}, -// {bits: 10, name: 'imm', type: 2, }, -// {bits: 4, name: 'funct3' type: 4, attr:['3','CJ','CJAL']}, +// {bits: 2, name: 'op', attr: ['2','CI','CI']}, +// {bits: 10, name: 'imm'}, +// {bits: 4, name: 'funct3' attr:['3','CJ','CJAL']}, //] config: {bits: 16}} //.... @@ -13,9 +13,9 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C1','C1']}, - {bits: 11, name: 'imm', type: 2, attr: ['11','offset[11|4|9:8|10|6|7|3:1|5]','offset[11|4|9:8|10|6|7|3:1|5]']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','C.J','C.JAL']}, + {bits: 2, name: 'op', attr: ['2','C1','C1']}, + {bits: 11, name: 'imm', attr: ['11','offset[11|4|9:8|10|6|7|3:1|5]','offset[11|4|9:8|10|6|7|3:1|5]']}, + {bits: 3, name: 'funct3', attr: ['3','C.J','C.JAL']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-cr-format-ls.adoc b/src/images/wavedrom/c-cr-format-ls.adoc index 0329261..b989e2c 100644 --- a/src/images/wavedrom/c-cr-format-ls.adoc +++ b/src/images/wavedrom/c-cr-format-ls.adoc @@ -3,10 +3,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C2', 'C2']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','0', '0']}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','src≠0', 'src≠0']}, - {bits: 4, name: 'funct4', type: 8, attr: ['4','C.JR', 'C.JALR']}, + {bits: 2, name: 'op', attr: ['2','C2', 'C2']}, + {bits: 5, name: 'rs2', attr: ['5','0', '0']}, + {bits: 5, name: 'rs1', attr: ['5','src≠0', 'src≠0']}, + {bits: 4, name: 'funct4', attr: ['4','C.JR', 'C.JALR']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-cs-format-ls.adoc b/src/images/wavedrom/c-cs-format-ls.adoc index 1f759a7..31f4ccf 100644 --- a/src/images/wavedrom/c-cs-format-ls.adoc +++ b/src/images/wavedrom/c-cs-format-ls.adoc @@ -4,12 +4,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2', 'C0','C0','C0','C0','C0']}, - {bits: 3, name: 'rs2ʹ', type: 3, attr: ['3', 'src','src','src','src','src']}, - {bits: 2, name: 'imm', type: 2, attr: ['2', 'offset[2|6]','offset[7:6]','offset[7:6]','offset[2|6]','offset[7:6]']}, - {bits: 3, name: 'rs1ʹ', type: 3, attr: ['3', 'base','base','base','base','base']}, - {bits: 3, name: 'imm', type: 3, attr: ['3', 'offset[5:3]','offset[5:3]','offset[5|4|8]','offset[5:3]','offset[5:3]']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3', 'C.SW','C.SD','C.SQ','C.FSW','C.FSD']}, + {bits: 2, name: 'op', attr: ['2', 'C0','C0','C0','C0','C0']}, + {bits: 3, name: 'rs2ʹ', attr: ['3', 'src','src','src','src','src']}, + {bits: 2, name: 'imm', attr: ['2', 'offset[2|6]','offset[7:6]','offset[7:6]','offset[2|6]','offset[7:6]']}, + {bits: 3, name: 'rs1ʹ', attr: ['3', 'base','base','base','base','base']}, + {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]','offset[5:3]','offset[5|4|8]','offset[5:3]','offset[5:3]']}, + {bits: 3, name: 'funct3', attr: ['3', 'C.SW','C.SD','C.SQ','C.FSW','C.FSD']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-def-illegal-inst.adoc b/src/images/wavedrom/c-def-illegal-inst.adoc index add949d..414a19e 100644 --- a/src/images/wavedrom/c-def-illegal-inst.adoc +++ b/src/images/wavedrom/c-def-illegal-inst.adoc @@ -4,10 +4,10 @@ .... {reg: [ - {bits: 2, name: '0', type: 8, attr: ['2','0'],}, - {bits: 5, name: '0', type: 4, attr: ['5','0'],}, - {bits: 5, name: '0', type: 8, attr: ['5','0'],}, - {bits: 1, name: '0', type: 8, attr: ['1','0'],}, - {bits: 3, name: '0', type: 8, attr: ['3','0'],}, + {bits: 2, name: '0', attr: ['2','0'],}, + {bits: 5, name: '0', attr: ['5','0'],}, + {bits: 5, name: '0', attr: ['5','0'],}, + {bits: 1, name: '0', attr: ['1','0'],}, + {bits: 3, name: '0', attr: ['3','0'],}, ], config: {bits: 16}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/c-int-reg-immed.adoc b/src/images/wavedrom/c-int-reg-immed.adoc index 45168d7..f509065 100644 --- a/src/images/wavedrom/c-int-reg-immed.adoc +++ b/src/images/wavedrom/c-int-reg-immed.adoc @@ -3,10 +3,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1', 'C1']}, - {bits: 5, name: 'imm[4:]', type: 1, attr: ['5','nzimm[4:0]', 'imm[4:0]', 'nzimm[4|6|8:7|5]']}, - {bits: 5, name: 'rd/rs1', type: 5, attr: ['5','dest != 0', 'dest != 0', '2']}, - {bits: 1, name: 'imm[5]', type: 5, attr: ['1','nzimm[5]', 'imm[5]', 'nzimm[9]']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.ADDI', 'C.ADDIW', 'C.ADDI16SP']}, + {bits: 2, name: 'op', attr: ['2','C1', 'C1', 'C1']}, + {bits: 5, name: 'imm[4:]', attr: ['5','nzimm[4:0]', 'imm[4:0]', 'nzimm[4|6|8:7|5]']}, + {bits: 5, name: 'rd/rs1', attr: ['5','dest != 0', 'dest != 0', '2']}, + {bits: 1, name: 'imm[5]', attr: ['1','nzimm[5]', 'imm[5]', 'nzimm[9]']}, + {bits: 3, name: 'funct3', attr: ['3','C.ADDI', 'C.ADDIW', 'C.ADDI16SP']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc index b2cf982..67e77b0 100644 --- a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc +++ b/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc @@ -4,10 +4,10 @@ .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2', 'C1', 'C1', 'C1', 'C1', 'C1', 'C1'],}, - {bits: 3, name: 'rs2′', type: 4, attr: ['3', 'src', 'src', 'src', 'src', 'src', 'src'],}, - {bits: 2, name: 'funct2', type: 8, attr: ['2', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, - {bits: 3, name: 'rd′/rs1′', type: 7, attr: ['3', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'],}, - {bits: 6, name: 'funct6', type: 8, attr: ['6', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, + {bits: 2, name: 'op', attr: ['2', 'C1', 'C1', 'C1', 'C1', 'C1', 'C1'],}, + {bits: 3, name: 'rs2′', attr: ['3', 'src', 'src', 'src', 'src', 'src', 'src'],}, + {bits: 2, name: 'funct2', attr: ['2', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, + {bits: 3, name: 'rd′/rs1′', attr: ['3', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'],}, + {bits: 6, name: 'funct6', attr: ['6', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc index 5e607f8..ddfa0f8 100644 --- a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc +++ b/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc @@ -4,9 +4,9 @@ .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2', 'C2', 'C2'],}, - {bits: 5, name: 'rs2', type: 4, attr: ['5', 'src≠0', 'src≠0'],}, - {bits: 5, name: 'rd/rs1', type: 7, attr: ['5', 'dest≠0', 'dest≠0'],}, - {bits: 4, name: 'funct4', type: 8, attr: ['4', 'C.MV', 'C.ADD'],}, + {bits: 2, name: 'op', attr: ['2', 'C2', 'C2'],}, + {bits: 5, name: 'rs2', attr: ['5', 'src≠0', 'src≠0'],}, + {bits: 5, name: 'rd/rs1', attr: ['5', 'dest≠0', 'dest≠0'],}, + {bits: 4, name: 'funct4', attr: ['4', 'C.MV', 'C.ADD'],}, ], config: {bits: 16}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/c-integer-const-gen.adoc b/src/images/wavedrom/c-integer-const-gen.adoc index 732961b..b6ae85b 100644 --- a/src/images/wavedrom/c-integer-const-gen.adoc +++ b/src/images/wavedrom/c-integer-const-gen.adoc @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1']}, - {bits: 5, name: 'imm[4:0]', type: 1, attr: ['5','imm[4:0]','imm[16:12]']}, - {bits: 5, name: 'rd', type: 5, attr: ['5','dest != 0', 'dest != {0, 2}']}, - {bits: 1, name: 'imm[5]', type: 5, attr: ['1','imm[5]', 'nzimm[17]'],}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.LI', 'C.LUI'],}, + {bits: 2, name: 'op', attr: ['2','C1', 'C1']}, + {bits: 5, name: 'imm[4:0]', attr: ['5','imm[4:0]','imm[16:12]']}, + {bits: 5, name: 'rd', attr: ['5','dest != 0', 'dest != {0, 2}']}, + {bits: 1, name: 'imm[5]', attr: ['1','imm[5]', 'nzimm[17]'],}, + {bits: 3, name: 'funct3', attr: ['3','C.LI', 'C.LUI'],}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-mop.adoc b/src/images/wavedrom/c-mop.adoc index 0aee8e4..9b850a5 100644 --- a/src/images/wavedrom/c-mop.adoc +++ b/src/images/wavedrom/c-mop.adoc @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg:[ - { bits: 2, name: 0x1, type: 8 }, + { bits: 2, name: 0x1 }, { bits: 5, name: 0x0 }, - { bits: 1, name: 0x1, type: 4 }, - { bits: 3, name: 'n[3:1]', type: 4 }, - { bits: 1, name: 0x0, type: 4 }, + { bits: 1, name: 0x1 }, + { bits: 3, name: 'n[3:1]' }, + { bits: 1, name: 0x0 }, { bits: 1, name: 0x0 }, { bits: 3, name: 0x3 }, ]} diff --git a/src/images/wavedrom/c-nop-instr.adoc b/src/images/wavedrom/c-nop-instr.adoc index e3fada1..89da752 100644 --- a/src/images/wavedrom/c-nop-instr.adoc +++ b/src/images/wavedrom/c-nop-instr.adoc @@ -4,10 +4,10 @@ .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C1'],}, - {bits: 5, name: 'imm[4:0]', type: 4, attr: ['5','0'],}, - {bits: 5, name: 'rd/rs1', type: 8, attr: ['5','0'],}, - {bits: 1, name: 'imm[5]', type: 8, attr: ['1','0'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','C.NOP'],}, + {bits: 2, name: 'op', attr: ['2','C1'],}, + {bits: 5, name: 'imm[4:0]', attr: ['5','0'],}, + {bits: 5, name: 'rd/rs1', attr: ['5','0'],}, + {bits: 1, name: 'imm[5]', attr: ['1','0'],}, + {bits: 3, name: 'funct3', attr: ['3','C.NOP'],}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/c-sp-load-store-css.adoc b/src/images/wavedrom/c-sp-load-store-css.adoc index 2cafcd8..a398c7f 100644 --- a/src/images/wavedrom/c-sp-load-store-css.adoc +++ b/src/images/wavedrom/c-sp-load-store-css.adoc @@ -3,10 +3,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C2','C2','C2','C2','C2']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','src', 'src', 'src', 'src', 'src']}, - {bits: 6, name: 'imm', type: 3, attr: ['6','offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']}, + {bits: 2, name: 'op', attr: ['2','C2','C2','C2','C2','C2']}, + {bits: 5, name: 'rs2', attr: ['5','src', 'src', 'src', 'src', 'src']}, + {bits: 6, name: 'imm', attr: ['6','offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']}, + {bits: 3, name: 'funct3', attr: ['3','C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.adoc index c39f2f6..f890ac8 100644 --- a/src/images/wavedrom/c-sp-load-store.adoc +++ b/src/images/wavedrom/c-sp-load-store.adoc @@ -4,11 +4,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C2','C2','C2','C2','C2']}, - {bits: 5, name: 'imm', type: 5, attr: ['5','offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']}, - {bits: 5, name: 'rd', type: 5, attr: ['5','dest≠0', 'dest≠0', 'dest≠0', 'dest', 'dest']}, - {bits: 1, name: 'imm', type: 1, attr: ['1','offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']}, - {bits: 3, name: 'funct3', type: 3, attr: ['3','C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']}, + {bits: 2, name: 'op', attr: ['2','C2','C2','C2','C2','C2']}, + {bits: 5, name: 'imm', attr: ['5','offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']}, + {bits: 5, name: 'rd', attr: ['5','dest≠0', 'dest≠0', 'dest≠0', 'dest', 'dest']}, + {bits: 1, name: 'imm', attr: ['1','offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']}, + {bits: 3, name: 'funct3', attr: ['3','C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/c-srli-srai.adoc b/src/images/wavedrom/c-srli-srai.adoc index 557bb39..78a1076 100644 --- a/src/images/wavedrom/c-srli-srai.adoc +++ b/src/images/wavedrom/c-srli-srai.adoc @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1'],}, - {bits: 5, name: 'shamt[4:0]', type: 1, attr: ['5','shamt[4:0]', 'shamt[4:0]'],}, - {bits: 3, name: 'rd′/rs1′', type: 5, attr: ['3','dest', 'dest'],}, - {bits: 2, name: 'funct2', type: 5, attr: ['2','C.SRLI', 'C.SRAI'],}, - {bits: 1, name: 'shamt[5]', type: 5, attr: ['1','shamt[5]', 'shamt[5]'],}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.SRLI', 'C.SRAI'],}, + {bits: 2, name: 'op', attr: ['2','C1', 'C1'],}, + {bits: 5, name: 'shamt[4:0]', attr: ['5','shamt[4:0]', 'shamt[4:0]'],}, + {bits: 3, name: 'rd′/rs1′', attr: ['3','dest', 'dest'],}, + {bits: 2, name: 'funct2', attr: ['2','C.SRLI', 'C.SRAI'],}, + {bits: 1, name: 'shamt[5]', attr: ['1','shamt[5]', 'shamt[5]'],}, + {bits: 3, name: 'funct3', attr: ['3','C.SRLI', 'C.SRAI'],}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/counters-diag.adoc b/src/images/wavedrom/counters-diag.adoc index 8668162..a29d567 100644 --- a/src/images/wavedrom/counters-diag.adoc +++ b/src/images/wavedrom/counters-diag.adoc @@ -4,11 +4,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3','CSRRS','CSRRS','CSRRS'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','0','0','0'], type: 8}, - {bits: 12, name: 'csr', attr: ['12','RDCYCLE[H]', 'RDTIME[H]','RDINSTRET[H]'], type: 4}, + {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest']}, + {bits: 3, name: 'funct3', attr: ['3','CSRRS','CSRRS','CSRRS']}, + {bits: 5, name: 'rs1', attr: ['5','0','0','0']}, + {bits: 12, name: 'csr', attr: ['12','RDCYCLE[H]', 'RDTIME[H]','RDINSTRET[H]']}, ]} .... diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.adoc index 63286e4..30ad1b3 100644 --- a/src/images/wavedrom/cr-register.adoc +++ b/src/images/wavedrom/cr-register.adoc @@ -6,96 +6,96 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 5, name: 'rd/rs1', type: 7}, - {bits: 4, name: 'funct4', type: 8}, + {bits: 2, name: 'op' }, + {bits: 5, name: 'rs2' }, + {bits: 5, name: 'rd/rs1' }, + {bits: 4, name: 'funct4' }, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'imm', type: 3}, - {bits: 5, name: 'rd/rs1', type: 7}, - {bits: 1, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, + {bits: 2, name: 'op' }, + {bits: 5, name: 'imm' }, + {bits: 5, name: 'rd/rs1' }, + {bits: 1, name: 'imm' }, + {bits: 3, name: 'funct3' }, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 6, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, + {bits: 2, name: 'op' }, + {bits: 5, name: 'rs2' }, + {bits: 6, name: 'imm' }, + {bits: 3, name: 'funct3' }, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rdʹ', type: 2}, - {bits: 8, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, + {bits: 2, name: 'op' }, + {bits: 3, name: 'rdʹ' }, + {bits: 8, name: 'imm' }, + {bits: 3, name: 'funct3' }, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rdʹ', type: 2}, - {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1ʹ', type: 4}, - {bits: 3, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, + {bits: 2, name: 'op' }, + {bits: 3, name: 'rdʹ' }, + {bits: 2, name: 'imm' }, + {bits: 3, name: 'rs1ʹ' }, + {bits: 3, name: 'imm' }, + {bits: 3, name: 'funct3' }, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2ʹ', type: 4}, - {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1ʹ', type: 4}, - {bits: 3, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, + {bits: 2, name: 'op' }, + {bits: 3, name: 'rs2ʹ' }, + {bits: 2, name: 'imm' }, + {bits: 3, name: 'rs1ʹ' }, + {bits: 3, name: 'imm' }, + {bits: 3, name: 'funct3' }, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2ʹ', type: 4}, - {bits: 2, name: 'funct2', type: 8}, - {bits: 3, name: 'rdʹ/rs1ʹ', type: 7}, - {bits: 6, name: 'funct6', type: 8}, + {bits: 2, name: 'op' }, + {bits: 3, name: 'rs2ʹ' }, + {bits: 2, name: 'funct2' }, + {bits: 3, name: 'rdʹ/rs1ʹ' }, + {bits: 6, name: 'funct6' }, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'offset', type: 3}, - {bits: 3, name: 'rdʹ/rs1ʹ', type: 7}, - {bits: 3, name: 'offset', type: 3}, - {bits: 3, name: 'funct3', type: 8}, + {bits: 2, name: 'op' }, + {bits: 5, name: 'offset' }, + {bits: 3, name: 'rdʹ/rs1ʹ' }, + {bits: 3, name: 'offset' }, + {bits: 3, name: 'funct3' }, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 11, name: 'jmp trgt', type: 3}, - {bits: 3, name: 'funct3', type: 8}, + {bits: 2, name: 'op' }, + {bits: 11, name: 'jmp trgt' }, + {bits: 3, name: 'funct3' }, ]} .... diff --git a/src/images/wavedrom/cr-registers-new.adoc b/src/images/wavedrom/cr-registers-new.adoc index 46a34e6..05331c8 100644 --- a/src/images/wavedrom/cr-registers-new.adoc +++ b/src/images/wavedrom/cr-registers-new.adoc @@ -2,56 +2,56 @@ .... ### CR : Register ${wd({reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 5, name: 'rd / rs1ʹ, type: 7}, - {bits: 4, name: 'funct4', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'imm', type: 3}, - {bits: 5, name: 'rd / rs1', type: 7}, - {bits: 1, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 6, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rdʹ', type: 2}, - {bits: 8, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rdʹ', type: 2}, - {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1ʹ', type: 4}, - {bits: 3, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2ʹ', type: 4}, - {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1ʹ', type: 4}, - {bits: 3, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2ʹ', type: 4}, - {bits: 2, name: 'funct2', type: 8}, - {bits: 3, name: 'rd` / rs1ʹ', type: 7}, - {bits: 6, name: 'funct6', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'offset', type: 3}, - {bits: 3, name: 'rd` / rs1ʹ', type: 7}, - {bits: 3, name: 'offset', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 11, name: 'jump target', type: 3}, - {bits: 3, name: 'funct3', type: 8}, + {bits: 2, name: 'op' }, + {bits: 5, name: 'rs2' }, + {bits: 5, name: 'rd / rs1ʹ }, + {bits: 4, name: 'funct4' }, + + {bits: 2, name: 'op' }, + {bits: 5, name: 'imm' }, + {bits: 5, name: 'rd / rs1' }, + {bits: 1, name: 'imm' }, + {bits: 3, name: 'funct3' }, + + {bits: 2, name: 'op' }, + {bits: 5, name: 'rs2' }, + {bits: 6, name: 'imm' }, + {bits: 3, name: 'funct3' }, + + {bits: 2, name: 'op' }, + {bits: 3, name: 'rdʹ' }, + {bits: 8, name: 'imm' }, + {bits: 3, name: 'funct3' }, + + {bits: 2, name: 'op' }, + {bits: 3, name: 'rdʹ' }, + {bits: 2, name: 'imm' }, + {bits: 3, name: 'rs1ʹ' }, + {bits: 3, name: 'imm' }, + {bits: 3, name: 'funct3' }, + + {bits: 2, name: 'op' }, + {bits: 3, name: 'rs2ʹ' }, + {bits: 2, name: 'imm' }, + {bits: 3, name: 'rs1ʹ' }, + {bits: 3, name: 'imm' }, + {bits: 3, name: 'funct3' }, + + {bits: 2, name: 'op' }, + {bits: 3, name: 'rs2ʹ' }, + {bits: 2, name: 'funct2' }, + {bits: 3, name: 'rd` / rs1ʹ' }, + {bits: 6, name: 'funct6' }, + + {bits: 2, name: 'op' }, + {bits: 5, name: 'offset' }, + {bits: 3, name: 'rd` / rs1ʹ' }, + {bits: 3, name: 'offset' }, + {bits: 3, name: 'funct3' }, + + {bits: 2, name: 'op' }, + {bits: 11, name: 'jump target' }, + {bits: 3, name: 'funct3' }, ], config: { hflip: true, compact: true, diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.adoc index 93022be..19d853e 100644 --- a/src/images/wavedrom/csr-instr.adoc +++ b/src/images/wavedrom/csr-instr.adoc @@ -1,24 +1,24 @@ //# 10 "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 -//## 10.1 CSR Instructions +//## 10.1 CSR Instructions [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'], type: 4}, - {bits: 12, name: 'csr', attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], type: 4}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'] }, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'] }, + {bits: 3, name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'] }, + {bits: 5, name: 'rs1', attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'] }, + {bits: 12, name: 'csr', attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], }, ]} .... //[wavedrom, ,] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'], type: 8}, -// {bits: 5, name: 'rd', attr: ['3', 'dest','dest', 'dest' ], type: 2}, -// {bits: 3, name: 'funct3', attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8}, -// {bits: 5, name: 'rs1', attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'], type: 3}, -// {bits: 12, name: 'csr', attr: ['12', 'source/dest','source/dest','source/dest'], type: 4}, +// {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'] }, +// {bits: 5, name: 'rd', attr: ['3', 'dest','dest', 'dest' ] }, +// {bits: 3, name: 'funct3', attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'] }, +// {bits: 5, name: 'rs1', attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'] }, +// {bits: 12, name: 'csr', attr: ['12', 'source/dest','source/dest','source/dest'] }, //]} //.... diff --git a/src/images/wavedrom/ct-conditional.adoc b/src/images/wavedrom/ct-conditional.adoc index b886d7c..e021907 100644 --- a/src/images/wavedrom/ct-conditional.adoc +++ b/src/images/wavedrom/ct-conditional.adoc @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'BRANCH', 'BRANCH', 'BRANCH'], type: 8}, - {bits: 5, name: 'imm[4:1|11]', attr: ['5', 'offset[4:1|11]', 'offset[4:1|11]', 'offset[4:1|11]'], type: 3}, - {bits: 3, name: 'funct3', attr: ['3', 'BEQ/BNE', 'BLT[U]', 'BGE[U]'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src2','src2', 'src2'], type: 4}, - {bits: 7, name: 'imm[12|10:5]', attr: ['7', 'offset[12|10:5]', 'offset[12|10:5]', 'offset[12|10:5]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'BRANCH', 'BRANCH', 'BRANCH'] }, + {bits: 5, name: 'imm[4:1|11]', attr: ['5', 'offset[4:1|11]', 'offset[4:1|11]', 'offset[4:1|11]'] }, + {bits: 3, name: 'funct3', attr: ['3', 'BEQ/BNE', 'BLT[U]', 'BGE[U]'] }, + {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1'] }, + {bits: 5, name: 'rs2', attr: ['5', 'src2','src2', 'src2'] }, + {bits: 7, name: 'imm[12|10:5]', attr: ['7', 'offset[12|10:5]', 'offset[12|10:5]', 'offset[12|10:5]'] }, ], config:{fontsize: 10}} .... diff --git a/src/images/wavedrom/ct-unconditional-2.adoc b/src/images/wavedrom/ct-unconditional-2.adoc index 4dda824..95f103e 100644 --- a/src/images/wavedrom/ct-unconditional-2.adoc +++ b/src/images/wavedrom/ct-unconditional-2.adoc @@ -3,10 +3,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'JALR'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', '0'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'JALR'] }, + {bits: 5, name: 'rd', attr: ['5', 'dest'] }, + {bits: 3, name: 'funct3', attr: ['3', '0'] }, + {bits: 5, name: 'rs1', attr: ['5', 'base'] }, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'] }, ]} .... diff --git a/src/images/wavedrom/ct-unconditional.adoc b/src/images/wavedrom/ct-unconditional.adoc index 756108f..3dfbd94 100644 --- a/src/images/wavedrom/ct-unconditional.adoc +++ b/src/images/wavedrom/ct-unconditional.adoc @@ -4,12 +4,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'JAL'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 8, name: 'imm[19:12]', attr: ['8'], type: 3}, - {bits: 1, name: '[11]', attr: ['1'], type: 3}, - {bits: 10, name: 'imm[10:1]', attr: ['10', 'offset[20:1]'], type: 3}, - {bits: 1, name: '[20]', attr: ['1'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'JAL']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 8, name: 'imm[19:12]', attr: ['8']}, + {bits: 1, name: '[11]', attr: ['1']}, + {bits: 10, name: 'imm[10:1]', attr: ['10', 'offset[20:1]']}, + {bits: 1, name: '[20]', attr: ['1']}, ], config:{fontsize: 12}} .... diff --git a/src/images/wavedrom/d-xwwx.adoc b/src/images/wavedrom/d-xwwx.adoc index 5965715..e5fb261 100644 --- a/src/images/wavedrom/d-xwwx.adoc +++ b/src/images/wavedrom/d-xwwx.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','000','000'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FMV.X.D','FMV.D.X'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','000','000']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','0','0']}, + {bits: 2, name: 'fmt', attr: ['2','D','D']}, + {bits: 5, name: 'funct5', attr: ['5','FMV.X.D','FMV.D.X']}, ]} .... diff --git a/src/images/wavedrom/division-op.adoc b/src/images/wavedrom/division-op.adoc index fabdac1..0dff0e3 100644 --- a/src/images/wavedrom/division-op.adoc +++ b/src/images/wavedrom/division-op.adoc @@ -3,23 +3,23 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3','DIV[U]/REM[U]', 'DIV[U]W/REM[U]W'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'dividend', 'dividend'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'divisor', 'divisor'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3','DIV[U]/REM[U]', 'DIV[U]W/REM[U]W']}, + {bits: 5, name: 'rs1', attr: ['5', 'dividend', 'dividend']}, + {bits: 5, name: 'rs2', attr: ['5', 'divisor', 'divisor']}, + {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']}, ]} .... //[wavedrom, ,svg] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-32', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'dividend', type: 4}, -// {bits: 5, name: 'rs2', attr: 'divisor', type: 4}, -// {bits: 7, name: 'funct7', attr: 'MULDIV', type: 8}, +// {bits: 7, name: 'opcode', attr: 'OP-32'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW']}, +// {bits: 5, name: 'rs1', attr: 'dividend'}, +// {bits: 5, name: 'rs2', attr: 'divisor'}, +// {bits: 7, name: 'funct7', attr: 'MULDIV'}, //]} //.... diff --git a/src/images/wavedrom/double-fl-class.adoc b/src/images/wavedrom/double-fl-class.adoc index 143ff5e..2779d1a 100644 --- a/src/images/wavedrom/double-fl-class.adoc +++ b/src/images/wavedrom/double-fl-class.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','1'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','1']}, + {bits: 5, name: 'rs1', attr: ['5','src']}, + {bits: 5, name: 'rs2', attr: ['5','0']}, + {bits: 2, name: 'fmt', attr: ['2','D']}, + {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, ]} .... diff --git a/src/images/wavedrom/double-fl-compare.adoc b/src/images/wavedrom/double-fl-compare.adoc index 8403734..550bb00 100644 --- a/src/images/wavedrom/double-fl-compare.adoc +++ b/src/images/wavedrom/double-fl-compare.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','D']}, + {bits: 5, name: 'funct5', attr: ['5','FCMP']}, ]} .... diff --git a/src/images/wavedrom/double-fl-compute.adoc b/src/images/wavedrom/double-fl-compute.adoc index 4ce3b71..8f3922d 100644 --- a/src/images/wavedrom/double-fl-compute.adoc +++ b/src/images/wavedrom/double-fl-compute.adoc @@ -3,52 +3,52 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D','D','D','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src']}, + {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0']}, + {bits: 2, name: 'fmt', attr: ['2','D','D','D','D']}, + {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D'], type: 8}, - {bits: 5, name: 'rs3', attr: ['5','src3'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','D']}, + {bits: 5, name: 'rs3', attr: ['5','src3']}, ]} .... //[wavedrom, ,] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['MIN', 'MAX'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 2, name: 'fmt', attr: 'D', type: 8}, -// {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8}, +// {bits: 7, name: 'opcode', attr: 'OP-FP'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: ['MIN', 'MAX']}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 2, name: 'fmt', attr: 'D'}, +// {bits: 5, name: 'funct5', attr: 'FMIN-MAX'}, //]} //.... //[wavedrom, ,] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: 'RM', type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 2, name: 'fmt', attr: 'D', type: 8}, -// {bits: 5, name: 'rs3', attr: 'src3', type: 4}, +// {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: 'RM'}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 2, name: 'fmt', attr: 'D'}, +// {bits: 5, name: 'rs3', attr: 'src3'}, //]} //.... diff --git a/src/images/wavedrom/double-fl-convert-mv.adoc b/src/images/wavedrom/double-fl-convert-mv.adoc index fb23b08..15222d3 100644 --- a/src/images/wavedrom/double-fl-convert-mv.adoc +++ b/src/images/wavedrom/double-fl-convert-mv.adoc @@ -4,13 +4,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.int.D','FCVT.D.int'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]']}, + {bits: 2, name: 'fmt', attr: ['2','D','D']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.int.D','FCVT.D.int']}, ]} .... diff --git a/src/images/wavedrom/double-ls.adoc b/src/images/wavedrom/double-ls.adoc index 0c6f4dd..0191a0c 100644 --- a/src/images/wavedrom/double-ls.adoc +++ b/src/images/wavedrom/double-ls.adoc @@ -4,23 +4,23 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','LOAD-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'width', attr: ['3','D'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7','LOAD-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'width', attr: ['3','D']}, + {bits: 5, name: 'rs1', attr: ['5','base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]']}, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','STORE-FP'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]'], type: 3}, - {bits: 3, name: 'width', attr: ['3','D'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7','STORE-FP']}, + {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]']}, + {bits: 3, name: 'width', attr: ['3','D']}, + {bits: 5, name: 'rs1', attr: ['5','base']}, + {bits: 5, name: 'rs2', attr: ['5','src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]']}, ]} .... diff --git a/src/images/wavedrom/env_call-breakpoint.adoc b/src/images/wavedrom/env_call-breakpoint.adoc index 7812687..5814faf 100644 --- a/src/images/wavedrom/env_call-breakpoint.adoc +++ b/src/images/wavedrom/env_call-breakpoint.adoc @@ -3,10 +3,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0', '0'], type: 4}, - {bits: 12, name: 'func12', attr: ['12', 'ECALL', 'EBREAK'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', '0', '0']}, + {bits: 12, name: 'func12', attr: ['12', 'ECALL', 'EBREAK']}, ]} .... diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc b/src/images/wavedrom/fcvt-sd-ds.adoc index 5b68a54..a192ffa 100644 --- a/src/images/wavedrom/fcvt-sd-ds.adoc +++ b/src/images/wavedrom/fcvt-sd-ds.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','D', 'S'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.S.D', 'FCVT.D.S'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','D', 'S']}, + {bits: 2, name: 'fmt', attr: ['2','S','D']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.S.D', 'FCVT.D.S']}, ]} .... diff --git a/src/images/wavedrom/float-csr.adoc b/src/images/wavedrom/float-csr.adoc index 7b2cf24..56be164 100644 --- a/src/images/wavedrom/float-csr.adoc +++ b/src/images/wavedrom/float-csr.adoc @@ -5,13 +5,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 1, name: 'NX', attr: ['1'], type: 5}, - {bits: 1, name: 'UF', attr: ['1'], type: 5}, - {bits: 1, name: 'OF', attr: ['1'], type: 5}, - {bits: 1, name: 'DZ', attr: ['1'], type: 5}, - {bits: 1, name: 'NV', attr: ['1'], type: 5}, - {bits: 3, name: 'Rounding Mode', attr:['3'], type: 6}, - {bits: 24, name: 'Reserved', attr:['24'], type: 7}, + {bits: 1, name: 'NX', attr: ['1']}, + {bits: 1, name: 'UF', attr: ['1']}, + {bits: 1, name: 'OF', attr: ['1']}, + {bits: 1, name: 'DZ', attr: ['1']}, + {bits: 1, name: 'NV', attr: ['1']}, + {bits: 3, name: 'Rounding Mode', attr:['3']}, + {bits: 24, name: 'Reserved', attr:['24']}, ], config: {fontsize: 10}} .... diff --git a/src/images/wavedrom/flt-pt-to-int-move.adoc b/src/images/wavedrom/flt-pt-to-int-move.adoc index fc2a95a..861085e 100644 --- a/src/images/wavedrom/flt-pt-to-int-move.adoc +++ b/src/images/wavedrom/flt-pt-to-int-move.adoc @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','000','000'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H','H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FMV.X.H','FMV.H.X'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','000','000']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','0','0']}, + {bits: 2, name: 'fmt', attr: ['2','H','H']}, + {bits: 5, name: 'funct5', attr: ['5','FMV.X.H','FMV.H.X']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc index 43250a4..830cb2a 100644 --- a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc +++ b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3','J[N]/JX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'funct3', attr: ['3','J[N]/JX']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','H']}, + {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/fnmaddsub.adoc b/src/images/wavedrom/fnmaddsub.adoc index e8bda1b..ce63985 100644 --- a/src/images/wavedrom/fnmaddsub.adoc +++ b/src/images/wavedrom/fnmaddsub.adoc @@ -4,13 +4,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, - {bits: 5, name: 'rd', attr: 'dest', type: 2}, - {bits: 3, name: 'funct3', attr: 'RM', type: 8}, - {bits: 5, name: 'rs1', attr: 'src1', type: 4}, - {bits: 5, name: 'rs2', attr: 'src2', type: 4}, - {bits: 2, name: 'fmt', attr: 'S', type: 8}, - {bits: 5, name: 'rs3', attr: 'src3', type: 4}, + {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']}, + {bits: 5, name: 'rd', attr: 'dest'}, + {bits: 3, name: 'funct3', attr: 'RM'}, + {bits: 5, name: 'rs1', attr: 'src1'}, + {bits: 5, name: 'rs2', attr: 'src2'}, + {bits: 2, name: 'fmt', attr: 'S'}, + {bits: 5, name: 'rs3', attr: 'src3'}, ]} .... diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc b/src/images/wavedrom/fsjgnjnx-d.adoc index fff7808..6247a94 100644 --- a/src/images/wavedrom/fsjgnjnx-d.adoc +++ b/src/images/wavedrom/fsjgnjnx-d.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','J[N]/JX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','J[N]/JX']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','D']}, + {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, ]} .... diff --git a/src/images/wavedrom/half-ls.adoc b/src/images/wavedrom/half-ls.adoc index fb26d9b..1d74b69 100644 --- a/src/images/wavedrom/half-ls.adoc +++ b/src/images/wavedrom/half-ls.adoc @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: 'LOAD-FP', type: 8}, - {bits: 5, name: 'rd', attr: 'dest', type: 2}, - {bits: 3, name: 'width', attr: 'H', type: 8}, - {bits: 5, name: 'rs1', attr: 'base', type: 4}, - {bits: 12, name: 'imm[11:0]', attr: 'offset', type: 3}, + {bits: 7, name: 'opcode', attr: 'LOAD-FP'}, + {bits: 5, name: 'rd', attr: 'dest'}, + {bits: 3, name: 'width', attr: 'H'}, + {bits: 5, name: 'rs1', attr: 'base'}, + {bits: 12, name: 'imm[11:0]', attr: 'offset'}, ]} .... diff --git a/src/images/wavedrom/half-pr-flt-pt-class.adoc b/src/images/wavedrom/half-pr-flt-pt-class.adoc index 5490f5e..d2af321 100644 --- a/src/images/wavedrom/half-pr-flt-pt-class.adoc +++ b/src/images/wavedrom/half-pr-flt-pt-class.adoc @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','001'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','001']}, + {bits: 5, name: 'rs1', attr: ['5', 'src']}, + {bits: 5, name: 'rs2', attr: ['5','0']}, + {bits: 2, name: 'fmt', attr: ['2','H']}, + {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/half-pr-flt-pt-compare.adoc b/src/images/wavedrom/half-pr-flt-pt-compare.adoc index 78033c1..47e2e9f 100644 --- a/src/images/wavedrom/half-pr-flt-pt-compare.adoc +++ b/src/images/wavedrom/half-pr-flt-pt-compare.adoc @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','H']}, + {bits: 5, name: 'funct5', attr: ['5','FCMP']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/half-prec-conv-and-mv.adoc b/src/images/wavedrom/half-prec-conv-and-mv.adoc index 013f1b9..7f05de4 100644 --- a/src/images/wavedrom/half-prec-conv-and-mv.adoc +++ b/src/images/wavedrom/half-prec-conv-and-mv.adoc @@ -4,12 +4,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]'], type: 3}, - {bits: 2, name: 'fmt', attr: ['2','H', 'H'], type: 2}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.int.H','FCVT.H.int'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]']}, + {bits: 2, name: 'fmt', attr: ['2','H', 'H']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.int.H','FCVT.H.int']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc index c42038c..f95854d 100644 --- a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc +++ b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src','src','src','src','SRC'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','H','S','H','D','H','Q'], type: 3}, - {bits: 2, name: 'fmt', attr: ['2','S','H','D','H','Q','H'], type: 2}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.S.H','FCVT.H.S','FCVT.D.H','FCVT.H.D','FCVT.Q.H','FCVT.H.Q'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src','src','src','src','SRC']}, + {bits: 5, name: 'rs2', attr: ['5','H','S','H','D','H','Q']}, + {bits: 2, name: 'fmt', attr: ['2','S','H','D','H','Q','H']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.S.H','FCVT.H.S','FCVT.D.H','FCVT.H.D','FCVT.Q.H','FCVT.H.Q']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/half-store.adoc b/src/images/wavedrom/half-store.adoc index fb0d18c..bdb9058 100644 --- a/src/images/wavedrom/half-store.adoc +++ b/src/images/wavedrom/half-store.adoc @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: 'STORE-FP', type: 8}, - {bits: 5, name: 'imm[4:0]', attr: 'offset', type: 3}, - {bits: 3, name: 'width', attr: 'H', type: 8}, - {bits: 5, name: 'rs1', attr: 'base', type: 4}, - {bits: 5, name: 'rs2', attr: 'src', type: 4}, - {bits: 12, name: 'imm[11:5]', attr: 'offset', type: 3}, + {bits: 7, name: 'opcode', attr: 'STORE-FP'}, + {bits: 5, name: 'imm[4:0]', attr: 'offset'}, + {bits: 3, name: 'width', attr: 'H'}, + {bits: 5, name: 'rs1', attr: 'base'}, + {bits: 5, name: 'rs2', attr: 'src'}, + {bits: 12, name: 'imm[11:5]', attr: 'offset'}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/hinvalgvma.edn b/src/images/wavedrom/hinvalgvma.edn index ab1a0cd..d3f9dd9 100644 --- a/src/images/wavedrom/hinvalgvma.edn +++ b/src/images/wavedrom/hinvalgvma.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'gaddr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'vmid'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.GVMA'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', 'gaddr']}, + {bits: 5, name: 'rs2', attr: ['5', 'vmid']}, + {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.GVMA']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/hinvalvvma.edn b/src/images/wavedrom/hinvalvvma.edn index 0b93b9f..05f5d40 100644 --- a/src/images/wavedrom/hinvalvvma.edn +++ b/src/images/wavedrom/hinvalvvma.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'vaddr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'asid'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.VVMA'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, + {bits: 5, name: 'rs2', attr: ['5', 'asid']}, + {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.VVMA']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/hypv-mm-fence.edn b/src/images/wavedrom/hypv-mm-fence.edn index 2840b1a..a653d4e 100644 --- a/src/images/wavedrom/hypv-mm-fence.edn +++ b/src/images/wavedrom/hypv-mm-fence.edn @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 3, attr: ['7', 'SYSTEM', 'SYSTEM']}, - {bits: 5, name: 'rd', type: 5, attr: ['5','0', '0']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','PRIV', 'PRIV']}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','vaddr', 'gaddr']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','asid', 'vmid']}, - {bits: 7, name: 'funct7', type: 5, attr: ['7','HFENCE.VVMA', 'HFENCE.GVMA']}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5','0', '0']}, + {bits: 3, name: 'funct3', attr: ['3','PRIV', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5','vaddr', 'gaddr']}, + {bits: 5, name: 'rs2', attr: ['5','asid', 'vmid']}, + {bits: 7, name: 'funct7', attr: ['7','HFENCE.VVMA', 'HFENCE.GVMA']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/hypv-virt-load-and-store.edn b/src/images/wavedrom/hypv-virt-load-and-store.edn index d0e1d9e..2ee4486 100644 --- a/src/images/wavedrom/hypv-virt-load-and-store.edn +++ b/src/images/wavedrom/hypv-virt-load-and-store.edn @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 3, attr: ['7','SYSTEM', 'SYSTEM', 'SYSTEM']}, - {bits: 5, name: 'rd', type: 5, attr: ['5','dest', 'dest', '0']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','PRIVM', 'PRIVM', 'PRIVM']}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','addr', 'addr', 'addr']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','[U]', 'HLVX', 'src']}, - {bits: 7, name: 'funct7', type: 5, attr: ['7','HLV.width', 'HLVX.HU/WU', 'HSV.width']}, + {bits: 7, name: 'opcode', attr: ['7','SYSTEM', 'SYSTEM', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5','dest', 'dest', '0']}, + {bits: 3, name: 'funct3', attr: ['3','PRIVM', 'PRIVM', 'PRIVM']}, + {bits: 5, name: 'rs1', attr: ['5','addr', 'addr', 'addr']}, + {bits: 5, name: 'rs2', attr: ['5','[U]', 'HLVX', 'src']}, + {bits: 7, name: 'funct7', attr: ['7','HLV.width', 'HLVX.HU/WU', 'HSV.width']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/immediate.adoc b/src/images/wavedrom/immediate.adoc index c6fb00d..3dec16b 100644 --- a/src/images/wavedrom/immediate.adoc +++ b/src/images/wavedrom/immediate.adoc @@ -8,7 +8,7 @@ {bits: 1, name: '[20]'}, {bits: 4, name: 'inst[24:21]'}, {bits: 6, name: 'inst[30:25]'}, - {bits: 21, name: '— inst[31] —', type: 7}, + {bits: 21, name: '— inst[31] —'}, ], config:{fontsize: 12, label:{right: 'I-immediate'}}} .... //#### S-immediate @@ -19,7 +19,7 @@ {bits: 1, name: '[7]'}, {bits: 4, name: 'inst[11:8]'}, {bits: 6, name: 'inst[30:25]'}, - {bits: 21, name: '— inst[31] —', type: 7}, + {bits: 21, name: '— inst[31] —'}, ], config:{fontsize: 12, label:{right: 'S-immediate'}}} .... //#### B-immediate @@ -27,11 +27,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 1, name: '0', type: 5}, + {bits: 1, name: '0'}, {bits: 4, name: 'inst[11:8]'}, {bits: 6, name: 'inst[30:25]'}, {bits: 1, name: '[7]'}, - {bits: 20, name: '— inst[31] —', type: 7}, + {bits: 20, name: '— inst[31] —'}, ], config:{fontsize: 12, label:{right: 'B-immediate'}}} .... //#### U-immediate @@ -39,10 +39,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 12, name: '0', type: 5}, + {bits: 12, name: '0'}, {bits: 8, name: 'inst[19:12]'}, {bits: 11, name: 'inst[30:20]'}, - {bits: 1, name: '[31]', type: 7}, + {bits: 1, name: '[31]'}, ], config:{fontsize: 12, label:{right: 'U-immediate'}}} .... //#### J-immediate @@ -50,11 +50,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 1, name: '0', type: 5}, + {bits: 1, name: '0'}, {bits: 4, name: 'inst[24:21]'}, {bits: 6, name: 'inst[30:25]'}, {bits: 1, name: '[20]'}, {bits: 8, name: 'inst[19:12]'}, - {bits: 12, name: '— inst[31] —', type: 7}, + {bits: 12, name: '— inst[31] —'}, ], config:{fontsize: 12, label:{right: 'J-immediate'}}} .... diff --git a/src/images/wavedrom/immediate_variants.adoc b/src/images/wavedrom/immediate_variants.adoc index c1f8335..8f9be0c 100644 --- a/src/images/wavedrom/immediate_variants.adoc +++ b/src/images/wavedrom/immediate_variants.adoc @@ -21,7 +21,7 @@ {bits: 5, name: 'rd'}, {bits: 3, name: 'funct3'}, {bits: 5, name: 'rs1'}, - {bits: 12, name: 'imm[11:0]', type: 3}, + {bits: 12, name: 'imm[11:0]'}, ], config: {label: {right: 'I-Type'}}} .... @@ -29,11 +29,11 @@ .... {reg: [ {bits: 7, name: 'opcode'}, - {bits: 5, name: 'imm[4:0]', type: 3}, + {bits: 5, name: 'imm[4:0]'}, {bits: 3, name: 'funct3'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, - {bits: 7, name: 'imm[11:5]', type: 3} + {bits: 7, name: 'imm[11:5]'} ], config: {label: {right: 'S-Type'}}} .... @@ -41,13 +41,13 @@ .... {reg: [ {bits: 7, name: 'opcode'}, - {bits: 1, name: '[11]', type: 3}, - {bits: 4, name: 'imm[4:1]', type: 3}, + {bits: 1, name: '[11]'}, + {bits: 4, name: 'imm[4:1]'}, {bits: 3, name: 'funct3'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, - {bits: 6, name: 'imm[10:5]', type: 3}, - {bits: 1, name: '[12]', type: 3} + {bits: 6, name: 'imm[10:5]'}, + {bits: 1, name: '[12]'} ], config: {fontsize: 12, label: {right: 'B-Type'}}} .... @@ -56,7 +56,7 @@ {reg: [ {bits: 7, name: 'opcode'}, {bits: 5, name: 'rd'}, - {bits: 20, name: 'imm[31:12]', type: 3} + {bits: 20, name: 'imm[31:12]'} ], config: {label: {right: 'U-Type'}}} .... @@ -65,10 +65,10 @@ {reg: [ {bits: 7, name: 'opcode'}, {bits: 5, name: 'rd'}, - {bits: 8, name: 'imm[19:12]', type: 3}, - {bits: 1, name: '[11]', type: 3}, - {bits: 10, name: 'imm[10:1]', type: 3}, - {bits: 1, name: '[20]', type: 3} + {bits: 8, name: 'imm[19:12]'}, + {bits: 1, name: '[11]'}, + {bits: 10, name: 'imm[10:1]'}, + {bits: 1, name: '[20]'} ], config: {fontsize: 12, label: {right: 'J-Type'}}} .... diff --git a/src/images/wavedrom/immediate_variants2.adoc b/src/images/wavedrom/immediate_variants2.adoc index 498b282..05402be 100644 --- a/src/images/wavedrom/immediate_variants2.adoc +++ b/src/images/wavedrom/immediate_variants2.adoc @@ -17,40 +17,40 @@ ${wd({reg: [ {bits: 5, name: 'rd'}, {bits: 3, name: 'func3'}, {bits: 5, name: 'rs1'}, - {bits: 12, name: 'imm[11:0]', type: 3}, + {bits: 12, name: 'imm[11:0]'}, ], config: {label: {right: 'I-Type'}}})} ${wd({reg: [ {bits: 7, name: 'opcode'}, - {bits: 5, name: 'imm[4:0]', type: 3}, + {bits: 5, name: 'imm[4:0]'}, {bits: 3, name: 'func3'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, - {bits: 7, name: 'imm[11:5]', type: 3} + {bits: 7, name: 'imm[11:5]'} ], config: {label: {right: 'S-Type'}}})} ${wd({reg: [ {bits: 7, name: 'opcode'}, - {bits: 1, name: '[11]', type: 3}, - {bits: 4, name: 'imm[4:1]', type: 3}, + {bits: 1, name: '[11]'}, + {bits: 4, name: 'imm[4:1]'}, {bits: 3, name: 'func3'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, - {bits: 6, name: 'imm[10:5]', type: 3}, - {bits: 1, name: '[12]', type: 3} + {bits: 6, name: 'imm[10:5]'}, + {bits: 1, name: '[12]'} ], config: {label: {right: 'B-Type'}}})} ${wd({reg: [ {bits: 7, name: 'opcode'}, {bits: 5, name: 'rd'}, - {bits: 20, name: 'imm[31:12]', type: 3} + {bits: 20, name: 'imm[31:12]'} ], config: {label: {right: 'U-Type'}}})} ${wd({reg: [ {bits: 7, name: 'opcode'}, {bits: 5, name: 'rd'}, - {bits: 8, name: 'imm[19:12]', type: 3}, - {bits: 1, name: '[11]', type: 3}, - {bits: 10, name: 'imm[10:1]', type: 3}, - {bits: 1, name: '[20]', type: 3} + {bits: 8, name: 'imm[19:12]'}, + {bits: 1, name: '[11]'}, + {bits: 10, name: 'imm[10:1]'}, + {bits: 1, name: '[20]'} ], config: {label: {right: 'J-Type'}}})}
\ No newline at end of file diff --git a/src/images/wavedrom/instruction_formats.adoc b/src/images/wavedrom/instruction_formats.adoc index 442e27d..0741210 100644 --- a/src/images/wavedrom/instruction_formats.adoc +++ b/src/images/wavedrom/instruction_formats.adoc @@ -5,44 +5,44 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'rd', type: 2}, - {bits: 3, name: 'funct3', type: 8}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 7, name: 'funct7', type: 8} + {bits: 7, name: 'opcode'}, + {bits: 5, name: 'rd'}, + {bits: 3, name: 'funct3'}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, + {bits: 7, name: 'funct7'} ], config: {label: {right: 'R-Type'}}} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'rd', type: 2}, - {bits: 3, name: 'funct3', type: 8}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 12, name: 'imm[11:0]', type: 3}, + {bits: 7, name: 'opcode'}, + {bits: 5, name: 'rd'}, + {bits: 3, name: 'funct3'}, + {bits: 5, name: 'rs1'}, + {bits: 12, name: 'imm[11:0]'}, ], config: {label: {right: 'I-Type'}}} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'imm[4:0]', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 7, name: 'imm[11:5]', type: 3} + {bits: 7, name: 'opcode'}, + {bits: 5, name: 'imm[4:0]'}, + {bits: 3, name: 'funct3'}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, + {bits: 7, name: 'imm[11:5]'} ], config: {label: {right: 'S-Type'}}} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'rd', type: 2}, - {bits: 20, name: 'imm[31:12]', type: 3} + {bits: 7, name: 'opcode'}, + {bits: 5, name: 'rd'}, + {bits: 20, name: 'imm[31:12]'} ], config: {label: {right: 'U-Type'}}} .... diff --git a/src/images/wavedrom/int-comp-lui-aiupc.adoc b/src/images/wavedrom/int-comp-lui-aiupc.adoc index c3dbf95..dfb77d1 100644 --- a/src/images/wavedrom/int-comp-lui-aiupc.adoc +++ b/src/images/wavedrom/int-comp-lui-aiupc.adoc @@ -5,8 +5,8 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]'], type: 3} + {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]']} ]} .... diff --git a/src/images/wavedrom/int-comp-slli-srli-srai.adoc b/src/images/wavedrom/int-comp-slli-srli-srai.adoc index 3fa49a4..3e86d08 100644 --- a/src/images/wavedrom/int-comp-slli-srli-srai.adoc +++ b/src/images/wavedrom/int-comp-slli-srli-srai.adoc @@ -5,12 +5,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src'], type: 4}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]'], type: 3}, - {bits: 7, name: 'imm[11:5]', attr: ['7', 0, 0, 32], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI']}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]']}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 0, 0, 32]} ]} .... diff --git a/src/images/wavedrom/int_reg-reg.adoc b/src/images/wavedrom/int_reg-reg.adoc index 1ec0c17..3fd19f7 100644 --- a/src/images/wavedrom/int_reg-reg.adoc +++ b/src/images/wavedrom/int_reg-reg.adoc @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP', 'OP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest','dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 0, 0, 0, 32], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP', 'OP']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest','dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA']}, + {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1']}, + {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2']}, + {bits: 7, name: 'funct7', attr: ['7', 0, 0, 0, 32]} ]} .... diff --git a/src/images/wavedrom/integer_computational.adoc b/src/images/wavedrom/integer_computational.adoc index 5172d4e..707f06f 100644 --- a/src/images/wavedrom/integer_computational.adoc +++ b/src/images/wavedrom/integer_computational.adoc @@ -4,11 +4,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'ADDI/SLTI[U]', 'ANDI/ORI/XORI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]', 'I-immediate[11:0]'], type: 3} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'ADDI/SLTI[U]', 'ANDI/ORI/XORI']}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]', 'I-immediate[11:0]']} ]} .... diff --git a/src/images/wavedrom/load-reserve-st-conditional.adoc b/src/images/wavedrom/load-reserve-st-conditional.adoc index 355342c..c1addd3 100644 --- a/src/images/wavedrom/load-reserve-st-conditional.adoc +++ b/src/images/wavedrom/load-reserve-st-conditional.adoc @@ -5,14 +5,14 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'AMO', 'AMO'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'width', 'width'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'addr', 'addr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', '0', 'src'], type: 4}, - {bits: 1, name: 'rl', attr: ['1', 'ring', 'ring'], type: 8}, - {bits: 1, name: 'aq', attr: ['1', 'orde', 'orde'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5', 'LR.W/D', 'SC.W/D'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'AMO', 'AMO']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'width', 'width']}, + {bits: 5, name: 'rs1', attr: ['5', 'addr', 'addr']}, + {bits: 5, name: 'rs2', attr: ['5', '0', 'src']}, + {bits: 1, name: 'rl', attr: ['1', 'ring', 'ring']}, + {bits: 1, name: 'aq', attr: ['1', 'orde', 'orde']}, + {bits: 5, name: 'funct5', attr: ['5', 'LR.W/D', 'SC.W/D']}, ]} .... diff --git a/src/images/wavedrom/load_store.adoc b/src/images/wavedrom/load_store.adoc index f9de4d1..ac23d35 100644 --- a/src/images/wavedrom/load_store.adoc +++ b/src/images/wavedrom/load_store.adoc @@ -3,22 +3,22 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LOAD'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'width'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'LOAD']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'width']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'STORE'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, - {bits: 3, name: 'funct3', attr: ['3', 'width'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'STORE']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, + {bits: 3, name: 'funct3', attr: ['3', 'width']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 5, name: 'rs2', attr: ['5', 'src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, ]} .... diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.adoc b/src/images/wavedrom/m-st-ext-for-int-mult.adoc index 520951c..77a3507 100644 --- a/src/images/wavedrom/m-st-ext-for-int-mult.adoc +++ b/src/images/wavedrom/m-st-ext-for-int-mult.adoc @@ -4,24 +4,24 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'MUL/MULH[[S]U]', 'MULW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'multiplicand', 'multiplicand'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'multiplier', 'multiplier'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'MUL/MULH[[S]U]', 'MULW']}, + {bits: 5, name: 'rs1', attr: ['5', 'multiplicand', 'multiplicand']}, + {bits: 5, name: 'rs2', attr: ['5', 'multiplier', 'multiplier']}, + {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']}, ]} .... //[wavedrom, ,] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-32', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: 'MULW', type: 8}, -// {bits: 5, name: 'rs1', attr: 'multiplicand', type: 4}, -// {bits: 5, name: 'rs2', attr: 'multiplier', type: 4}, -// {bits: 7, name: 'funct7', attr: 'MULDIV', type: 8}, +// {bits: 7, name: 'opcode', attr: 'OP-32'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: 'MULW'}, +// {bits: 5, name: 'rs1', attr: 'multiplicand'}, +// {bits: 5, name: 'rs2', attr: 'multiplier'}, +// {bits: 7, name: 'funct7', attr: 'MULDIV'}, //]} //.... diff --git a/src/images/wavedrom/mem_order.adoc b/src/images/wavedrom/mem_order.adoc index 75b5ab0..c7e0ba4 100644 --- a/src/images/wavedrom/mem_order.adoc +++ b/src/images/wavedrom/mem_order.adoc @@ -3,10 +3,10 @@ [wavedrom,mem-order ,] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'FENCE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, + {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'FENCE']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, {bits: 1, name: 'SW', attr: 1}, {bits: 1, name: 'SR', attr: 1}, {bits: 1, name: 'SO', attr: 1}, @@ -15,6 +15,6 @@ {bits: 1, name: 'PR', attr: 1}, {bits: 1, name: 'PO', attr: 1}, {bits: 1, name: 'PI', attr: 1}, - {bits: 4, name: 'fm', attr: ['4', 'FM'], type: 8}, + {bits: 4, name: 'fm', attr: ['4', 'FM']}, ]} .... diff --git a/src/images/wavedrom/menvcfgreg.adoc b/src/images/wavedrom/menvcfgreg.adoc new file mode 100644 index 0000000..5ed6fb6 --- /dev/null +++ b/src/images/wavedrom/menvcfgreg.adoc @@ -0,0 +1,21 @@ +//.Machine environment configuration (`menvcfg`) register. +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'FIOM'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'LPE'}, + {bits: 1, name: 'SSE'}, + {bits: 2, name: 'CBIE'}, + {bits: 1, name: 'CBCFE'}, + {bits: 1, name: 'CBZE'}, + {bits: 24, name: 'WPRI'}, + {bits: 2, name: 'PMM'}, + {bits: 25, name: 'WPRI'}, + {bits: 1, name: 'DTE'}, + {bits: 1, name: 'CDE'}, + {bits: 1, name: 'ADUE'}, + {bits: 1, name: 'PBMTE'}, + {bits: 1, name: 'STCE'}, +], config:{lanes: 4, hspace:1024}} +.... diff --git a/src/images/wavedrom/mm-env-call.adoc b/src/images/wavedrom/mm-env-call.adoc index 9838230..703c0be 100644 --- a/src/images/wavedrom/mm-env-call.adoc +++ b/src/images/wavedrom/mm-env-call.adoc @@ -4,10 +4,10 @@ .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM','SYSTEM'],}, - {bits: 5, name: 'rd', type: 2, attr: ['5','0','0'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV','PRIV'],}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','0','0'],}, - {bits: 12, name: 'funct12', type: 8, attr: ['12','ECALL','EBREAK',]}, + {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM'],}, + {bits: 5, name: 'rd', attr: ['5','0','0'],}, + {bits: 3, name: 'funct3', attr: ['3','PRIV','PRIV'],}, + {bits: 5, name: 'rs1', attr: ['5','0','0'],}, + {bits: 12, name: 'funct12', attr: ['12','ECALL','EBREAK',]}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/mop-r.adoc b/src/images/wavedrom/mop-r.adoc index 713b37c..55347e0 100644 --- a/src/images/wavedrom/mop-r.adoc +++ b/src/images/wavedrom/mop-r.adoc @@ -1,10 +1,10 @@ [wavedrom, ,svg] .... {reg:[ - { bits: 7, name: 0x73, attr: ['SYSTEM'], type: 8 }, - { bits: 5, name: 'rd', type: 2 }, + { bits: 7, name: 0x73, attr: ['SYSTEM']}, + { bits: 5, name: 'rd'}, { bits: 3, name: 0x4 }, - { bits: 5, name: 'rs1', type: 4 }, + { bits: 5, name: 'rs1'}, { bits: 2, name: 'n[1:0]' }, { bits: 4, name: 0x7 }, { bits: 2, name: 'n[3:2]' }, diff --git a/src/images/wavedrom/mop-rr.adoc b/src/images/wavedrom/mop-rr.adoc index b70f854..879e372 100644 --- a/src/images/wavedrom/mop-rr.adoc +++ b/src/images/wavedrom/mop-rr.adoc @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg:[ - { bits: 7, name: 0x73, attr: ['SYSTEM'], type: 8 }, - { bits: 5, name: 'rd', type: 2 }, + { bits: 7, name: 0x73, attr: ['SYSTEM']}, + { bits: 5, name: 'rd'}, { bits: 3, name: 0x4 }, - { bits: 5, name: 'rs1', type: 4 }, - { bits: 5, name: 'rs2', type: 4 }, + { bits: 5, name: 'rs1'}, + { bits: 5, name: 'rs2'}, { bits: 1, name: 0x1 }, { bits: 2, name: 'n[1:0]' }, { bits: 2, name: 0x0 }, diff --git a/src/images/wavedrom/mseccfg.adoc b/src/images/wavedrom/mseccfg.adoc new file mode 100644 index 0000000..82242ca --- /dev/null +++ b/src/images/wavedrom/mseccfg.adoc @@ -0,0 +1,14 @@ +//.Machine security configuration (`mseccfg`) register. +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'MML'}, + {bits: 1, name: 'MMWP'}, + {bits: 1, name: 'RLB'}, + {bits: 5, name: 'WPRI'}, + {bits: 1, name: 'USEED'}, + {bits: 1, name: 'SSEED'}, + {bits: 1, name: 'MLPE'}, + {bits: 53, name: 'WPRI'}, +], config:{lanes: 4, hspace:1024}} +.... diff --git a/src/images/wavedrom/mstatushreg.adoc b/src/images/wavedrom/mstatushreg.adoc new file mode 100644 index 0000000..702ea11 --- /dev/null +++ b/src/images/wavedrom/mstatushreg.adoc @@ -0,0 +1,15 @@ +//.Additional machine-mode status (`mstatush`) register for RV32. +[wavedrom, ,svg] +.... +{reg: [ + {bits: 4, name: 'WPRI'}, + {bits: 1, name: 'SBE'}, + {bits: 1, name: 'MBE'}, + {bits: 1, name: 'GVA'}, + {bits: 1, name: 'MPV'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MPELP'}, + {bits: 1, name: 'MDT'}, + {bits: 21, name: 'WPRI'}, +], config:{lanes: 2, hspace:1024}} +.... diff --git a/src/images/wavedrom/mstatusreg-rv321.adoc b/src/images/wavedrom/mstatusreg-rv321.adoc new file mode 100644 index 0000000..cc77fc2 --- /dev/null +++ b/src/images/wavedrom/mstatusreg-rv321.adoc @@ -0,0 +1,29 @@ +//.Machine-mode status (`mstatus`) register for RV32 +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SPIE'}, + {bits: 1, name: 'UBE'}, + {bits: 1, name: 'MPIE'}, + {bits: 1, name: 'SPP'}, + {bits: 2, name: 'VS[1:0]'}, + {bits: 2, name: 'MPP[1:0]'}, + {bits: 2, name: 'FS[1:0]'}, + {bits: 2, name: 'XS[1:0]'}, + {bits: 1, name: 'MPRV'}, + {bits: 1, name: 'SUM'}, + {bits: 1, name: 'MXR'}, + {bits: 1, name: 'TVM'}, + {bits: 1, name: 'TW'}, + {bits: 1, name: 'TSR'}, + {bits: 1, name: 'SPELP'}, + {bits: 1, name: 'SDT'}, + {bits: 6, name: 'WPRI'}, + {bits: 1, name: 'SD'}, +], config:{lanes: 2, hspace:1024}} +.... diff --git a/src/images/wavedrom/mstatusreg.adoc b/src/images/wavedrom/mstatusreg.adoc new file mode 100644 index 0000000..db24626 --- /dev/null +++ b/src/images/wavedrom/mstatusreg.adoc @@ -0,0 +1,39 @@ +//.Machine-mode status (`mstatus`) register for RV64 +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SPIE'}, + {bits: 1, name: 'UBE'}, + {bits: 1, name: 'MPIE'}, + {bits: 1, name: 'SPP'}, + {bits: 2, name: 'VS[1:0]'}, + {bits: 2, name: 'MPP[1:0]'}, + {bits: 2, name: 'FS[1:0]'}, + {bits: 2, name: 'XS[1:0]'}, + {bits: 1, name: 'MPRV'}, + {bits: 1, name: 'SUM'}, + {bits: 1, name: 'MXR'}, + {bits: 1, name: 'TVM'}, + {bits: 1, name: 'TW'}, + {bits: 1, name: 'TSR'}, + {bits: 1, name: 'SPELP'}, + {bits: 1, name: 'SDT'}, + {bits: 7, name: 'WPRI'}, + {bits: 2, name: 'UXL[1:0]'}, + {bits: 2, name: 'SXL[1:0]'}, + {bits: 1, name: 'SBE'}, + {bits: 1, name: 'MBE'}, + {bits: 1, name: 'GVA'}, + {bits: 1, name: 'MPV'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MPELP'}, + {bits: 1, name: 'MDT'}, + {bits: 20, name: 'WPRI'}, + {bits: 1, name: 'SD'}, +], config:{lanes: 4, hspace:1024}} +.... diff --git a/src/images/wavedrom/nop.adoc b/src/images/wavedrom/nop.adoc index 34ad70e..b566909 100644 --- a/src/images/wavedrom/nop.adoc +++ b/src/images/wavedrom/nop.adoc @@ -2,10 +2,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'ADDI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', '0'], type: 3} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'ADDI']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', '0']} ]} .... diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc index ba4e224..a388033 100644 --- a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc +++ b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3', 'J[N]/JX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3', 'J[N]/JX']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, ]} .... diff --git a/src/images/wavedrom/quad-cnvrt-mv.adoc b/src/images/wavedrom/quad-cnvrt-mv.adoc index 3fc9f86..840118d 100644 --- a/src/images/wavedrom/quad-cnvrt-mv.adoc +++ b/src/images/wavedrom/quad-cnvrt-mv.adoc @@ -3,26 +3,26 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]', 'W[U]/L[U]'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','Q','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.int.Q','FCVT.Q.int'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]', 'W[U]/L[U]']}, + {bits: 2, name: 'fmt', attr: ['2','Q','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.int.Q','FCVT.Q.int']}, ]} .... //[wavedrom, ,] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'rm', attr: 'RM', type: 8}, -// {bits: 5, name: 'rs1', attr: 'src', type: 4}, -// {bits: 5, name: 'rs2', attr: ['W', 'WU', 'L', 'LU'], type: 4}, -// {bits: 2, name: 'fmt', attr: 'Q', type: 8}, -// {bits: 5, name: 'funct5', attr: 'FCVT.Q.int', type: 8}, +// {bits: 7, name: 'opcode', attr: 'OP-FP'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'rm', attr: 'RM'}, +// {bits: 5, name: 'rs1', attr: 'src'}, +// {bits: 5, name: 'rs2', attr: ['W', 'WU', 'L', 'LU']}, +// {bits: 2, name: 'fmt', attr: 'Q'}, +// {bits: 5, name: 'funct5', attr: 'FCVT.Q.int'}, //]} //.... diff --git a/src/images/wavedrom/quad-cnvt-interchange.adoc b/src/images/wavedrom/quad-cnvt-interchange.adoc index 1178397..54adc1f 100644 --- a/src/images/wavedrom/quad-cnvt-interchange.adoc +++ b/src/images/wavedrom/quad-cnvt-interchange.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-FP', 'OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','Q', 'S', 'Q', 'D'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S','Q', 'D', 'Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.S.Q', 'FCVT.Q.S', 'FCVT.D.Q', 'FCVT.Q.D'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'OP-FP', 'OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','Q', 'S', 'Q', 'D']}, + {bits: 2, name: 'fmt', attr: ['2','S','Q', 'D', 'Q']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.S.Q', 'FCVT.Q.S', 'FCVT.D.Q', 'FCVT.Q.D']}, ]} .... diff --git a/src/images/wavedrom/quad-compute.adoc b/src/images/wavedrom/quad-compute.adoc index 6aa3953..2451ac9 100644 --- a/src/images/wavedrom/quad-compute.adoc +++ b/src/images/wavedrom/quad-compute.adoc @@ -3,39 +3,39 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','Q','Q','Q','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src']}, + {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0']}, + {bits: 2, name: 'fmt', attr: ['2','Q','Q','Q','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','Q'], type: 8}, - {bits: 5, name: 'rs3', attr: ['5','src3'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','Q']}, + {bits: 5, name: 'rs3', attr: ['5','src3']}, ]} .... //[wavedrom, ,] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['MIN', 'MAX'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 2, name: 'fmt', attr: 'Q', type: 8}, -// {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8}, +// {bits: 7, name: 'opcode', attr: 'OP-FP'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: ['MIN', 'MAX']}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 2, name: 'fmt', attr: 'Q'}, +// {bits: 5, name: 'funct5', attr: 'FMIN-MAX'}, //]} //.... @@ -43,12 +43,12 @@ //[wavedrom, ,] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: 'RM', type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 2, name: 'fmt', attr: 'Q', type: 8}, -// {bits: 5, name: 'rs3', attr: 'src3', type: 4}, +// {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']}, +// {bits: 5, name: 'rd', attr: 'dest'} +// {bits: 3, name: 'funct3', attr: 'RM'}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 2, name: 'fmt', attr: 'Q'}, +// {bits: 5, name: 'rs3', attr: 'src3'}, //]} //....
\ No newline at end of file diff --git a/src/images/wavedrom/quad-float-clssfy.adoc b/src/images/wavedrom/quad-float-clssfy.adoc index 0023c7d..325239e 100644 --- a/src/images/wavedrom/quad-float-clssfy.adoc +++ b/src/images/wavedrom/quad-float-clssfy.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','001'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','001']}, + {bits: 5, name: 'rs1', attr: ['5','src']}, + {bits: 5, name: 'rs2', attr: ['5','0']}, + {bits: 2, name: 'fmt', attr: ['2','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, ]} .... diff --git a/src/images/wavedrom/quad-float-compare.adoc b/src/images/wavedrom/quad-float-compare.adoc index 2269bc9..86e8f83 100644 --- a/src/images/wavedrom/quad-float-compare.adoc +++ b/src/images/wavedrom/quad-float-compare.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FCMP']}, ]} .... diff --git a/src/images/wavedrom/quad-ls.adoc b/src/images/wavedrom/quad-ls.adoc index 3ba4099..d855534 100644 --- a/src/images/wavedrom/quad-ls.adoc +++ b/src/images/wavedrom/quad-ls.adoc @@ -3,23 +3,23 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','LOAD-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'width', attr: ['3','Q'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7','LOAD-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'width', attr: ['3','Q']}, + {bits: 5, name: 'rs1', attr: ['5','base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]']}, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','STORE-FP'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]'], type: 3}, - {bits: 3, name: 'width', attr: ['3','Q'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7','STORE-FP']}, + {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]']}, + {bits: 3, name: 'width', attr: ['3','Q']}, + {bits: 5, name: 'rs1', attr: ['5','base']}, + {bits: 5, name: 'rs2', attr: ['5','src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]']}, ]} .... diff --git a/src/images/wavedrom/reg-based-ldnstr.adoc b/src/images/wavedrom/reg-based-ldnstr.adoc index ea9e245..031ea1a 100644 --- a/src/images/wavedrom/reg-based-ldnstr.adoc +++ b/src/images/wavedrom/reg-based-ldnstr.adoc @@ -4,12 +4,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', attr: ['2', 'C0', 'C0', 'C0', 'C0', 'C0'], type: 8}, - {bits: 3, name: 'rdʹ', attr: ['3', 'dest', 'dest','dest','dest','dest'], type: 3}, - {bits: 2, name: 'imm', attr:['2', 'offset[2|6]', 'offset[7:6]', 'offset[7:6]', 'offset[2|6]', 'offset[7:6]'], type: 2}, - {bits: 3, name: 'rs1ʹ', attr: ['3', 'base', 'base', 'base', 'base', 'base'], type: 2}, - {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]'], type: 3}, - {bits: 3, name: 'funct3', attr: ['3', 'C.LW', 'C.LD', 'C.LQ', 'C.FLW', 'C.FLD'], type: 8}, + {bits: 2, name: 'op', attr: ['2', 'C0', 'C0', 'C0', 'C0', 'C0']}, + {bits: 3, name: 'rdʹ', attr: ['3', 'dest', 'dest','dest','dest','dest']}, + {bits: 2, name: 'imm', attr:['2', 'offset[2|6]', 'offset[7:6]', 'offset[7:6]', 'offset[2|6]', 'offset[7:6]']}, + {bits: 3, name: 'rs1ʹ', attr: ['3', 'base', 'base', 'base', 'base', 'base']}, + {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]']}, + {bits: 3, name: 'funct3', attr: ['3', 'C.LW', 'C.LD', 'C.LQ', 'C.FLW', 'C.FLD']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/rv64_lui-auipc.adoc b/src/images/wavedrom/rv64_lui-auipc.adoc index 132c770..5850133 100644 --- a/src/images/wavedrom/rv64_lui-auipc.adoc +++ b/src/images/wavedrom/rv64_lui-auipc.adoc @@ -3,8 +3,8 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]'], type: 3} + {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]']} ]} .... diff --git a/src/images/wavedrom/rv64i-base-int.adoc b/src/images/wavedrom/rv64i-base-int.adoc index e4edaf3..4ff3b83 100644 --- a/src/images/wavedrom/rv64i-base-int.adoc +++ b/src/images/wavedrom/rv64i-base-int.adoc @@ -5,11 +5,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'ADDIW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]'], type: 3} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'ADDIW']}, + {bits: 5, name: 'rs1', attr: ['5', 'src']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]']} ]} .... diff --git a/src/images/wavedrom/rv64i-slli.adoc b/src/images/wavedrom/rv64i-slli.adoc index 038a052..b261564 100644 --- a/src/images/wavedrom/rv64i-slli.adoc +++ b/src/images/wavedrom/rv64i-slli.adoc @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src'], type: 4}, - {bits: 6, name: 'imm[5:0]', attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]'], type: 3}, - {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000'], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI']}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, + {bits: 6, name: 'imm[5:0]', attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]']}, + {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']} ]} .... diff --git a/src/images/wavedrom/rv64i-slliw.adoc b/src/images/wavedrom/rv64i-slliw.adoc index bd51e9b..0ca01ba 100644 --- a/src/images/wavedrom/rv64i-slliw.adoc +++ b/src/images/wavedrom/rv64i-slliw.adoc @@ -1,12 +1,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLLIW', 'SRLIW', 'SRAIW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src'], type: 4}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]'], type: 3}, - {bits: 1, name: '[5]', attr: ['1', '0', '0', '0'], type: 3}, - {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000'], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'SLLIW', 'SRLIW', 'SRAIW']}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]']}, + {bits: 1, name: '[5]', attr: ['1', '0', '0', '0']}, + {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']} ]} .... diff --git a/src/images/wavedrom/rv64i_int-reg-reg.adoc b/src/images/wavedrom/rv64i_int-reg-reg.adoc index a69e718..6d29ec7 100644 --- a/src/images/wavedrom/rv64i_int-reg-reg.adoc +++ b/src/images/wavedrom/rv64i_int-reg-reg.adoc @@ -5,23 +5,23 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP-32', 'OP-32', 'OP-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLL/SRL', 'SRA', 'ADDW', 'SLLW/SRLW', 'SUBW/SRAW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1', 'src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2', 'src2'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', '000000', '010000', '000000', '000000', '010000'], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP-32', 'OP-32', 'OP-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'SLL/SRL', 'SRA', 'ADDW', 'SLLW/SRLW', 'SUBW/SRAW']}, + {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1', 'src1']}, + {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2', 'src2']}, + {bits: 7, name: 'funct7', attr: ['7', '0000000', '0100000', '0000000', '0000000', '0100000']} ]} .... //[wavedrom, ,svg] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-32', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 7, name: 'funct7', attr: [0, 0, 0, 32, 32], type: 8} +// {bits: 7, name: 'opcode', attr: 'OP-32'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 7, name: 'funct7', attr: [0, 0, 0, 32, 32]} //]} //.... diff --git a/src/images/wavedrom/sfenceinvalir.edn b/src/images/wavedrom/sfenceinvalir.edn index 639be34..747df40 100644 --- a/src/images/wavedrom/sfenceinvalir.edn +++ b/src/images/wavedrom/sfenceinvalir.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', '1'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.INVAL.IR'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, + {bits: 5, name: 'rs2', attr: ['5', '1']}, + {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.INVAL.IR']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sfencevma.edn b/src/images/wavedrom/sfencevma.edn index a7a7663..e06d949 100644 --- a/src/images/wavedrom/sfencevma.edn +++ b/src/images/wavedrom/sfencevma.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'vaddr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'asid'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.VMA'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, + {bits: 5, name: 'rs2', attr: ['5', 'asid']}, + {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.VMA']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sfencewinval.edn b/src/images/wavedrom/sfencewinval.edn index 2973af8..712f1c1 100644 --- a/src/images/wavedrom/sfencewinval.edn +++ b/src/images/wavedrom/sfencewinval.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', '0'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.W.INVAL'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, + {bits: 5, name: 'rs2', attr: ['5', '0']}, + {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.W.INVAL']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sinvalvma.edn b/src/images/wavedrom/sinvalvma.edn index 89d0d40..1752a52 100644 --- a/src/images/wavedrom/sinvalvma.edn +++ b/src/images/wavedrom/sinvalvma.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'vaddr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'asid'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'SINVAL.VMA'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, + {bits: 5, name: 'rs2', attr: ['5', 'asid']}, + {bits: 7, name: 'funct7', attr: ['7', 'SINVAL.VMA']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sp-load-store-2.adoc b/src/images/wavedrom/sp-load-store-2.adoc index f1025e9..a95b861 100644 --- a/src/images/wavedrom/sp-load-store-2.adoc +++ b/src/images/wavedrom/sp-load-store-2.adoc @@ -3,22 +3,22 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'width', attr: ['3', 'W'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'width', attr: ['3', 'W']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, - {bits: 3, name: 'width', attr: ['3', 'W'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, + {bits: 3, name: 'width', attr: ['3', 'W']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 5, name: 'rs2', attr: ['5', 'src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sp-load-store.adoc b/src/images/wavedrom/sp-load-store.adoc index 192626b..6b1fe49 100644 --- a/src/images/wavedrom/sp-load-store.adoc +++ b/src/images/wavedrom/sp-load-store.adoc @@ -3,23 +3,23 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'width', attr: ['3', 'H'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'width', attr: ['3', 'H']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, ]} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, - {bits: 3, name: 'width', attr: ['3', 'H'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, + {bits: 3, name: 'width', attr: ['3', 'H']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 5, name: 'rs2', attr: ['5', 'src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, ]} .... diff --git a/src/images/wavedrom/spfloat-classify.adoc b/src/images/wavedrom/spfloat-classify.adoc index 236880d..52ec8bc 100644 --- a/src/images/wavedrom/spfloat-classify.adoc +++ b/src/images/wavedrom/spfloat-classify.adoc @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','001'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','001']}, + {bits: 5, name: 'rs1', attr: ['5','src']}, + {bits: 5, name: 'rs2', attr: ['5','0']}, + {bits: 2, name: 'fmt', attr: ['2','S']}, + {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, ]} .... diff --git a/src/images/wavedrom/spfloat-cn-cmp.adoc b/src/images/wavedrom/spfloat-cn-cmp.adoc index e46a099..0e5db87 100644 --- a/src/images/wavedrom/spfloat-cn-cmp.adoc +++ b/src/images/wavedrom/spfloat-cn-cmp.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP', 'OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest', 'dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src', 'src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]D', 'W[U]/L[U]'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.int.fmt', 'FCVT.fmt.int'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP', 'OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest', 'dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src', 'src']}, + {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]D', 'W[U]/L[U]']}, + {bits: 2, name: 'fmt', attr: ['2','S','S']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.int.fmt', 'FCVT.fmt.int']}, ]} .... diff --git a/src/images/wavedrom/spfloat-comp.adoc b/src/images/wavedrom/spfloat-comp.adoc index 7059e8e..05012a7 100644 --- a/src/images/wavedrom/spfloat-comp.adoc +++ b/src/images/wavedrom/spfloat-comp.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','EQ', 'LT', 'LE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','EQ', 'LT', 'LE']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','S']}, + {bits: 5, name: 'funct5', attr: ['5','FCMP']}, ]} .... diff --git a/src/images/wavedrom/spfloat-mv.adoc b/src/images/wavedrom/spfloat-mv.adoc index d5df81d..47a63ee 100644 --- a/src/images/wavedrom/spfloat-mv.adoc +++ b/src/images/wavedrom/spfloat-mv.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','000', '000'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FMV.X.W','FMV.W.X'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','000', '000']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','0','0']}, + {bits: 2, name: 'fmt', attr: ['2','S','S']}, + {bits: 5, name: 'funct5', attr: ['5','FMV.X.W','FMV.W.X']}, ]} .... diff --git a/src/images/wavedrom/spfloat-sign-inj.adoc b/src/images/wavedrom/spfloat-sign-inj.adoc index 74040b7..8c81976 100644 --- a/src/images/wavedrom/spfloat-sign-inj.adoc +++ b/src/images/wavedrom/spfloat-sign-inj.adoc @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','J[N]/JX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'rm', attr: ['3','J[N]/JX']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','S']}, + {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat-zfh.adoc b/src/images/wavedrom/spfloat-zfh.adoc index d53e6bd..4221c2d 100644 --- a/src/images/wavedrom/spfloat-zfh.adoc +++ b/src/images/wavedrom/spfloat-zfh.adoc @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'MIN/MAX', 'RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src1', 'src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', 'src2', '0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H', 'H', 'H', 'H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'MIN/MAX', 'RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src1', 'src']}, + {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', 'src2', '0']}, + {bits: 2, name: 'fmt', attr: ['2','H', 'H', 'H', 'H']}, + {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat.adoc b/src/images/wavedrom/spfloat.adoc index 9384544..97679bd 100644 --- a/src/images/wavedrom/spfloat.adoc +++ b/src/images/wavedrom/spfloat.adoc @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'RM','MIN/MAX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src', 'src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', '0', 'src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S', 'S', 'S', 'S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FSQRT','FMIN-MAX'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'RM','MIN/MAX']}, + {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src', 'src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', '0', 'src2']}, + {bits: 2, name: 'fmt', attr: ['2','S', 'S', 'S', 'S']}, + {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FSQRT','FMIN-MAX']}, ]} .... diff --git a/src/images/wavedrom/spfloat2-zfh.adoc b/src/images/wavedrom/spfloat2-zfh.adoc index 44789da..64d3fa7 100644 --- a/src/images/wavedrom/spfloat2-zfh.adoc +++ b/src/images/wavedrom/spfloat2-zfh.adoc @@ -1,12 +1,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H'], type: 8}, - {bits: 5, name: 'rs3', attr: ['5','src3'], type: 4}, + {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','H']}, + {bits: 5, name: 'rs3', attr: ['5','src3']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat2.adoc b/src/images/wavedrom/spfloat2.adoc index 8c2b976..cee5bdc 100644 --- a/src/images/wavedrom/spfloat2.adoc +++ b/src/images/wavedrom/spfloat2.adoc @@ -1,12 +1,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S'], type: 8}, - {bits: 5, name: 'rs3', attr: ['5','src3'], type: 4}, + {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','S']}, + {bits: 5, name: 'rs3', attr: ['5','src3']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/transformedatomicinst.edn b/src/images/wavedrom/transformedatomicinst.edn index d598bc3..ab4f989 100644 --- a/src/images/wavedrom/transformedatomicinst.edn +++ b/src/images/wavedrom/transformedatomicinst.edn @@ -1,13 +1,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7']}, - {bits: 5, name: 'rd', type: 2, attr: ['5']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3']}, - {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']}, - {bits: 5, name: 'rs2',type: 4, attr: ['5']}, - {bits: 1, name: 'rl',type: 4, attr: ['1']}, - {bits: 1, name: 'aq',type: 4, attr: ['1']}, - {bits: 5, name: 'funct5', type: 8, attr: ['5']}, + {bits: 7, name: 'opcode', attr: ['7']}, + {bits: 5, name: 'rd', attr: ['5']}, + {bits: 3, name: 'funct3', attr: ['3']}, + {bits: 5, name: 'Addr. Offset', attr: ['5']}, + {bits: 5, name: 'rs2', attr: ['5']}, + {bits: 1, name: 'rl', attr: ['1']}, + {bits: 1, name: 'aq', attr: ['1']}, + {bits: 5, name: 'funct5', attr: ['5']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/transformedloadinst.edn b/src/images/wavedrom/transformedloadinst.edn index 0d6e5ab..3d14134 100644 --- a/src/images/wavedrom/transformedloadinst.edn +++ b/src/images/wavedrom/transformedloadinst.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7']}, - {bits: 5, name: 'rd', type: 2, attr: ['5']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3']}, - {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']}, - {bits: 5, name: '0', type: 4, attr: ['5']}, - {bits: 7, name: '0', type: 8, attr: ['7']}, + {bits: 7, name: 'opcode', attr: ['7']}, + {bits: 5, name: 'rd', attr: ['5']}, + {bits: 3, name: 'funct3', attr: ['3']}, + {bits: 5, name: 'Addr. Offset', attr: ['5']}, + {bits: 5, name: '0', attr: ['5']}, + {bits: 7, name: '0', attr: ['7']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/transformedstoreinst.edn b/src/images/wavedrom/transformedstoreinst.edn index e807ad5..789a6e4 100644 --- a/src/images/wavedrom/transformedstoreinst.edn +++ b/src/images/wavedrom/transformedstoreinst.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7']}, - {bits: 5, name: '0', type: 2, attr: ['5']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3']}, - {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5']}, - {bits: 7, name: '0', type: 8, attr: ['7']}, + {bits: 7, name: 'opcode', attr: ['7']}, + {bits: 5, name: '0', attr: ['5']}, + {bits: 3, name: 'funct3', attr: ['3']}, + {bits: 5, name: 'Addr. Offset', attr: ['5']}, + {bits: 5, name: 'rs2', attr: ['5']}, + {bits: 7, name: '0', attr: ['7']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/transformedvmaccessinst.edn b/src/images/wavedrom/transformedvmaccessinst.edn index 9c7e9e3..65b6a1c 100644 --- a/src/images/wavedrom/transformedvmaccessinst.edn +++ b/src/images/wavedrom/transformedvmaccessinst.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7']}, - {bits: 5, name: 'rd', type: 2, attr: ['5']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3']}, - {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5']}, - {bits: 7, name: 'funct7', type: 8, attr: ['7']}, + {bits: 7, name: 'opcode', attr: ['7']}, + {bits: 5, name: 'rd', attr: ['5']}, + {bits: 3, name: 'funct3', attr: ['3']}, + {bits: 5, name: 'Addr. Offset', attr: ['5']}, + {bits: 5, name: 'rs2', attr: ['5']}, + {bits: 7, name: 'funct7', attr: ['7']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/trap-return.adoc b/src/images/wavedrom/trap-return.adoc index 1e15e2b..7467ad6 100644 --- a/src/images/wavedrom/trap-return.adoc +++ b/src/images/wavedrom/trap-return.adoc @@ -4,10 +4,10 @@ .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM'],}, - {bits: 5, name: 'rd', type: 2, attr: ['5','0'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV'],}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','0'],}, - {bits: 12, name: 'funct12', type: 8, attr: ['12','MRET/SRET',]}, + {bits: 7, name: 'opcode', attr: ['7','SYSTEM'],}, + {bits: 5, name: 'rd', attr: ['5','0'],}, + {bits: 3, name: 'funct3', attr: ['3','PRIV'],}, + {bits: 5, name: 'rs1', attr: ['5','0'],}, + {bits: 12, name: 'funct12', attr: ['12','MRET/SRET',]}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/valu-format.adoc b/src/images/wavedrom/valu-format.adoc index cdd3447..95732e7 100644 --- a/src/images/wavedrom/valu-format.adoc +++ b/src/images/wavedrom/valu-format.adoc @@ -16,10 +16,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPIVV'}, - {bits: 5, name: 'vd', type: 2}, + {bits: 5, name: 'vd'}, {bits: 3, name: 0}, - {bits: 5, name: 'vs1', type: 2}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'vs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -29,10 +29,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPFVV'}, - {bits: 5, name: 'vd / rd', type: 7}, + {bits: 5, name: 'vd / rd'}, {bits: 3, name: 1}, - {bits: 5, name: 'vs1', type: 2}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'vs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -42,10 +42,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPMVV'}, - {bits: 5, name: 'vd / rd', type: 7}, + {bits: 5, name: 'vd / rd'}, {bits: 3, name: 2}, - {bits: 5, name: 'vs1', type: 2}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'vs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -55,10 +55,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: ['OPIVI']}, - {bits: 5, name: 'vd', type: 2}, + {bits: 5, name: 'vd'}, {bits: 3, name: 3}, - {bits: 5, name: 'imm[4:0]', type: 5}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'imm[4:0]'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -68,10 +68,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPIVX'}, - {bits: 5, name: 'vd', type: 2}, + {bits: 5, name: 'vd'}, {bits: 3, name: 4}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -81,10 +81,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPFVF'}, - {bits: 5, name: 'vd', type: 2}, + {bits: 5, name: 'vd'}, {bits: 3, name: 5}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -94,10 +94,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPMVX'}, - {bits: 5, name: 'vd / rd', type: 7}, + {bits: 5, name: 'vd / rd'}, {bits: 3, name: 6}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} diff --git a/src/images/wavedrom/vcfg-format.adoc b/src/images/wavedrom/vcfg-format.adoc index ac0353c..0219e6b 100644 --- a/src/images/wavedrom/vcfg-format.adoc +++ b/src/images/wavedrom/vcfg-format.adoc @@ -12,10 +12,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'vsetvli'}, - {bits: 5, name: 'rd', type: 4}, + {bits: 5, name: 'rd'}, {bits: 3, name: 7}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 11, name: 'vtypei[10:0]', type: 5}, + {bits: 5, name: 'rs1'}, + {bits: 11, name: 'vtypei[10:0]'}, {bits: 1, name: '0'}, ]} .... @@ -24,10 +24,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'vsetivli'}, - {bits: 5, name: 'rd', type: 4}, + {bits: 5, name: 'rd'}, {bits: 3, name: 7}, - {bits: 5, name: 'uimm[4:0]', type: 5}, - {bits: 10, name: 'vtypei[9:0]', type: 5}, + {bits: 5, name: 'uimm[4:0]'}, + {bits: 10, name: 'vtypei[9:0]'}, {bits: 1, name: '1'}, {bits: 1, name: '1'}, ]} @@ -37,10 +37,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'vsetvl'}, - {bits: 5, name: 'rd', type: 4}, + {bits: 5, name: 'rd'}, {bits: 3, name: 7}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'rs2', type: 4}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, {bits: 6, name: 0x00}, {bits: 1, name: 1}, ]} diff --git a/src/images/wavedrom/vmem-format.adoc b/src/images/wavedrom/vmem-format.adoc index f9b25ee..58cc6bf 100644 --- a/src/images/wavedrom/vmem-format.adoc +++ b/src/images/wavedrom/vmem-format.adoc @@ -12,9 +12,9 @@ Format for Vector Load Instructions under LOAD-FP major opcode .... {reg: [ {bits: 7, name: 0x7, attr: 'VL* unit-stride'}, - {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 5, name: 'vd', attr: 'destination of load'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'rs1', attr: 'base address'}, {bits: 5, name: 'lumop'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, @@ -27,10 +27,10 @@ Format for Vector Load Instructions under LOAD-FP major opcode .... {reg: [ {bits: 7, name: 0x7, attr: 'VLS* strided'}, - {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 5, name: 'vd', attr: 'destination of load'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, - {bits: 5, name: 'rs2', attr: 'stride', type: 4}, + {bits: 5, name: 'rs1', attr: 'base address'}, + {bits: 5, name: 'rs2', attr: 'stride'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, @@ -42,10 +42,10 @@ Format for Vector Load Instructions under LOAD-FP major opcode .... {reg: [ {bits: 7, name: 0x7, attr: 'VLX* indexed'}, - {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 5, name: 'vd', attr: 'destination of load'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, - {bits: 5, name: 'vs2', attr: 'address offsets', type: 2}, + {bits: 5, name: 'rs1', attr: 'base address'}, + {bits: 5, name: 'vs2', attr: 'address offsets'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, @@ -66,9 +66,9 @@ Format for Vector Store Instructions under STORE-FP major opcode .... {reg: [ {bits: 7, name: 0x27, attr: 'VS* unit-stride'}, - {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 5, name: 'vs3', attr: 'store data'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'rs1', attr: 'base address'}, {bits: 5, name: 'sumop'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, @@ -81,10 +81,10 @@ Format for Vector Store Instructions under STORE-FP major opcode .... {reg: [ {bits: 7, name: 0x27, attr: 'VSS* strided'}, - {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 5, name: 'vs3', attr: 'store data'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, - {bits: 5, name: 'rs2', attr: 'stride', type: 4}, + {bits: 5, name: 'rs1', attr: 'base address'}, + {bits: 5, name: 'rs2', attr: 'stride'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, @@ -96,10 +96,10 @@ Format for Vector Store Instructions under STORE-FP major opcode .... {reg: [ {bits: 7, name: 0x27, attr: 'VSX* indexed'}, - {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 5, name: 'vs3', attr: 'store data'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, - {bits: 5, name: 'vs2', attr: 'address offsets', type: 2}, + {bits: 5, name: 'rs1', attr: 'base address'}, + {bits: 5, name: 'vs2', attr: 'address offsets'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, diff --git a/src/images/wavedrom/wfi.adoc b/src/images/wavedrom/wfi.adoc index 4447b9f..870e2a1 100644 --- a/src/images/wavedrom/wfi.adoc +++ b/src/images/wavedrom/wfi.adoc @@ -4,10 +4,10 @@ .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM'],}, - {bits: 5, name: 'rd', type: 2, attr: ['5','0'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV'],}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','0'],}, - {bits: 12, name: 'funct12', type: 8, attr: ['12','WFI',]}, -], config: {bits: 32}} + {bits: 7, name: 'opcode', attr: ['7','SYSTEM'],}, + {bits: 5, name: 'rd', attr: ['5','0'],}, + {bits: 3, name: 'funct3', attr: ['3','PRIV'],}, + {bits: 5, name: 'rs1', attr: ['5','0'],}, + {bits: 12, name: 'funct12', attr: ['12','WFI',]}, +], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/zifencei-fetch.adoc b/src/images/wavedrom/zifencei-fetch.adoc index 42e0d6f..660c134 100644 --- a/src/images/wavedrom/zifencei-fetch.adoc +++ b/src/images/wavedrom/zifencei-fetch.adoc @@ -3,9 +3,9 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: 'MISC-MEM', type: 8}, + {bits: 7, name: 'opcode', attr: 'MISC-MEM'}, {bits: 5, name: 'rd', attr: 0}, - {bits: 3, name: 'funct3', attr: 'FENCE.I', type: 8}, + {bits: 3, name: 'funct3', attr: 'FENCE.I'}, {bits: 5, name: 'rs1', attr: 0}, {bits: 12, name: 'func12', attr: 0}, ]} diff --git a/src/images/wavedrom/zifencei-ff.adoc b/src/images/wavedrom/zifencei-ff.adoc index 5ccfae0..24cf87b 100644 --- a/src/images/wavedrom/zifencei-ff.adoc +++ b/src/images/wavedrom/zifencei-ff.adoc @@ -3,10 +3,10 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'FENCE.I'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12', '0'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'FENCE.I']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, + {bits: 12, name: 'funct12', attr: ['12', '0']}, ]} .... diff --git a/src/images/wavedrom/zihintpause-hint.adoc b/src/images/wavedrom/zihintpause-hint.adoc index 4c4a2ed..34c73a7 100644 --- a/src/images/wavedrom/zihintpause-hint.adoc +++ b/src/images/wavedrom/zihintpause-hint.adoc @@ -3,9 +3,9 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: 'MISC-MEM', type: 8}, + {bits: 7, name: 'opcode', attr: 'MISC-MEM'}, {bits: 5, name: 'rd', attr: 0}, - {bits: 3, name: 'funct3', attr: 'PAUSE', type: 8}, + {bits: 3, name: 'funct3', attr: 'PAUSE'}, {bits: 5, name: 'rs1', attr: 0}, {bits: 1, name: 'SW', attr: 0}, {bits: 1, name: 'SR', attr: 0}, diff --git a/src/machine.adoc b/src/machine.adoc index cd2159b..a81f7bb 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -368,93 +368,18 @@ S-level ISA. [[mstatusreg-rv32]] .Machine-mode status (`mstatus`) register for RV32 -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'SIE'}, - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'MIE'}, - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'SPIE'}, - {bits: 1, name: 'UBE'}, - {bits: 1, name: 'MPIE'}, - {bits: 1, name: 'SPP'}, - {bits: 2, name: 'VS[1:0]'}, - {bits: 2, name: 'MPP[1:0]'}, - {bits: 2, name: 'FS[1:0]'}, - {bits: 2, name: 'XS[1:0]'}, - {bits: 1, name: 'MPRV'}, - {bits: 1, name: 'SUM'}, - {bits: 1, name: 'MXR'}, - {bits: 1, name: 'TVM'}, - {bits: 1, name: 'TW'}, - {bits: 1, name: 'TSR'}, - {bits: 1, name: 'SPELP'}, - {bits: 7, name: 'WPRI'}, - {bits: 1, name: 'SD'}, -], config:{lanes: 2, hspace:1024}} -.... +include::images/wavedrom/mstatusreg-rv321.adoc[] [[mstatusreg]] .Machine-mode status (`mstatus`) register for RV64 -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'SIE'}, - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'MIE'}, - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'SPIE'}, - {bits: 1, name: 'UBE'}, - {bits: 1, name: 'MPIE'}, - {bits: 1, name: 'SPP'}, - {bits: 2, name: 'VS[1:0]'}, - {bits: 2, name: 'MPP[1:0]'}, - {bits: 2, name: 'FS[1:0]'}, - {bits: 2, name: 'XS[1:0]'}, - {bits: 1, name: 'MPRV'}, - {bits: 1, name: 'SUM'}, - {bits: 1, name: 'MXR'}, - {bits: 1, name: 'TVM'}, - {bits: 1, name: 'TW'}, - {bits: 1, name: 'TSR'}, - {bits: 1, name: 'SPELP'}, - {bits: 8, name: 'WPRI'}, - {bits: 2, name: 'UXL[1:0]'}, - {bits: 2, name: 'SXL[1:0]'}, - {bits: 1, name: 'SBE'}, - {bits: 1, name: 'MBE'}, - {bits: 1, name: 'GVA'}, - {bits: 1, name: 'MPV'}, - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'MPELP'}, - {bits: 1, name: 'MDT'}, - {bits: 20, name: 'WPRI'}, - {bits: 1, name: 'SD'}, -], config:{lanes: 4, hspace:1024}} -.... +include::images/wavedrom/mstatusreg.adoc[] For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`. [[mstatushreg]] .Additional machine-mode status (`mstatush`) register for RV32. -[wavedrom, ,svg] -.... -{reg: [ - {bits: 4, name: 'WPRI'}, - {bits: 1, name: 'SBE'}, - {bits: 1, name: 'MBE'}, - {bits: 1, name: 'GVA'}, - {bits: 1, name: 'MPV'}, - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'MPELP'}, - {bits: 1, name: 'MDT'}, - {bits: 21, name: 'WPRI'}, -], config:{lanes: 2, hspace:1024}} -.... +include::images/wavedrom/mstatushreg.adoc[] [[privstack]] ===== Privilege and Global Interrupt-Enable Stack in `mstatus` register @@ -573,9 +498,11 @@ by the same write (For RV32, the `MDT` bit is in `mstatush` and the `MIE` bit in When a trap is to be taken into M-mode, if the `MDT` bit is currently 0, it is then set to 1, and the trap is delivered as expected. However, if `MDT` is -already set to 1, then this is an _unexpected trap_. Additionally, when the -Smrnmi extension is implemented, a trap that occurs when executing in M-mode -with the `mnstatus.NMIE` set to 0 is an _unexpected trap_. +already set to 1, then this is an _unexpected trap_. When the Smrnmi extension +is implemented, a trap caused by an RNMI is not considered an _unexpected trap_ +irrespective of the state of the `MDT` bit. A trap caused by an RNMI does not +set the `MDT` bit. However, a trap that occurs when executing in M-mode with +`mnstatus.NMIE` set to 0 is an _unexpected trap_. In the event of a _unexpected trap_, the handling is as follows: @@ -589,26 +516,32 @@ In the event of a _unexpected trap_, the handling is as follows: [NOTE] ==== The consequence of this specification is that on occurrence of double trap the -RNMI handler is not provided with information that a trap would report in the -`mtval` and the `mtval2` registers. This information, if needed, may be obtained +RNMI handler is not provided with information that a trap reports in the +`mtval` and the `mtval2` registers. This information, if needed, can be obtained by the RNMI handler by decoding the instruction at the address in `mnepc` and examining its source register contents. ==== * When the Smrnmi extension is not implemented, or if the Smrnmi extension is implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state - without updating any architectural state including the `pc`. This state + without updating any architectural state, including the `pc`. This state involves ceasing execution, disabling all interrupts (including NMIs), and asserting a `critical-error` signal to the platform. [NOTE] ==== -The actions performed by the platform on assertion of a `critical-error` signal -by a hart are platform specific. The range of possible actions include restarting -the affected hart or restarting the entire platform among others. +The actions performed by the platform when a hart asserts a `critical-error` signal +are platform-specific. The range of possible actions include restarting +the affected hart or restarting the entire platform, among others. ==== -An `MRET` instruction sets the `MDT` bit to 0. +The `MRET` and `SRET` instructions, when executed in M-mode, set the `MDT` bit +to 0. If the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set +to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0. + +The `MNRET` instruction, provided by the Smrnmi extension, sets the `MDT` bit to +0 if the new privilege mode is not M. If it is U, VS, or VU, then `sstatus.SDT` is +also set to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0. [[xlen-control]] ===== Base ISA Control in `mstatus` Register @@ -654,6 +587,21 @@ always be a software bug, but machine operation is well-defined even in this case. ==== +Some HINT instructions are encoded as integer computational instructions that +overwrite their destination register with its current value, e.g., +`c.addi x8, 0`. +When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the +destination register not all equal to bit XLEN-1, it is implementation-defined +whether bits MXLEN..XLEN of the destination register are unchanged or are +overwritten with copies of bit XLEN-1. + +NOTE: This definition allows implementations to elide register writeback for +some HINTs, while allowing them to execute other HINTs in the same manner as +other integer computational instructions. +The implementation choice is observable only by privilege modes with an XLEN +setting greater than the current XLEN; it is invisible to the current +privilege mode. + ===== Memory Privilege in `mstatus` Register The MPRV (Modify PRiVilege) bit modifies the _effective privilege mode_, @@ -2150,28 +2098,10 @@ as shown in <<menvcfgreg>>, that controls certain characteristics of the execution environment for modes less privileged than M. -[#menvcfgreg] +[[menvcfgreg]] .Machine environment configuration (`menvcfg`) register. -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: 'FIOM'}, - {bits: 1, name: 'WPRI'}, - {bits: 1, name: 'LPE'}, - {bits: 1, name: 'SSE'}, - {bits: 2, name: 'CBIE'}, - {bits: 1, name: 'CBCFE'}, - {bits: 1, name: 'CBZE'}, - {bits: 24, name: 'WPRI'}, - {bits: 2, name: 'PMM'}, - {bits: 25, name: 'WPRI'}, - {bits: 1, name: 'DTE'}, - {bits: 1, name: 'CDE'}, - {bits: 1, name: 'ADUE'}, - {bits: 1, name: 'PBMTE'}, - {bits: 1, name: 'STCE'}, -], config:{lanes: 4, hspace:1024}} -.... +include::images/wavedrom/menvcfgreg.adoc[] + If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`, FENCE instructions executed in modes less privileged than M are modified @@ -2273,9 +2203,11 @@ the following rules apply to privilege modes that are less than M: * 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. * The `pte.xwr=010b` encoding in VS/S-stage page tables becomes reserved. -* The `henvcfg.SSE` and `senvcfg.SSE` fields will read as zero and are read-only. * `SSAMOSWAP.W/D` raises an illegal-instruction exception. +When `menvcfg.SSE` is 0, the `henvcfg.SSE` and `senvcfg.SSE` fields are +read-only zero. + The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `menvcfg`. When `menvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not implemented. When Ssdbltrp is not implemented `sstatus.SDT`, `vsstatus.SDT`, and @@ -2295,19 +2227,7 @@ shown in <<mseccfg>>, that controls security features. [[mseccfg]] .Machine security configuration (`mseccfg`) register. -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: 'MML'}, - {bits: 1, name: 'MMWP'}, - {bits: 1, name: 'RLB'}, - {bits: 5, name: 'WPRI'}, - {bits: 1, name: 'USEED'}, - {bits: 1, name: 'SSEED'}, - {bits: 1, name: 'MLPE'}, - {bits: 53, name: 'WPRI'}, -], config:{lanes: 4, hspace:1024}} -.... +include::images/wavedrom/mseccfg.adoc[] The definitions of the SSEED and USEED fields will be furnished by the forthcoming entropy-source extension, Zkr. Their allocations within @@ -2383,8 +2303,9 @@ Simple fixed-frequency systems can use a single clock for both cycle counting and wall-clock time. ==== -Writes to `mtime` and `mtimecmp` are guaranteed to be reflected in MTIP -eventually, but not necessarily immediately. +If the result of the comparison between `mtime` and `mtimecmp` changes, it is +guaranteed to be reflected in MTIP eventually, but not necessarily +immediately. [NOTE] ==== diff --git a/src/naming.adoc b/src/naming.adoc index 0aaa177..6ddb92a 100644 --- a/src/naming.adoc +++ b/src/naming.adoc @@ -88,7 +88,7 @@ closely related alphabetical extension category, IMAFDQLCBKJTPVH. For the indicates the extension is related to the "F" standard extension. If multiple "Z" extensions are named, they should be ordered first by category, then alphabetically within a category—for example, -"Zicsr_Zifencei_Zam". +"Zicsr_Zifencei_Ztso". All multi-letter extensions, including those with the "Z" prefix, must be separated from other multi-letter extensions by an underscore, e.g., diff --git a/src/priv-cfi.adoc b/src/priv-cfi.adoc index 082ceb7..278c7f4 100644 --- a/src/priv-cfi.adoc +++ b/src/priv-cfi.adoc @@ -271,17 +271,6 @@ of as "store/AMO/SS" exceptions, indicating that the trapping instruction is either a store, an AMO, or a shadow stack instruction. ==== -[NOTE] -==== -The H (hypervisor) extension specifies that when a guest-page fault is caused by -an implicit memory access of VS-stage address translation, the reported -exception is either a load or store/AMO guest-page fault based not on the -original instruction type but rather on whether the memory access attempted for -VS-stage translation was a read or a write of memory. VS-stage address -translation can thus cause a shadow stack instruction to raise a load -guest-page-fault exception. -==== - Shadow stack instructions are restricted to accessing shadow stack (`pte.xwr=010b`) pages. Should a shadow stack instruction access a page that is not designated as a shadow stack page and is not marked as read-only diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index 25712c5..76beaa7 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -14,7 +14,7 @@ modules: *Smstateen Extension* + *Smcsrind/Sscsrind Extension* + *Smepmp* + -**Smcntrpmf* + +*Smcntrpmf* + *Smrnmi Extension* + *Smcdeleg* + _Smdbltrp_ + @@ -28,7 +28,8 @@ _Supervisor ISA_ + *Sscofpmf* + _Ssdbltrp_ + *Hypervisor ISA* + -_Shlcofideleg_ +_Shlcofideleg_ + +*Svvptc* |_1.13_ + *1.0* + @@ -48,7 +49,8 @@ _1.13_ + *1.0* + _1.0_ + *1.0* + -_0.1_ +_0.1_ + +*1.0* |_Draft_ + *Ratified* + @@ -68,7 +70,8 @@ _Draft_ + *Ratified* + _Draft_ + *Ratified* + -_Draft_ +_Draft_ + +*Ratified* |=== The following changes have been made since version 1.12 of the Machine and @@ -93,6 +96,7 @@ implemented. * Specified synchronization requirements when changing the PBMTE fields in `menvcfg` and `henvcfg`. * Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension. +* Relaxed behavior of some HINTs when MXLEN > XLEN. Finally, the following clarifications and document improvments have been made since the last document release: @@ -112,6 +116,8 @@ be set to a nonzero value but sometimes not. * Clarified exception behavior of unimplemented or inaccessible CSRs. * Clarified that Svpbmt allows implementations to override additional PMAs. * Replaced the concept of vacant memory regions with inaccessible memory or I/O regions. +* Clarified that timer and count-overflow interrupts' arrival in + interrupt-pending registers is not immediate. [.big]*_Preface to Version 20211203_* diff --git a/src/rnmi.adoc b/src/rnmi.adoc index aef8e9d..e085f6e 100644 --- a/src/rnmi.adoc +++ b/src/rnmi.adoc @@ -1,11 +1,5 @@ [[rnmi]] -== "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 0.5 - -[WARNING] -==== -*Warning! This frozen specification may change before being accepted as -standard by RISC-V International.* -==== +== "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0 The base machine-level architecture supports only unresumable non-maskable interrupts (UNMIs), where the NMI jumps to a handler in diff --git a/src/scalar-crypto.adoc b/src/scalar-crypto.adoc index b3de74a..63064dc 100644 --- a/src/scalar-crypto.adoc +++ b/src/scalar-crypto.adoc @@ -211,118 +211,28 @@ protocols, while ShangMi ciphers are required for use in China. ==== `Zbkb` - Bitmanip instructions for Cryptography These are a subset of the Bitmanipulation Extension `Zbb` which are -particularly useful for Cryptography. - -NOTE: Some of these instructions are defined in the first Bitmanip -ratification package, and some are not ( -<<insns-pack-sc,pack>>, -<<insns-packh-sc,packh>>, -<<insns-packw-sc,packw>>, -<<insns-brev8,brev8>>, -<<insns-zip-sc,zip>>, -<<insns-unzip-sc,unzip>>). -All of the instructions in <<zbkb-sc>> have their complete specification included -in this document, including those _not_ present in the initial -Bitmanip ratification package. -This is to make the present specification complete as a standalone document. -Inevitably there might be small divergences between the Bitmanip and -Scalar Cryptography specification documents as they move at different -paces. -When this happens, assume that the Bitmanip specification has the -most up-to-date version of Bitmanip instructions. -This is an unfortunate but necessary stop-gap while Scalar Cryptography -and Bitmanip are being rapidly iterated on prior to public review. - -[%header,cols="^1,^1,4,8"] -|=== -|RV32 -|RV64 -|Mnemonic -|Instruction - -| ✓ | ✓ | ror | <<insns-ror-sc>> -| ✓ | ✓ | rol | <<insns-rol-sc>> -| ✓ | ✓ | rori | <<insns-rori-sc>> -| | ✓ | rorw | <<insns-rorw-sc>> -| | ✓ | rolw | <<insns-rolw-sc>> -| | ✓ | roriw | <<insns-roriw-sc>> -| ✓ | ✓ | andn | <<insns-andn-sc>> -| ✓ | ✓ | orn | <<insns-orn-sc>> -| ✓ | ✓ | xnor | <<insns-xnor-sc>> -| ✓ | ✓ | pack | <<insns-pack-sc>> -| ✓ | ✓ | packh | <<insns-packh-sc>> -| | ✓ | packw | <<insns-packw-sc>> -| ✓ | ✓ | brev8 | <<insns-brev8>> -| ✓ | ✓ | rev8 | <<insns-rev8-sc>> -| ✓ | | zip | <<insns-zip-sc>> -| ✓ | | unzip | <<insns-unzip-sc>> -|=== +particularly useful for Cryptography. Please refer to <<b-st-ext.adoc#zbkb>>. [[zbkc-sc,Zbkc-sc]] ==== `Zbkc` - Carry-less multiply instructions Constant time carry-less multiply for Galois/Counter Mode. -These are separated from the <<zbkb-sc>> because they +These are separated from the <<b-st-ext.adoc#zbkb>> because they have a considerable implementation overhead which cannot be amortised across other instructions. -NOTE: These instructions are defined in the first Bitmanip -ratification package for the `Zbc` extension. -All of the instructions in <<zbkc-sc>> have their complete specification included -in this document, including those _not_ present in the initial -Bitmanip ratification package. -This is to make the present specification complete as a standalone document. -Inevitably there might be small divergences between the Bitmanip and -Scalar Cryptography specification documents as they move at different -paces. -When this happens, assume that the Bitmanip specification has the -most up-to-date version of Bitmanip instructions. -This is an unfortunate but necessary stop-gap while Scalar Cryptography -and Bitmanip are being rapidly iterated on prior to public review. - -[%header,cols="^1,^1,4,8"] -|=== -|RV32 -|RV64 -|Mnemonic -|Instruction - -| ✓ | ✓ | clmul | <<insns-clmul>> -| ✓ | ✓ | clmulh | <<insns-clmulh-sc>> -|=== +Please refer to <<b-st-ext.adoc#zbkc>>. [[zbkx-sc,Zbkx-sc]] ==== `Zbkx` - Crossbar permutation instructions These instructions are useful for implementing SBoxes in constant time, and potentially with DPA protections. -These are separated from the <<zbkb-sc>> because they +These are separated from the <<b-st-ext.adoc#zbkbc>> because they have an implementation overhead which cannot be amortised across other instructions. -NOTE: All of these instructions are missing from the first Bitmanip -ratification package. -Hence, all of the instructions in <<zbkx-sc>> have their complete specification -included in this document. -This is to make the present specification complete as a standalone document. -Inevitably there might be small divergences between the Bitmanip and -Scalar Cryptography specification documents as they move at different -paces. -When this happens, assume that the Bitmanip specification has the -most up-to-date version of Bitmanip instructions. -This is an unfortunate but necessary stop-gap while Scalar Cryptography -and Bitmanip are being rapidly iterated on prior to public review. - -[%header,cols="^1,^1,4,8"] -|=== -|RV32 -|RV64 -|Mnemonic -|Instruction - -| ✓ | ✓ | xperm8 | <<insns-xperm8>> -| ✓ | ✓ | xperm4 | <<insns-xperm4>> -|=== +Please refer to <<b-st-ext.adoc#zbkx>>. [[zknd,Zknd]] ==== `Zknd` - NIST Suite: AES Decryption @@ -1321,14 +1231,14 @@ Included in:: <<< -[#insns-brev8,reftext="Reverse bits in bytes"] +[#insns-brev8-sc,reftext="Reverse bits in bytes"] ==== brev8 Synopsis:: Reverse the bits in each byte of a source register. Mnemonic:: -brev8, _rd_, _rs_ +brev8 _rd_, _rs_ Encoding:: [wavedrom, , svg] @@ -1336,29 +1246,21 @@ Encoding:: {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, - { bits: 3, name: 0x65 }, + { bits: 3, name: 0x5 }, { bits: 5, name: 'rs' }, - { bits: 12, name: 0x687 }, + { bits: 12, name: 0x687 } ]} .... Description:: This instruction reverses the order of the bits in every byte of a register. -[NOTE] -==== -This instruction is a specific encoding of a more generic instruction which was originally -proposed as part of the RISC-V Bitmanip extension (grevi). Eventually, the more generic -instruction may be standardised. Until then, only the most common instances of it, such as -this, are being included in specifications. -==== - Operation:: [source,sail] -- result : xlenbits = EXTZ(0b0); foreach (i from 0 to sizeof(xlen) by 8) { -result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]); + result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]); }; X(rd) = result; -- @@ -3436,48 +3338,51 @@ Included in:: |=== <<< -[#insns-xperm8,reftext="Crossbar permutation (bytes)"] +[#insns-xperm8-sc,reftext="Crossbar permutation (bytes)"] ==== xperm8 Synopsis:: -Byte-wise lookup of indicies into a vector. +Byte-wise lookup of indices into a vector in registers. Mnemonic:: -xprem8 _rd_, _rs1_, _rs2_ +xperm8 _rd_, _rs1_, _rs2_ Encoding:: [wavedrom, , svg] .... {reg:[ - { bits: 2, name: 0x3 }, - { bits: 5, name: 0xC }, - { bits: 5, name: 'rd'}, - { bits: 3, name: 0x4 }, - { bits: 5, name: 'rs1' }, - { bits: 5, name: 'rs2' }, - { bits: 7, name: 0x14 }, +{bits: 2, name: 0x3}, +{bits: 5, name: 0xc}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x4}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 7, name: 0x14}, ]} .... Description:: -The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 8-bit elements. The -rs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in rs2 replaced by the -indexed element in rs1, or zero if the index into rs2 is out of bounds. +The xperm8 instruction operates on bytes. +The _rs1_ register contains a vector of XLEN/8 8-bit elements. +The _rs2_ register contains a vector of XLEN/8 8-bit indexes. +The result is each element in _rs2_ replaced by the indexed element in _rs1_, +or zero if the index into _rs2_ is out of bounds. Operation:: [source,sail] -- val xperm8_lookup : (bits(8), xlenbits) -> bits(8) function xperm8_lookup (idx, lut) = { -(lut >> (idx @ 0b000))[7..0] + (lut >> (idx @ 0b000))[7..0] } -function clause execute ( XPERM_8 (rs2,rs1,rd)) = { -result : xlenbits = EXTZ(0b0); -foreach(i from 0 to xlen by 8) { -result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1)); -}; -X(rd) = result; -RETIRE_SUCCESS + +function clause execute ( XPERM8 (rs2,rs1,rd)) = { + result : xlenbits = EXTZ(0b0); + foreach(i from 0 to xlen by 8) { + result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1)); + }; + X(rd) = result; + RETIRE_SUCCESS } -- @@ -3488,18 +3393,18 @@ Included in:: |Minimum version |Lifecycle state -|Zbkx (<<#zbkx-sc>>) -|v1.0.0-rc4 +|Zbkx (<<#zbkx>>) +|v1.0 |Ratified |=== <<< -[#insns-xperm4,reftext="Crossbar permutation (nibbles)"] +[#insns-xperm4-sc,reftext="Crossbar permutation (nibbles)"] ==== xperm4 Synopsis:: -Nibble-wise lookup of indicies into a vector. +Nibble-wise lookup of indices into a vector. Mnemonic:: xperm4 _rd_, _rs1_, _rs2_ @@ -3508,35 +3413,38 @@ Encoding:: [wavedrom, , svg] .... {reg:[ - { bits: 2, name: 0x3 }, - { bits: 5, name: 0xC }, - { bits: 5, name: 'rd'}, - { bits: 3, name: 0x2 }, - { bits: 5, name: 'rs1' }, - { bits: 5, name: 'rs2' }, - { bits: 7, name: 0x14 }, +{bits: 2, name: 0x3}, +{bits: 5, name: 0xc}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x2}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 7, name: 0x14}, ]} .... Description:: -The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 4-bit elements. -The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in rs2 replaced by the -indexed element in rs1, or zero if the index into rs2 is out of bounds. +The xperm4 instruction operates on nibbles. +The _rs1_ register contains a vector of XLEN/4 4-bit elements. +The _rs2_ register contains a vector of XLEN/4 4-bit indexes. +The result is each element in _rs2_ replaced by the indexed element in _rs1_, +or zero if the index into _rs2_ is out of bounds. Operation:: [source,sail] -- val xperm4_lookup : (bits(4), xlenbits) -> bits(4) function xperm4_lookup (idx, lut) = { -(lut >> (idx @ 0b00))[3..0] + (lut >> (idx @ 0b00))[3..0] } -function clause execute ( XPERM_4 (rs2,rs1,rd)) = { -result : xlenbits = EXTZ(0b0); -foreach(i from 0 to xlen by 4) { -result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1)); -}; -X(rd) = result; -RETIRE_SUCCESS + +function clause execute ( XPERM4 (rs2,rs1,rd)) = { + result : xlenbits = EXTZ(0b0); + foreach(i from 0 to xlen by 4) { + result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1)); + }; + X(rd) = result; + RETIRE_SUCCESS } -- @@ -3547,8 +3455,8 @@ Included in:: |Minimum version |Lifecycle state -|Zbkx (<<#zbkx-sc>>) -|v1.0.0-rc4 +|Zbkx (<<#zbkx>>) +|v1.0 |Ratified |=== @@ -4269,8 +4177,8 @@ specific instances of `grevi`, `shfli` and `unshfli` respectively. | ✓ | ✓ | clmul | <<insns-clmul-sc>> | ✓ | ✓ | clmulh | <<insns-clmulh-sc>> -| ✓ | ✓ | xperm4 | <<insns-xperm4>> -| ✓ | ✓ | xperm8 | <<insns-xperm8>> +| ✓ | ✓ | xperm4 | <<insns-xperm4-sc>> +| ✓ | ✓ | xperm8 | <<insns-xperm8-sc>> | ✓ | ✓ | ror | <<insns-ror-sc>> | ✓ | ✓ | rol | <<insns-rol-sc>> | ✓ | ✓ | rori | <<insns-rori-sc>> @@ -4283,7 +4191,7 @@ specific instances of `grevi`, `shfli` and `unshfli` respectively. | ✓ | ✓ | pack | <<insns-pack-sc>> | ✓ | ✓ | packh | <<insns-packh-sc>> | | ✓ | packw | <<insns-packw-sc>> -| ✓ | ✓ | brev8 | <<insns-brev8>> +| ✓ | ✓ | brev8 | <<insns-brev8-sc>> | ✓ | ✓ | rev8 | <<insns-rev8-sc>> | ✓ | | zip | <<insns-zip-sc>> | ✓ | | unzip | <<insns-unzip-sc>> diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc index 7e67a25..84f1a09 100644 --- a/src/sscofpmf.adoc +++ b/src/sscofpmf.adoc @@ -71,17 +71,20 @@ count overflow interrupt disable for the associated hpmcounter. Count overflow never results from writes to the mhpmcounter__n__ or mhpmevent__n__ registers, only from hardware increments of counter registers. -This "count overflow interrupt request" signal is treated as a standard local -interrupt that corresponds to bit 13 in the mip/mie/sip/sie registers. The -mip/sip LCOFIP and mie/sie LCOFIE bits are respectively the interrupt-pending -and interrupt-enable bits for this interrupt. ('LCOFI' represents 'Local Count -Overflow Interrupt'.) - -Generation of a "count overflow interrupt request" by an hpmcounter sets the -LCOFIP bit in the mip/sip registers and sets the associated OF bit. The mideleg -register controls the delegation of this interrupt to S-mode versus M-mode. The -LCOFIP bit is cleared by software before servicing the count overflow interrupt -resulting from one or more count overflows. +This count-overflow-interrupt-request signal is treated as a standard local +interrupt that corresponds to bit 13 in the `mip`/`mie`/`sip`/`sie` registers. +The `mip`/`sip` LCOFIP and `mie`/`sie` LCOFIE bits are, respectively, the +interrupt-pending and interrupt-enable bits for this interrupt. +('LCOFI' represents 'Local Count Overflow Interrupt'.) + +Generation of a count-overflow-interrupt request by an `hpmcounter` sets the +associated OF bit. +When an OF bit is set, it eventually, but not necessarily immediately, sets +the LCOFIP bit in the `mip`/`sip` registers. +The LCOFIP bit is cleared by software before servicing the count overflow +interrupt resulting from one or more count overflows. +The `mideleg` register controls the delegation of this interrupt to S-mode +versus M-mode. [NOTE] ==== diff --git a/src/ssdbltrp.adoc b/src/ssdbltrp.adoc index e2b1127..83a98bd 100644 --- a/src/ssdbltrp.adoc +++ b/src/ssdbltrp.adoc @@ -10,6 +10,6 @@ S/HS-mode. The Ssdbltrp extension adds the `menvcfg`.DTE (See <<sec:menvcfg>>) and the `sstatus`.SDT fields (See <<sstatus>>). If the hypervisor extension is additionally implemented, then the extension adds the `henvcfg`.DTE (See -<<sec:henvcfg>>) and the `vstatus`.SDT fields (See <<vstatus>>). +<<sec:henvcfg>>) and the `vsstatus`.SDT fields (See <<vsstatus>>). See <<supv-double-trap>> for the operational details. diff --git a/src/sstc.adoc b/src/sstc.adoc index 8198349..49be41a 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -38,13 +38,15 @@ bits, while accesses to the `stimecmph` CSR access the high 32 bits of `stimecmp The CSR numbers for `stimecmp` / `stimecmph` are 0x14D / 0x15D (within the Supervisor Trap Setup block of CSRs). -A supervisor timer interrupt becomes pending - as reflected in the STIP bit in -the mip and sip registers - whenever time contains a value greater than or -equal to stimecmp, treating the values as unsigned integers. Writes to stimecmp -are guaranteed to be reflected in STIP eventually, but not necessarily -immediately. The interrupt remains posted until stimecmp becomes greater than -time - typically as a result of writing stimecmp. The interrupt will be taken -based on the standard interrupt enable and delegation rules. +A supervisor timer interrupt becomes pending, as reflected in the STIP bit in +the `mip` and `sip` registers whenever `time` contains a value greater than or +equal to `stimecmp`, treating the values as unsigned integers. +If the result of this comparison changes, it is guaranteed to be reflected in +STIP eventually, but not necessarily immediately. +The interrupt remains posted until `stimecmp` becomes greater than `time`, +typically as a result of writing `stimecmp`. +The interrupt will be taken based on the standard interrupt enable and +delegation rules. [NOTE] ==== @@ -122,14 +124,16 @@ The proposed CSR numbers for `vstimecmp` / `vstimecmph` are 0x24D / 0x25D (withi the Virtual Supervisor Registers block of CSRs, and mirroring the CSR numbers for stimecmp/stimecmph). -A virtual supervisor timer interrupt becomes pending - as reflected in the -VSTIP bit in the `hip` register - whenever (`time` + `htimedelta`), truncated to 64 -bits, contains a value greater than or equal to `vstimecmp`, treating the values -as unsigned integers. Writes to `vstimecmp` and `htimedelta` are guaranteed to be -reflected in VSTIP eventually, but not necessarily immediately. The interrupt -remains posted until `vstimecmp` becomes greater than (`time` + `htimedelta`) - -typically as a result of writing `vstimecmp`. The interrupt will be taken based -on the standard interrupt enable and delegation rules while V=1. +A virtual supervisor timer interrupt becomes pending, as reflected in the +VSTIP bit in the `hip` register, whenever (`time` + `htimedelta`), truncated +to 64 bits, contains a value greater than or equal to `vstimecmp`, treating +the values as unsigned integers. +If the result of this comparison changes, it is guaranteed to be reflected in +VSTIP eventually, but not necessarily immediately. +The interrupt remains posted until `vstimecmp` becomes greater than (`time` ++ `htimedelta`), typically as a result of writing `vstimecmp`. +The interrupt will be taken based on the standard interrupt enable and +delegation rules while V=1. [NOTE] ==== diff --git a/src/supervisor.adoc b/src/supervisor.adoc index b212620..d79d733 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -149,6 +149,20 @@ and load and store effective addresses are taken modulo latexmath:[$2^{\text{UXLEN}}$]. For example, when UXLEN=32 and SXLEN=64, user-mode memory accesses reference the lowest 4 GiB of the address space. +Some HINT instructions are encoded as integer computational instructions that +overwrite their destination register with its current value, e.g., +`c.addi x8, 0`. +When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the +destination register not all equal to bit XLEN-1, it is implementation-defined +whether bits SXLEN..XLEN of the destination register are unchanged or are +overwritten with copies of bit XLEN-1. + +NOTE: This definition allows implementations to elide register writeback for +some HINTs, while allowing them to execute other HINTs in the same manner as +other integer computational instructions. +The implementation choice is observable only by S-mode with SXLEN > UXLEN; it +is invisible to U-mode. + [[sum]] ===== Memory Privilege in `sstatus` Register @@ -253,13 +267,13 @@ An `SRET` instruction sets the `SDT` bit to 0. [NOTE] ==== -A trap handler after saving the state needed for resuming from the trap, -including `scause`, `sepc`, and `stval` among others, should clear the `SDT` bit -when it is reentrant. +After a trap handler has saved the state, such as `scause`, `sepc`, +and `stval`, needed for resuming from the trap and is reentrant, it +should clear the `SDT` bit. -Resetting of the `SDT` by an `SRET` enables the trap handler to detect double -trap occuring during the tail phase, where it restores critical state to return -from a trap. +Resetting the `SDT` by an `SRET` enables the trap handler to detect a double +trap that may occur during the tail phase, where it restores critical state +to return from a trap. The consequence of this specification is that if a critical error condition was caused by a guest page-fault, then the GPA will not be available in `mtval2` @@ -270,7 +284,7 @@ instruction in this phase of trap handling is not common. However, not recording the GPA is considered benign because, if required, it can still be obtained -- albeit with added effort -- through the process of walking the page tables. -For a double trap originating in VS-mode, M-mode should redirect the exception +For a double trap that originates in VS-mode, M-mode should redirect the exception to HS-mode by copying the values of M-mode CSRs updated by the trap to HS-mode CSRs and should use an `MRET` to resume execution at the address in `stvec`. @@ -1096,13 +1110,6 @@ If the value held in _rs1_ is not a valid virtual address, then the SFENCE.VMA instruction has no effect. No exception is raised in this case. -When __rs2__≠``x0``, bits SXLEN-1:ASIDMAX of the value held -in _rs2_ are reserved for future standard use. Until their use is -defined by a standard extension, they should be zeroed by software and -ignored by current implementations. Furthermore, if -ASIDLEN<ASIDMAX, the implementation shall ignore bits -ASIDMAX-1:ASIDLEN of the value held in _rs2_. - [NOTE] ==== It is always legal to over-fence, e.g., by fencing only based on a @@ -1114,6 +1121,13 @@ choice not to raise an exception when an invalid virtual address is held in _rs1_ facilitates this type of simplification. ==== +When __rs2__≠``x0``, bits SXLEN-1:ASIDMAX of the value held +in _rs2_ are reserved for future standard use. Until their use is +defined by a standard extension, they should be zeroed by software and +ignored by current implementations. Furthermore, if +ASIDLEN<ASIDMAX, the implementation shall ignore bits +ASIDMAX-1:ASIDLEN of the value held in _rs2_. + An implicit read of the memory-management data structures may return any translation for an address that was valid at any time since the most recent SFENCE.VMA that subsumes that address. The ordering implied by @@ -2227,29 +2241,32 @@ exceptions when A/D bits need be set, instead takes effect. The Svade extension is also defined in <<translation>>. [[sec:svvptc]] -== "Svvptc" Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0 +== "Svvptc" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0 -When the Svvptc extension is implemented, explicit stores that update the Valid -bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will -eventually become visible within a bounded timeframe to subsequent implicit +When the Svvptc extension is implemented, explicit stores by a hart that update +the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart +will eventually become visible within a bounded timeframe to subsequent implicit accesses by that hart to such PTEs. [NOTE] ==== -Typically, PTEs are marked as Valid by the operating system following a -page-fault exception or during system calls for memory mapping. In such cases, -the trap handler commonly employs an `SRET` instruction to return from the trap. -When Svvptc is implemented, the stores it executes to change the Valid bit -of the PTEs from 0 to 1 then become visible to implicit references to those PTEs -within a bounded timeframe. This visibility pertains to the instructions like -the one causing the page fault or those accessing new memory regions. A -memory-management fence can be used to force immediate visibility of these PTE -updates to all implicit references associated with instructions following the -memory-management fence. However, when Svvptc is implemented, visibility (in a -bounded amount of time) is guaranteed and use of a memory-management fence is -not required in these scenarios. While this approach might lead to an occasional -gratuitous page-fault, the performance benefit of omitting the memory-management -fence instructions outweighs the occasional cost of a gratuitous page fault. +Svvptc relieves an operating system from executing certain memory-management +instructions, such as `SFENCE.VMA` or `SINVAL.VMA`, which would normally be used +to synchronize the hart's address-translation caches when a memory-resident PTE +is changed from Invalid to Valid. Synchronizing the hart's address-translation +caches with other forms of updates to a memory-resident PTE, including when a +PTE is changed from Valid to Invalid, requires the use of suitable +memory-management instructions. Svvptc guarantees that a change to a PTE from +Invalid to Valid is made visible within a bounded time, thereby making the +execution of these memory-management instructions redundant. The performance +benefit of eliding these instructions outweighs the cost of an occasional +gratuitous additional page fault that may occur. + +Depending on the microarchitecture, some possible ways to facilitate +implementation of Svvptc include: not having any address-translation caches, not +storing Invalid PTEs in the address-translation caches, automatically evicting +Invalid PTEs using a bounded timer, or making address-translation caches +coherent with store instructions that modify PTEs. ==== //// diff --git a/src/unpriv-cfi.adoc b/src/unpriv-cfi.adoc index 1615d62..a700715 100644 --- a/src/unpriv-cfi.adoc +++ b/src/unpriv-cfi.adoc @@ -554,7 +554,8 @@ that uses shadow stacks is as follows: : ld x1,(sp) # pop link register x1 from regular stack addi sp,sp,8 - sspopchk x1 # fault if x1 not equal to shadow return address + sspopchk x1 # fault if x1 not equal to shadow + # return address ret ---- diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index b8cd859..467d8de 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -1163,13 +1163,13 @@ and `vsetivli`, and in the `rs2` register for `vsetvl`. mf8 # LMUL=1/8 mf4 # LMUL=1/4 mf2 # LMUL=1/2 - m1 # LMUL=1, assumed if m setting absent + m1 # LMUL=1 m2 # LMUL=2 m4 # LMUL=4 m8 # LMUL=8 Examples: - vsetvli t0, a0, e8, ta, ma # SEW= 8, LMUL=1 + vsetvli t0, a0, e8, m1, ta, ma # SEW= 8, LMUL=1 vsetvli t0, a0, e8, m2, ta, ma # SEW= 8, LMUL=2 vsetvli t0, a0, e32, mf2, ta, ma # SEW=32, LMUL=1/2 ---- @@ -1549,19 +1549,19 @@ currently reserved. ==== Vector Unit-Stride Instructions ---- - # Vector unit-stride loads and stores +# Vector unit-stride loads and stores - # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) - vle8.v vd, (rs1), vm # 8-bit unit-stride load - vle16.v vd, (rs1), vm # 16-bit unit-stride load - vle32.v vd, (rs1), vm # 32-bit unit-stride load - vle64.v vd, (rs1), vm # 64-bit unit-stride load +# vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) +vle8.v vd, (rs1), vm # 8-bit unit-stride load +vle16.v vd, (rs1), vm # 16-bit unit-stride load +vle32.v vd, (rs1), vm # 32-bit unit-stride load +vle64.v vd, (rs1), vm # 64-bit unit-stride load - # vs3 store data, rs1 base address, vm is mask encoding (v0.t or <missing>) - vse8.v vs3, (rs1), vm # 8-bit unit-stride store - vse16.v vs3, (rs1), vm # 16-bit unit-stride store - vse32.v vs3, (rs1), vm # 32-bit unit-stride store - vse64.v vs3, (rs1), vm # 64-bit unit-stride store +# vs3 store data, rs1 base address, vm is mask encoding (v0.t or <missing>) +vse8.v vs3, (rs1), vm # 8-bit unit-stride store +vse16.v vs3, (rs1), vm # 16-bit unit-stride store +vse32.v vs3, (rs1), vm # 32-bit unit-stride store +vse64.v vs3, (rs1), vm # 64-bit unit-stride store ---- Additional unit-stride mask load and store instructions are @@ -1572,11 +1572,11 @@ and the destination register is always written with a tail-agnostic policy. ---- - # Vector unit-stride mask load - vlm.v vd, (rs1) # Load byte vector of length ceil(vl/8) +# Vector unit-stride mask load +vlm.v vd, (rs1) # Load byte vector of length ceil(vl/8) - # Vector unit-stride mask store - vsm.v vs3, (rs1) # Store byte vector of length ceil(vl/8) +# Vector unit-stride mask store +vsm.v vs3, (rs1) # Store byte vector of length ceil(vl/8) ---- `vlm.v` and `vsm.v` are encoded with the same `width[2:0]`=0 encoding as @@ -1602,19 +1602,19 @@ and also reduce the cost of mask spill/fill by reducing need to change ==== Vector Strided Instructions ---- - # Vector strided loads and stores +# Vector strided loads and stores - # vd destination, rs1 base address, rs2 byte stride - vlse8.v vd, (rs1), rs2, vm # 8-bit strided load - vlse16.v vd, (rs1), rs2, vm # 16-bit strided load - vlse32.v vd, (rs1), rs2, vm # 32-bit strided load - vlse64.v vd, (rs1), rs2, vm # 64-bit strided load +# vd destination, rs1 base address, rs2 byte stride +vlse8.v vd, (rs1), rs2, vm # 8-bit strided load +vlse16.v vd, (rs1), rs2, vm # 16-bit strided load +vlse32.v vd, (rs1), rs2, vm # 32-bit strided load +vlse64.v vd, (rs1), rs2, vm # 64-bit strided load - # vs3 store data, rs1 base address, rs2 byte stride - vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store - vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store - vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store - vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store +# vs3 store data, rs1 base address, rs2 byte stride +vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store +vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store +vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store +vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store ---- Negative and zero strides are supported. @@ -1648,36 +1648,35 @@ address are required, then an ordered indexed operation can be used. ==== Vector Indexed Instructions ---- - # Vector indexed loads and stores +# Vector indexed loads and stores - # Vector indexed-unordered load instructions - # vd destination, rs1 base address, vs2 byte offsets - vluxei8.v vd, (rs1), vs2, vm # unordered 8-bit indexed load of SEW data - vluxei16.v vd, (rs1), vs2, vm # unordered 16-bit indexed load of SEW data - vluxei32.v vd, (rs1), vs2, vm # unordered 32-bit indexed load of SEW data - vluxei64.v vd, (rs1), vs2, vm # unordered 64-bit indexed load of SEW data +# Vector indexed-unordered load instructions +# vd destination, rs1 base address, vs2 byte offsets +vluxei8.v vd, (rs1), vs2, vm # unordered 8-bit indexed load of SEW data +vluxei16.v vd, (rs1), vs2, vm # unordered 16-bit indexed load of SEW data +vluxei32.v vd, (rs1), vs2, vm # unordered 32-bit indexed load of SEW data +vluxei64.v vd, (rs1), vs2, vm # unordered 64-bit indexed load of SEW data - # Vector indexed-ordered load instructions - # vd destination, rs1 base address, vs2 byte offsets - vloxei8.v vd, (rs1), vs2, vm # ordered 8-bit indexed load of SEW data - vloxei16.v vd, (rs1), vs2, vm # ordered 16-bit indexed load of SEW data - vloxei32.v vd, (rs1), vs2, vm # ordered 32-bit indexed load of SEW data - vloxei64.v vd, (rs1), vs2, vm # ordered 64-bit indexed load of SEW data +# Vector indexed-ordered load instructions +# vd destination, rs1 base address, vs2 byte offsets +vloxei8.v vd, (rs1), vs2, vm # ordered 8-bit indexed load of SEW data +vloxei16.v vd, (rs1), vs2, vm # ordered 16-bit indexed load of SEW data +vloxei32.v vd, (rs1), vs2, vm # ordered 32-bit indexed load of SEW data +vloxei64.v vd, (rs1), vs2, vm # ordered 64-bit indexed load of SEW data - # Vector indexed-unordered store instructions - # vs3 store data, rs1 base address, vs2 byte offsets - vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data - vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data - vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data - vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data - - # Vector indexed-ordered store instructions - # vs3 store data, rs1 base address, vs2 byte offsets - vsoxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data - vsoxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data - vsoxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data - vsoxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data +# Vector indexed-unordered store instructions +# vs3 store data, rs1 base address, vs2 byte offsets +vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data +vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data +vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data +vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data +# Vector indexed-ordered store instructions +# vs3 store data, rs1 base address, vs2 byte offsets +vsoxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data +vsoxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data +vsoxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data +vsoxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data ---- NOTE: The assembler syntax for indexed loads and stores uses @@ -1714,13 +1713,13 @@ operation will not be restarted due to a trap or vector-length trimming. ---- - # Vector unit-stride fault-only-first loads +# Vector unit-stride fault-only-first loads - # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) - vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load - vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load - vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load - vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load +# vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) +vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load +vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load +vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load +vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load ---- ---- @@ -1837,14 +1836,14 @@ The assembler prefixes `vlseg`/`vsseg` are used for unit-stride segment loads and stores respectively. ---- - # Format - vlseg<nf>e<eew>.v vd, (rs1), vm # Unit-stride segment load template - vsseg<nf>e<eew>.v vs3, (rs1), vm # Unit-stride segment store template +# Format +vlseg<nf>e<eew>.v vd, (rs1), vm # Unit-stride segment load template +vsseg<nf>e<eew>.v vs3, (rs1), vm # Unit-stride segment store template - # Examples - vlseg8e8.v vd, (rs1), vm # Load eight vector registers with eight byte fields. +# Examples +vlseg8e8.v vd, (rs1), vm # Load eight vector registers with eight byte fields. - vsseg3e32.v vs3, (rs1), vm # Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory +vsseg3e32.v vs3, (rs1), vm # Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory ---- For loads, the `vd` register will hold the first field loaded from the @@ -1852,27 +1851,27 @@ segment. For stores, the `vs3` register is read to provide the first field to be stored to each segment. ---- - # Example 1 - # Memory structure holds packed RGB pixels (24-bit data structure, 8bpp) - vsetvli a1, t0, e8, ta, ma - vlseg3e8.v v8, (a0), vm - # v8 holds the red pixels - # v9 holds the green pixels - # v10 holds the blue pixels +# Example 1 +# Memory structure holds packed RGB pixels (24-bit data structure, 8bpp) +vsetvli a1, t0, e8, m1, ta, ma +vlseg3e8.v v8, (a0), vm +# v8 holds the red pixels +# v9 holds the green pixels +# v10 holds the blue pixels - # Example 2 - # Memory structure holds complex values, 32b for real and 32b for imaginary - vsetvli a1, t0, e32, ta, ma - vlseg2e32.v v8, (a0), vm - # v8 holds real - # v9 holds imaginary +# Example 2 +# Memory structure holds complex values, 32b for real and 32b for imaginary +vsetvli a1, t0, e32, m1, ta, ma +vlseg2e32.v v8, (a0), vm +# v8 holds real +# v9 holds imaginary ---- There are also fault-only-first versions of the unit-stride instructions. ---- - # Template for vector fault-only-first unit-stride segment loads. - vlseg<nf>e<eew>ff.v vd, (rs1), vm # Unit-stride fault-only-first segment loads +# Template for vector fault-only-first unit-stride segment loads. +vlseg<nf>e<eew>ff.v vd, (rs1), vm # Unit-stride fault-only-first segment loads ---- For fault-only-first segment loads, if an exception is detected partway @@ -1892,20 +1891,20 @@ GPR argument. NOTE: Negative and zero strides are supported. ---- - # Format - vlsseg<nf>e<eew>.v vd, (rs1), rs2, vm # Strided segment loads - vssseg<nf>e<eew>.v vs3, (rs1), rs2, vm # Strided segment stores +# Format +vlsseg<nf>e<eew>.v vd, (rs1), rs2, vm # Strided segment loads +vssseg<nf>e<eew>.v vs3, (rs1), rs2, vm # Strided segment stores - # Examples - vsetvli a1, t0, e8, ta, ma - vlsseg3e8.v v4, (x5), x6 # Load bytes at addresses x5+i*x6 into v4[i], - # and bytes at addresses x5+i*x6+1 into v5[i], - # and bytes at addresses x5+i*x6+2 into v6[i]. +# Examples +vsetvli a1, t0, e8, m1, ta, ma +vlsseg3e8.v v4, (x5), x6 # Load bytes at addresses x5+i*x6 into v4[i], + # and bytes at addresses x5+i*x6+1 into v5[i], + # and bytes at addresses x5+i*x6+2 into v6[i]. - # Examples - vsetvli a1, t0, e32, ta, ma - vssseg2e32.v v2, (x5), x6 # Store words from v2[i] to address x5+i*x6 - # and words from v3[i] to address x5+i*x6+4 +# Examples +vsetvli a1, t0, e32, m1, ta, ma +vssseg2e32.v v2, (x5), x6 # Store words from v2[i] to address x5+i*x6 + # and words from v3[i] to address x5+i*x6+4 ---- Accesses to the fields within each segment can occur in any order, @@ -1928,22 +1927,22 @@ EMUL=(EEW/SEW)*LMUL. The EMUL * NFIELDS {le} 8 constraint applies to the data vector register group. ---- - # Format - vluxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed-unordered segment loads - vloxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed-ordered segment loads - vsuxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed-unordered segment stores - vsoxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed-ordered segment stores +# Format +vluxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed-unordered segment loads +vloxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed-ordered segment loads +vsuxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed-unordered segment stores +vsoxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed-ordered segment stores - # Examples - vsetvli a1, t0, e8, ta, ma - vluxseg3ei8.v v4, (x5), v3 # Load bytes at addresses x5+v3[i] into v4[i], - # and bytes at addresses x5+v3[i]+1 into v5[i], - # and bytes at addresses x5+v3[i]+2 into v6[i]. +# Examples +vsetvli a1, t0, e8, m1, ta, ma +vluxseg3ei8.v v4, (x5), v3 # Load bytes at addresses x5+v3[i] into v4[i], + # and bytes at addresses x5+v3[i]+1 into v5[i], + # and bytes at addresses x5+v3[i]+2 into v6[i]. - # Examples - vsetvli a1, t0, e32, ta, ma - vsuxseg2ei32.v v2, (x5), v5 # Store words from v2[i] to address x5+v5[i] - # and words from v3[i] to address x5+v5[i]+4 +# Examples +vsetvli a1, t0, e32, m1, ta, ma +vsuxseg2ei32.v v2, (x5), v5 # Store words from v2[i] to address x5+v5[i] + # and words from v3[i] to address x5+v5[i]+4 ---- For vector indexed segment loads, the destination vector register @@ -2060,39 +2059,39 @@ environments can mandate the minimum alignment requirements to support an ABI. ---- - # Format of whole register load and store instructions. - vl1r.v v3, (a0) # Pseudoinstruction equal to vl1re8.v +# Format of whole register load and store instructions. +vl1r.v v3, (a0) # Pseudoinstruction equal to vl1re8.v - vl1re8.v v3, (a0) # Load v3 with VLEN/8 bytes held at address in a0 - vl1re16.v v3, (a0) # Load v3 with VLEN/16 halfwords held at address in a0 - vl1re32.v v3, (a0) # Load v3 with VLEN/32 words held at address in a0 - vl1re64.v v3, (a0) # Load v3 with VLEN/64 doublewords held at address in a0 +vl1re8.v v3, (a0) # Load v3 with VLEN/8 bytes held at address in a0 +vl1re16.v v3, (a0) # Load v3 with VLEN/16 halfwords held at address in a0 +vl1re32.v v3, (a0) # Load v3 with VLEN/32 words held at address in a0 +vl1re64.v v3, (a0) # Load v3 with VLEN/64 doublewords held at address in a0 - vl2r.v v2, (a0) # Pseudoinstruction equal to vl2re8.v +vl2r.v v2, (a0) # Pseudoinstruction equal to vl2re8.v - vl2re8.v v2, (a0) # Load v2-v3 with 2*VLEN/8 bytes from address in a0 - vl2re16.v v2, (a0) # Load v2-v3 with 2*VLEN/16 halfwords held at address in a0 - vl2re32.v v2, (a0) # Load v2-v3 with 2*VLEN/32 words held at address in a0 - vl2re64.v v2, (a0) # Load v2-v3 with 2*VLEN/64 doublewords held at address in a0 +vl2re8.v v2, (a0) # Load v2-v3 with 2*VLEN/8 bytes from address in a0 +vl2re16.v v2, (a0) # Load v2-v3 with 2*VLEN/16 halfwords held at address in a0 +vl2re32.v v2, (a0) # Load v2-v3 with 2*VLEN/32 words held at address in a0 +vl2re64.v v2, (a0) # Load v2-v3 with 2*VLEN/64 doublewords held at address in a0 - vl4r.v v4, (a0) # Pseudoinstruction equal to vl4re8.v +vl4r.v v4, (a0) # Pseudoinstruction equal to vl4re8.v - vl4re8.v v4, (a0) # Load v4-v7 with 4*VLEN/8 bytes from address in a0 - vl4re16.v v4, (a0) - vl4re32.v v4, (a0) - vl4re64.v v4, (a0) +vl4re8.v v4, (a0) # Load v4-v7 with 4*VLEN/8 bytes from address in a0 +vl4re16.v v4, (a0) +vl4re32.v v4, (a0) +vl4re64.v v4, (a0) - vl8r.v v8, (a0) # Pseudoinstruction equal to vl8re8.v +vl8r.v v8, (a0) # Pseudoinstruction equal to vl8re8.v - vl8re8.v v8, (a0) # Load v8-v15 with 8*VLEN/8 bytes from address in a0 - vl8re16.v v8, (a0) - vl8re32.v v8, (a0) - vl8re64.v v8, (a0) +vl8re8.v v8, (a0) # Load v8-v15 with 8*VLEN/8 bytes from address in a0 +vl8re16.v v8, (a0) +vl8re32.v v8, (a0) +vl8re64.v v8, (a0) - vs1r.v v3, (a1) # Store v3 to address in a1 - vs2r.v v2, (a1) # Store v2-v3 to address in a1 - vs4r.v v4, (a1) # Store v4-v7 to address in a1 - vs8r.v v8, (a1) # Store v8-v15 to address in a1 +vs1r.v v3, (a1) # Store v3 to address in a1 +vs2r.v v2, (a1) # Store v2-v3 to address in a1 +vs4r.v v4, (a1) # Store v4-v7 to address in a1 +vs8r.v v8, (a1) # Store v8-v15 to address in a1 ---- NOTE: Implementations should raise illegal instruction exceptions on @@ -2109,10 +2108,10 @@ following vector instruction needs a new SEW/LMUL. So, in best case only two instructions (of which only one performs vector operations) are needed to synthesize the effect of the dedicated instruction: ---- - csrr t0, vl # Save current vl (potentially not needed) - vsetvli t1, x0, e8, m8, ta, ma # Maximum VLMAX - vlm.v v0, (a0) # Load mask register - vsetvli x0, t0, <new type> # Restore vl (potentially already present) +csrr t0, vl # Save current vl (potentially not needed) +vsetvli t1, x0, e8, m8, ta, ma # Maximum VLMAX +vlm.v v0, (a0) # Load mask register +vsetvli x0, t0, <new type> # Restore vl (potentially already present) ---- === Vector Memory Alignment Constraints @@ -2306,7 +2305,7 @@ The first vector register group operand can be either single or double-width. ---- -Assembly syntax pattern for vector widening arithmetic instructions +# Assembly syntax pattern for vector widening arithmetic instructions # Double-width result, two single-width sources: 2*SEW = SEW op SEW vwop.vv vd, vs2, vs1, vm # integer vector-vector vd[i] = vs2[i] op vs1[i] @@ -2526,10 +2525,10 @@ instructions with unchanged inputs, destructive accumulations will require an additional move to obtain correct results. ---- - # Example multi-word arithmetic sequence, accumulating into v4 - vmadc.vvm v1, v4, v8, v0 # Get carry into temp register v1 - vadc.vvm v4, v4, v8, v0 # Calc new sum - vmmv.m v0, v1 # Move temp carry into v0 for next word +# Example multi-word arithmetic sequence, accumulating into v4 +vmadc.vvm v1, v4, v8, v0 # Get carry into temp register v1 +vadc.vvm v4, v4, v8, v0 # Calc new sum +vmmv.m v0, v1 # Move temp carry into v0 for next word ---- The subtract with borrow instruction `vsbc` performs the equivalent @@ -2537,27 +2536,27 @@ function to support long word arithmetic for subtraction. There are no subtract with immediate instructions. ---- - # Produce difference with borrow. +# Produce difference with borrow. - # vd[i] = vs2[i] - vs1[i] - v0.mask[i] - vsbc.vvm vd, vs2, vs1, v0 # Vector-vector +# vd[i] = vs2[i] - vs1[i] - v0.mask[i] +vsbc.vvm vd, vs2, vs1, v0 # Vector-vector - # vd[i] = vs2[i] - x[rs1] - v0.mask[i] - vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar +# vd[i] = vs2[i] - x[rs1] - v0.mask[i] +vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar - # Produce borrow out in mask register format +# Produce borrow out in mask register format - # vd.mask[i] = borrow_out(vs2[i] - vs1[i] - v0.mask[i]) - vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector +# vd.mask[i] = borrow_out(vs2[i] - vs1[i] - v0.mask[i]) +vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector - # vd.mask[i] = borrow_out(vs2[i] - x[rs1] - v0.mask[i]) - vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar +# vd.mask[i] = borrow_out(vs2[i] - x[rs1] - v0.mask[i]) +vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar - # vd.mask[i] = borrow_out(vs2[i] - vs1[i]) - vmsbc.vv vd, vs2, vs1 # Vector-vector, no borrow-in +# vd.mask[i] = borrow_out(vs2[i] - vs1[i]) +vmsbc.vv vd, vs2, vs1 # Vector-vector, no borrow-in - # vd.mask[i] = borrow_out(vs2[i] - x[rs1]) - vmsbc.vx vd, vs2, rs1 # Vector-scalar, no borrow-in +# vd.mask[i] = borrow_out(vs2[i] - x[rs1]) +vmsbc.vx vd, vs2, rs1 # Vector-scalar, no borrow-in ---- For `vmsbc`, the borrow is defined to be 1 iff the difference, prior to @@ -2807,9 +2806,9 @@ masked va >= x, any vd Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is `v0`, e.g., ---- - # (a < b) && (b < c) in two instructions when mask-undisturbed - vmslt.vv v0, va, vb # All body elements written - vmslt.vv v0, vb, vc, v0.t # Only update at set mask +# (a < b) && (b < c) in two instructions when mask-undisturbed +vmslt.vv v0, va, vb # All body elements written +vmslt.vv v0, vb, vc, v0.t # Only update at set mask ---- Compares write mask registers, and so always operate under a @@ -2883,21 +2882,21 @@ standard scalar integer multiply/divides, with the same results for extreme inputs. ---- - # Unsigned divide. - vdivu.vv vd, vs2, vs1, vm # Vector-vector - vdivu.vx vd, vs2, rs1, vm # vector-scalar +# Unsigned divide. +vdivu.vv vd, vs2, vs1, vm # Vector-vector +vdivu.vx vd, vs2, rs1, vm # vector-scalar - # Signed divide - vdiv.vv vd, vs2, vs1, vm # Vector-vector - vdiv.vx vd, vs2, rs1, vm # vector-scalar +# Signed divide +vdiv.vv vd, vs2, vs1, vm # Vector-vector +vdiv.vx vd, vs2, rs1, vm # vector-scalar - # Unsigned remainder - vremu.vv vd, vs2, vs1, vm # Vector-vector - vremu.vx vd, vs2, rs1, vm # vector-scalar +# Unsigned remainder +vremu.vv vd, vs2, vs1, vm # Vector-vector +vremu.vx vd, vs2, rs1, vm # vector-scalar - # Signed remainder - vrem.vv vd, vs2, vs1, vm # Vector-vector - vrem.vx vd, vs2, rs1, vm # vector-scalar +# Signed remainder +vrem.vv vd, vs2, vs1, vm # Vector-vector +vrem.vx vd, vs2, rs1, vm # vector-scalar ---- NOTE: The decision to include integer divide and remainder was @@ -3188,14 +3187,14 @@ used to control the right shift amount, which provides the scaling. ---- # Narrowing unsigned clip # SEW 2*SEW SEW - vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) - vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) - vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm)) +vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) +vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) +vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm)) # Narrowing signed clip - vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) - vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) - vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm)) +vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) +vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) +vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm)) ---- For `vnclipu`/`vnclip`, the rounding mode is specified in the `vxrm` @@ -3273,14 +3272,14 @@ elements do not set FP exception flags. ==== Vector Single-Width Floating-Point Add/Subtract Instructions ---- - # Floating-point add - vfadd.vv vd, vs2, vs1, vm # Vector-vector - vfadd.vf vd, vs2, rs1, vm # vector-scalar +# Floating-point add +vfadd.vv vd, vs2, vs1, vm # Vector-vector +vfadd.vf vd, vs2, rs1, vm # vector-scalar - # Floating-point subtract - vfsub.vv vd, vs2, vs1, vm # Vector-vector - vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] - vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] +# Floating-point subtract +vfsub.vv vd, vs2, vs1, vm # Vector-vector +vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] +vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] ---- ==== Vector Widening Floating-Point Add/Subtract Instructions @@ -3302,16 +3301,16 @@ vfwsub.wf vd, vs2, rs1, vm # vector-scalar ==== Vector Single-Width Floating-Point Multiply/Divide Instructions ---- - # Floating-point multiply - vfmul.vv vd, vs2, vs1, vm # Vector-vector - vfmul.vf vd, vs2, rs1, vm # vector-scalar +# Floating-point multiply +vfmul.vv vd, vs2, vs1, vm # Vector-vector +vfmul.vf vd, vs2, rs1, vm # vector-scalar - # Floating-point divide - vfdiv.vv vd, vs2, vs1, vm # Vector-vector - vfdiv.vf vd, vs2, rs1, vm # vector-scalar +# Floating-point divide +vfdiv.vv vd, vs2, vs1, vm # Vector-vector +vfdiv.vf vd, vs2, rs1, vm # vector-scalar - # Reverse floating-point divide vector = scalar / vector - vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] +# Reverse floating-point divide vector = scalar / vector +vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] ---- ==== Vector Widening Floating-Point Multiply @@ -3396,15 +3395,15 @@ vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] This is a unary vector-vector instruction. ---- - # Floating-point square root - vfsqrt.v vd, vs2, vm # Vector-vector square root +# Floating-point square root +vfsqrt.v vd, vs2, vm # Vector-vector square root ---- ==== Vector Floating-Point Reciprocal Square-Root Estimate Instruction ---- - # Floating-point reciprocal square-root estimate to 7 bits. - vfrsqrt7.v vd, vs2, vm +# Floating-point reciprocal square-root estimate to 7 bits. +vfrsqrt7.v vd, vs2, vm ---- This is a unary vector-vector instruction that returns an estimate of @@ -3472,8 +3471,8 @@ with greater estimate accuracy. ==== Vector Floating-Point Reciprocal Estimate Instruction ---- - # Floating-point reciprocal estimate to 7 bits. - vfrec7.v vd, vs2, vm +# Floating-point reciprocal estimate to 7 bits. +vfrec7.v vd, vs2, vm ---- NOTE: An earlier draft version had used the assembler name `vfrece7` @@ -3572,13 +3571,13 @@ in version 2.2 of the RISC-V F/D/Q extension: they perform the `minimumNumber` or `maximumNumber` operation on active elements. ---- - # Floating-point minimum - vfmin.vv vd, vs2, vs1, vm # Vector-vector - vfmin.vf vd, vs2, rs1, vm # vector-scalar +# Floating-point minimum +vfmin.vv vd, vs2, vs1, vm # Vector-vector +vfmin.vf vd, vs2, rs1, vm # vector-scalar - # Floating-point maximum - vfmax.vv vd, vs2, vs1, vm # Vector-vector - vfmax.vf vd, vs2, rs1, vm # vector-scalar +# Floating-point maximum +vfmax.vv vd, vs2, vs1, vm # Vector-vector +vfmax.vf vd, vs2, rs1, vm # vector-scalar ---- ==== Vector Floating-Point Sign-Injection Instructions @@ -3587,14 +3586,14 @@ Vector versions of the scalar sign-injection instructions. The result takes all bits except the sign bit from the vector `vs2` operands. ---- - vfsgnj.vv vd, vs2, vs1, vm # Vector-vector - vfsgnj.vf vd, vs2, rs1, vm # vector-scalar +vfsgnj.vv vd, vs2, vs1, vm # Vector-vector +vfsgnj.vf vd, vs2, rs1, vm # vector-scalar - vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector - vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar +vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector +vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar - vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector - vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar +vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector +vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar ---- NOTE: A vector of floating-point values can be negated using a @@ -3626,27 +3625,27 @@ operand is NaN, whereas the other compares write 0 when either operand is NaN. ---- - # Compare equal - vmfeq.vv vd, vs2, vs1, vm # Vector-vector - vmfeq.vf vd, vs2, rs1, vm # vector-scalar +# Compare equal +vmfeq.vv vd, vs2, vs1, vm # Vector-vector +vmfeq.vf vd, vs2, rs1, vm # vector-scalar - # Compare not equal - vmfne.vv vd, vs2, vs1, vm # Vector-vector - vmfne.vf vd, vs2, rs1, vm # vector-scalar +# Compare not equal +vmfne.vv vd, vs2, vs1, vm # Vector-vector +vmfne.vf vd, vs2, rs1, vm # vector-scalar - # Compare less than - vmflt.vv vd, vs2, vs1, vm # Vector-vector - vmflt.vf vd, vs2, rs1, vm # vector-scalar +# Compare less than +vmflt.vv vd, vs2, vs1, vm # Vector-vector +vmflt.vf vd, vs2, rs1, vm # vector-scalar - # Compare less than or equal - vmfle.vv vd, vs2, vs1, vm # Vector-vector - vmfle.vf vd, vs2, rs1, vm # vector-scalar +# Compare less than or equal +vmfle.vv vd, vs2, vs1, vm # Vector-vector +vmfle.vf vd, vs2, rs1, vm # vector-scalar - # Compare greater than - vmfgt.vf vd, vs2, rs1, vm # vector-scalar +# Compare greater than +vmfgt.vf vd, vs2, rs1, vm # vector-scalar - # Compare greater than or equal - vmfge.vf vd, vs2, rs1, vm # vector-scalar +# Compare greater than or equal +vmfge.vf vd, vs2, rs1, vm # vector-scalar ---- ---- @@ -3675,11 +3674,11 @@ the comparand is a non-NaN constant, the middle two instructions can be omitted. ---- - # Example of implementing isgreater() - vmfeq.vv v0, va, va # Only set where A is not NaN. - vmfeq.vv v1, vb, vb # Only set where B is not NaN. - vmand.mm v0, v0, v1 # Only set where A and B are ordered, - vmfgt.vv v0, va, vb, v0.t # so only set flags on ordered values. +# Example of implementing isgreater() +vmfeq.vv v0, va, va # Only set where A is not NaN. +vmfeq.vv v1, vb, vb # Only set where B is not NaN. +vmand.mm v0, v0, v1 # Only set where A and B are ordered, +vmfgt.vv v0, va, vb, v0.t # so only set flags on ordered values. ---- NOTE: In the above sequence, it is tempting to mask the second `vmfeq` @@ -3694,7 +3693,7 @@ This is a unary vector-vector instruction that operates in the same way as the scalar classify instruction. ---- - vfclass.v vd, vs2, vm # Vector-vector +vfclass.v vd, vs2, vm # Vector-vector ---- The 10-bit mask produced by this instruction is placed in the @@ -3885,15 +3884,15 @@ All operands and results of single-width reduction instructions have the same SEW width. Overflows wrap around on arithmetic sums. ---- - # Simple reductions, where [*] denotes all active elements: - vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) - vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] ) - vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] ) - vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] ) - vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] ) - vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] ) - vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] ) - vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] ) +# Simple reductions, where [*] denotes all active elements: +vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) +vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] ) +vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] ) +vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] ) +vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] ) +vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] ) +vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] ) +vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] ) ---- [[sec-vector-integer-reduce-widen]] @@ -3909,23 +3908,22 @@ elements before summing them. For both `vwredsumu.vs` and `vwredsum.vs`, overflows wrap around. ---- - # Unsigned sum reduction into double-width accumulator - vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW)) +# Unsigned sum reduction into double-width accumulator +vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW)) - # Signed sum reduction into double-width accumulator - vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW)) +# Signed sum reduction into double-width accumulator +vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW)) ---- [[sec-vector-float-reduce]] ==== Vector Single-Width Floating-Point Reduction Instructions ---- - # Simple reductions. - vfredosum.vs vd, vs2, vs1, vm # Ordered sum - vfredusum.vs vd, vs2, vs1, vm # Unordered sum - vfredmax.vs vd, vs2, vs1, vm # Maximum value - vfredmin.vs vd, vs2, vs1, vm # Minimum value - +# Simple reductions. +vfredosum.vs vd, vs2, vs1, vm # Ordered sum +vfredusum.vs vd, vs2, vs1, vm # Unordered sum +vfredmax.vs vd, vs2, vs1, vm # Maximum value +vfredmin.vs vd, vs2, vs1, vm # Minimum value ---- NOTE: Older assembler mnemonic `vfredsum` is retained as alias for `vfredusum`. @@ -4058,14 +4056,14 @@ Mask elements past `vl`, the tail elements, are always updated with a tail-agnostic policy. ---- - vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] - vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) - vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] - vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] - vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] - vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) - vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] - vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) +vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] +vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) +vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] +vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] +vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] +vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) +vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] +vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) ---- NOTE: The previous assembler mnemonics `vmandnot` and `vmornot` have @@ -4076,10 +4074,10 @@ mnemonics can be retained as assembler aliases for compatibility. Several assembler pseudoinstructions are defined as shorthand for common uses of mask logical operations: ---- - vmmv.m vd, vs => vmand.mm vd, vs, vs # Copy mask register - vmclr.m vd => vmxor.mm vd, vd, vd # Clear mask register - vmset.m vd => vmxnor.mm vd, vd, vd # Set mask register - vmnot.m vd, vs => vmnand.mm vd, vs, vs # Invert bits +vmmv.m vd, vs => vmand.mm vd, vs, vs # Copy mask register +vmclr.m vd => vmxor.mm vd, vd, vd # Clear mask register +vmset.m vd => vmxnor.mm vd, vd, vd # Set mask register +vmnot.m vd, vs => vmnand.mm vd, vs, vs # Invert bits ---- NOTE: The `vmmv.m` instruction was previously called `vmcpy.m`, but @@ -4132,7 +4130,7 @@ use. ==== Vector count population in mask `vcpop.m` ---- - vcpop.m rd, vs2, vm +vcpop.m rd, vs2, vm ---- NOTE: This instruction previously had the assembler mnemonic `vpopc.m` @@ -4151,7 +4149,7 @@ The operation can be performed under a mask, in which case only the masked elements are counted. ---- - vcpop.m rd, vs2, v0.t # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] ) +vcpop.m rd, vs2, v0.t # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] ) ---- The `vcpop.m` instruction writes `x[rd]` even if `vl`=0 (with the @@ -4164,7 +4162,7 @@ Traps on `vcpop.m` are always reported with a `vstart` of 0. The ==== `vfirst` find-first-set mask bit ---- - vfirst.m rd, vs2, vm +vfirst.m rd, vs2, vm ---- The `vfirst` instruction finds the lowest-numbered active element of @@ -4356,27 +4354,27 @@ The `viota.m` instruction can be combined with memory scatter instructions (indexed stores) to perform vector compress functions. ---- - # Compact non-zero elements from input memory array to output memory array - # - # size_t compact_non_zero(size_t n, const int* in, int* out) - # { - # size_t i; - # size_t count = 0; - # int *p = out; - # - # for (i=0; i<n; i++) - # { - # const int v = *in++; - # if (v != 0) - # *p++ = v; - # } - # - # return (size_t) (p - out); - # } - # - # a0 = n - # a1 = &in - # a2 = &out +# Compact non-zero elements from input memory array to output memory array +# +# size_t compact_non_zero(size_t n, const int* in, int* out) +# { +# size_t i; +# size_t count = 0; +# int *p = out; +# +# for (i=0; i<n; i++) +# { +# const int v = *in++; +# if (v != 0) +# *p++ = v; +# } +# +# return (size_t) (p - out); +# } +# +# a0 = n +# a1 = &in +# a2 = &out compact_non_zero: li a6, 0 # Clear count of non-zero elements @@ -4406,7 +4404,7 @@ The `vid.v` instruction writes each element's index to the destination vector register group, from 0 to `vl`-1. ---- - vid.v vd, vm # Write element ID to destination. +vid.v vd, vm # Write element ID to destination. ---- The instruction can be masked. Masking does not change the @@ -4516,8 +4514,8 @@ undisturbed/agnostic policy is followed for inactive elements. ===== Vector Slideup Instructions ---- - vslideup.vx vd, vs2, rs1, vm # vd[i+x[rs1]] = vs2[i] - vslideup.vi vd, vs2, uimm, vm # vd[i+uimm] = vs2[i] +vslideup.vx vd, vs2, rs1, vm # vd[i+x[rs1]] = vs2[i] +vslideup.vi vd, vs2, uimm, vm # vd[i+uimm] = vs2[i] ---- For `vslideup`, the value in `vl` specifies the maximum number of destination @@ -4529,13 +4527,13 @@ Destination elements _OFFSET_ through `vl`-1 are written if unmasked and if _OFFSET_ < `vl`. ---- - vslideup behavior for destination elements (`vstart` < `vl`) +vslideup behavior for destination elements (`vstart` < `vl`) - OFFSET is amount to slideup, either from x register or a 5-bit immediate +OFFSET is amount to slideup, either from x register or a 5-bit immediate - 0 <= i < min(vl, max(vstart, OFFSET)) Unchanged - max(vstart, OFFSET) <= i < vl vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled - vl <= i < VLMAX Follow tail policy + 0 <= i < min(vl, max(vstart, OFFSET)) Unchanged +max(vstart, OFFSET) <= i < vl vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled + vl <= i < VLMAX Follow tail policy ---- The destination vector register group for `vslideup` cannot overlap @@ -4549,8 +4547,8 @@ input vectors during execution, and enables restart with non-zero ===== Vector Slidedown Instructions ---- - vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+x[rs1]] - vslidedown.vi vd, vs2, uimm, vm # vd[i] = vs2[i+uimm] +vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+x[rs1]] +vslidedown.vi vd, vs2, uimm, vm # vd[i] = vs2[i+uimm] ---- For `vslidedown`, the value in `vl` specifies the maximum number of @@ -4564,15 +4562,14 @@ using an unsigned integer in the `x` register specified by `rs1`, or a If XLEN > SEW, _OFFSET_ is _not_ truncated to SEW bits. ---- - vslidedown behavior for source elements for element i in slide (`vstart` < `vl`) - 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] - VLMAX <= i+OFFSET src[i] = 0 - - vslidedown behavior for destination element i in slide (`vstart` < `vl`) - 0 <= i < vstart Unchanged - vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled - vl <= i < VLMAX Follow tail policy +vslidedown behavior for source elements for element i in slide (`vstart` < `vl`) + 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] + VLMAX <= i+OFFSET src[i] = 0 +vslidedown behavior for destination element i in slide (`vstart` < `vl`) + 0 <= i < vstart Unchanged + vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled + vl <= i < VLMAX Follow tail policy ---- ===== Vector Slide1up @@ -4582,7 +4579,7 @@ also allow a scalar integer value to be inserted at the vacated element position. ---- - vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] +vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] ---- The `vslide1up` instruction places the `x` register argument at @@ -4603,12 +4600,12 @@ past `vl` are handled according to the current tail policy (Section ---- - vslide1up behavior when vl > 0 +vslide1up behavior when vl > 0 - i < vstart unchanged - 0 = i = vstart vd[i] = x[rs1] if v0.mask[i] enabled - max(vstart, 1) <= i < vl vd[i] = vs2[i-1] if v0.mask[i] enabled - vl <= i < VLMAX Follow tail policy + i < vstart unchanged + 0 = i = vstart vd[i] = x[rs1] if v0.mask[i] enabled +max(vstart, 1) <= i < vl vd[i] = vs2[i-1] if v0.mask[i] enabled + vl <= i < VLMAX Follow tail policy ---- The `vslide1up` instruction requires that the destination vector @@ -4619,7 +4616,7 @@ Otherwise, the instruction encoding is reserved. ===== Vector Floating-Point Slide1up Instruction ---- - vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] +vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] ---- The `vfslide1up` instruction is defined analogously to `vslide1up`, @@ -4637,7 +4634,7 @@ past `vl` are handled according to the current tail policy (Section <<sec-agnostic>>). ---- - vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] +vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] ---- The `vslide1down` instruction places the `x` register argument at @@ -4649,12 +4646,12 @@ XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored. ---- - vslide1down behavior +vslide1down behavior - i < vstart unchanged - vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled - vstart <= i = vl-1 vd[vl-1] = x[rs1] if v0.mask[i] enabled - vl <= i < VLMAX Follow tail policy + i < vstart unchanged +vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled +vstart <= i = vl-1 vd[vl-1] = x[rs1] if v0.mask[i] enabled + vl <= i < VLMAX Follow tail policy ---- NOTE: The `vslide1down` instruction can be used to load values into a @@ -4667,7 +4664,7 @@ contents of a vector register, albeit slowly, with multiple repeated ===== Vector Floating-Point Slide1down Instruction ---- - vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] +vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] ---- The `vfslide1down` instruction is defined analogously to `vslide1down`, @@ -4729,7 +4726,7 @@ contiguous elements at the start of the destination vector register group. ---- - vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled +vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled ---- The vector mask register specified by `vs1` indicates which of the @@ -4740,16 +4737,16 @@ elements according to the current tail policy (Section <<sec-agnostic>>). ---- - Example use of vcompress instruction +Example use of vcompress instruction - 8 7 6 5 4 3 2 1 0 Element number +8 7 6 5 4 3 2 1 0 Element number - 1 1 0 1 0 0 1 0 1 v0 - 8 7 6 5 4 3 2 1 0 v1 - 1 2 3 4 5 6 7 8 9 v2 - vsetivli t0, 9, e8, m1, tu, ma - vcompress.vm v2, v1, v0 - 1 2 3 4 8 7 5 2 0 v2 +1 1 0 1 0 0 1 0 1 v0 +8 7 6 5 4 3 2 1 0 v1 +1 2 3 4 5 6 7 8 9 v2 + vsetivli t0, 9, e8, m1, tu, ma + vcompress.vm v2, v1, v0 +1 2 3 4 8 7 5 2 0 v2 ---- `vcompress` is encoded as an unmasked instruction (`vm=1`). The equivalent @@ -4775,30 +4772,30 @@ There is no inverse `vdecompress` provided, as this operation can be readily synthesized using iota and a masked vrgather: ---- - Desired functionality of 'vdecompress' - 7 6 5 4 3 2 1 0 # vid +Desired functionality of 'vdecompress' +7 6 5 4 3 2 1 0 # vid - e d c b a # packed vector of 5 elements - 1 0 0 1 1 1 0 1 # mask vector of 8 elements - p q r s t u v w # destination register before vdecompress + e d c b a # packed vector of 5 elements +1 0 0 1 1 1 0 1 # mask vector of 8 elements +p q r s t u v w # destination register before vdecompress - e q r d c b v a # result of vdecompress +e q r d c b v a # result of vdecompress ---- ---- - # v0 holds mask - # v1 holds packed data - # v11 holds input expanded vector and result - viota.m v10, v0 # Calc iota from mask in v0 - vrgather.vv v11, v1, v10, v0.t # Expand into destination +# v0 holds mask +# v1 holds packed data +# v11 holds input expanded vector and result +viota.m v10, v0 # Calc iota from mask in v0 +vrgather.vv v11, v1, v10, v0.t # Expand into destination ---- ---- - p q r s t u v w # v11 destination register - e d c b a # v1 source vector - 1 0 0 1 1 1 0 1 # v0 mask vector +p q r s t u v w # v11 destination register + e d c b a # v1 source vector +1 0 0 1 1 1 0 1 # v0 mask vector - 4 4 4 3 2 1 1 0 # v10 result of viota.m - e q r d c b v a # v11 destination after vrgather using viota.m under mask +4 4 4 3 2 1 1 0 # v10 result of viota.m +e q r d c b v a # v11 destination after vrgather using viota.m under mask ---- ==== Whole Vector Register Move @@ -4838,12 +4835,12 @@ related `vmerge` encoding, and it is unlikely the `vsmul` instruction would benefit from an immediate form. ---- - vmv<nr>r.v vd, vs2 # General form +vmv<nr>r.v vd, vs2 # General form - vmv1r.v v1, v2 # Copy v1=v2 - vmv2r.v v10, v12 # Copy v10=v12; v11=v13 - vmv4r.v v4, v8 # Copy v4=v8; v5=v9; v6=v10; v7=v11 - vmv8r.v v0, v8 # Copy v0=v8; v1=v9; ...; v7=v15 +vmv1r.v v1, v2 # Copy v1=v2 +vmv2r.v v10, v12 # Copy v10=v12; v11=v13 +vmv4r.v v4, v8 # Copy v4=v8; v5=v9; v6=v10; v7=v11 +vmv8r.v v0, v8 # Copy v0=v8; v1=v9; ...; v7=v15 ---- The source and destination vector register numbers must be aligned diff --git a/src/zabha.adoc b/src/zabha.adoc index 26529a5..932aacf 100644 --- a/src/zabha.adoc +++ b/src/zabha.adoc @@ -1,4 +1,4 @@ -== "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0.0 +== "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 The A-extension offers atomic memory operation (AMO) instructions for _words_, _doublewords_, and _quadwords_ (only for `AMOCAS`). The absence of atomic |