1 files changed, 27 insertions, 20 deletions
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc
index 25712c5..0e53842 100644
--- a/src/priv-preface.adoc
+++ b/src/priv-preface.adoc
@@ -1,24 +1,24 @@
 [colophon]
 = Preface
 
-[.big]*_Preface to Version 20240528_*
+[.big]*_Preface to Version 20241017_*
 
 This document describes the RISC-V privileged architecture. This
-release, version 20240528, contains the following versions of the RISC-V ISA
+release, version 20241017, contains the following versions of the RISC-V ISA
 modules:
 
 [%autowidth,float="center",align="center",cols="^,<,^",options="header",]
 |===
 |Module |Version |Status
-|_Machine ISA_ +
+|*Machine ISA* +
 *Smstateen Extension* +
 *Smcsrind/Sscsrind Extension* +
 *Smepmp* +
-**Smcntrpmf* +
+*Smcntrpmf* +
 *Smrnmi Extension* +
 *Smcdeleg* +
-_Smdbltrp_ +
-_Supervisor ISA_ +
+*Smdbltrp* +
+*Supervisor ISA* +
 *Svade Extension* +
 *Svnapot Extension* + 
 *Svpbmt Extension* +  
@@ -26,19 +26,20 @@ _Supervisor ISA_ +
 *Svadu Extension* +
 *Sstc* +
 *Sscofpmf* +
-_Ssdbltrp_ +
+*Ssdbltrp* +
 *Hypervisor ISA* +
-_Shlcofideleg_
+*Shlcofideleg* +
+*Svvptc*
 
-|_1.13_ +
+|*1.13* +
+*1.0* +
 *1.0* +
 *1.0* +
 *1.0* +
 *1.0* +
 *1.0* +
 *1.0* +
-_1.0_ +
-_1.13_ +
+*1.13* +
 *1.0* +
 *1.0* +
 *1.0* +
@@ -46,19 +47,18 @@ _1.13_ +
 *1.0* +
 *1.0* +
 *1.0* +
-_1.0_ +
 *1.0* +
-_0.1_
+*1.0* +
+*1.0* +
+*1.0*
 
-|_Draft_ +
+|*Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
-_Draft_ +
-_Draft_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
@@ -66,9 +66,12 @@ _Draft_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
-_Draft_ +
 *Ratified* +
-_Draft_
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified*
 |===
 
 The following changes have been made since version 1.12 of the Machine and
@@ -92,9 +95,10 @@ implemented.
 * Defined hardware error and software check exception codes.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
-* Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
+* Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension.
+* Relaxed behavior of some HINTs when MXLEN > XLEN.
 
-Finally, the following clarifications and document improvments have been made
+Finally, the following clarifications and document improvements have been made
 since the last document release:
 
 * Transliterated the document from LaTeX into AsciiDoc.
@@ -112,6 +116,9 @@ be set to a nonzero value but sometimes not.
 * Clarified exception behavior of unimplemented or inaccessible CSRs.
 * Clarified that Svpbmt allows implementations to override additional PMAs.
 * Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
+* Clarified that timer and count-overflow interrupts' arrival in
+  interrupt-pending registers is not immediate.
+* Clarified that MXR affects only explicit memory accesses.
 
 [.big]*_Preface to Version 20211203_*