143 files changed, 254 insertions, 515 deletions
diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc
index ff6e3f3..abc9ec3 100644
--- a/src/a-st-ext.adoc
+++ b/src/a-st-ext.adoc
@@ -54,7 +54,7 @@ same address domain.
 [[sec:lrsc]]
 === "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
 
-include::images/wavedrom/load-reserve-st-conditional.adoc[]
+include::images/wavedrom/load-reserve-st-conditional.edn[]
 
 Complex atomic memory operations on a single memory word or doubleword
 are performed with the load-reserved (LR) and store-conditional (SC)
@@ -355,7 +355,7 @@ substantially easier to provide in some microarchitectural styles.
 [[sec:amo]]
 === "Zaamo" Extension for Atomic Memory Operations
 
-include::images/wavedrom/atomic-mem.adoc[]
+include::images/wavedrom/atomic-mem.edn[]
 
 The atomic memory operation (AMO) instructions perform read-modify-write
 operations for multiprocessor synchronization and are encoded with an
diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc
index fa26a78..7f23978 100644
--- a/src/b-st-ext.adoc
+++ b/src/b-st-ext.adoc
@@ -191,7 +191,7 @@ along with their specific mapping:
 
 |&#10003;
 |&#10003;
-|orc.b _rd_, _rs1_, _rs2_
+|orc.b _rd_, _rs_
 |<<#insns-orc_b>>
 |
 |&#10003;
@@ -2386,6 +2386,13 @@ Included in::
 |Ratified
 |===
 
+NOTE: For RV32, the `pack` instruction with _rs2_=`x0` is the `zext.h`
+instruction.
+Hence, for RV32, any extension that contains the `pack` instruction also
+contains the `zext.h` instruction (but not necessarily the `c.zext.h`
+instruction, which is only guaranteed to exist if both the Zcb and Zbb
+extensions are implemented).
+
 <<<
 [#insns-packh,reftext="Pack low bytes of registers"]
 ==== packh
@@ -2484,6 +2491,13 @@ Included in::
 |Ratified
 |===
 
+NOTE: For RV64, the `packw` instruction with _rs2_=`x0` is the `zext.h`
+instruction.
+Hence, for RV64, any extension that contains the `packw` instruction also
+contains the `zext.h` instruction (but not necessarily the `c.zext.h`
+instruction, which is only guaranteed to exist if both the Zcb and Zbb
+extensions are implemented).
+
 <<<
 [#insns-rev8,reftext="Byte-reverse register"]
 ==== rev8
diff --git a/src/bfloat16.adoc b/src/bfloat16.adoc
index ba3e8bc..531484a 100644
--- a/src/bfloat16.adoc
+++ b/src/bfloat16.adoc
@@ -308,7 +308,7 @@ This extension provides the minimal set of instructions needed to enable scalar
 of the BF16 format. It enables BF16 as an interchange format as it provides conversion
 between BF16 values and FP32 values. 
 
-This extension requires the single-precision floating-point extension
+This extension depends upon the single-precision floating-point extension
 `F`, and the `FLH`, `FSH`, `FMV.X.H`, and `FMV.H.X` instructions as
 defined in the `Zfh` extension.
 
@@ -372,7 +372,7 @@ This extension provides the minimal set of instructions needed to enable vector
 format. It enables BF16 as an interchange format as it provides conversion between BF16 values
 and FP32 values.
 
-This extension requires either the
+This extension depends upon either the
 "V" extension or the `Zve32f` embedded vector extension.
 
 [NOTE]
@@ -428,7 +428,7 @@ the desired rounding mode.
 This extension provides
 a vector widening BF16 mul-add instruction that accumulates into FP32. 
 
-This extension requires the `Zvfbfmin` extension and the `Zfbfmin` extension.
+This extension depends upon the `Zvfbfmin` extension and the `Zfbfmin` extension.
 
 [%autowidth]
 [%header,cols="2,4"]
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc
index 97aca5f..c79bcc7 100644
--- a/src/c-st-ext.adoc
+++ b/src/c-st-ext.adoc
@@ -49,7 +49,7 @@ and/or D) is also implemented. In addition, RV32C includes a compressed
 jump and link instruction to compress short-range subroutine calls,
 where the same opcode is used to compress ADDIW for RV64C and RV128C.
 
-[TIP]
+[NOTE]
 ====
 Double-precision loads and stores are a significant fraction of static
 and dynamic instructions, hence the motivation to include them in the
@@ -100,7 +100,7 @@ instructions in one C instruction.
 It is important to note that the C extension is not designed to be a
 stand-alone ISA, and is meant to be used alongside a base ISA.
 
-[TIP]
+[NOTE]
 ====
 Variable-length instruction sets have long been used to improve code
 density. For example, the IBM Stretch cite:[stretch], developed in the late 1950s, had
@@ -217,7 +217,7 @@ For many RVC instructions, zero-valued immediates are disallowed and
 encoding space for other instructions requiring fewer operand bits.
 
 //[[cr-register]]
-//include::images/wavedrom/cr-register.adoc[]
+//include::images/wavedrom/cr-register.edn[]
 //.Compressed 16-bit RVC instructions
 //(((compressed, 16-bit)))
 
@@ -297,7 +297,7 @@ registers.
 
 ==== Stack-Pointer-Based Loads and Stores
 
-include::images/wavedrom/c-sp-load-store.adoc[]
+include::images/wavedrom/c-sp-load-store.edn[]
 [[c-sp-load-store]]
 //.Stack-Pointer-Based Loads and Stores--these instructions use the CI format.
 
@@ -334,7 +334,7 @@ register _rd_. It computes its effective address by adding the
 _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
 expands to `fld rd, offset(x2)`.
 
-include::images/wavedrom/c-sp-load-store-css.adoc[]
+include::images/wavedrom/c-sp-load-store-css.edn[]
 [[c-sp-load-store-css]]
 //.Stack-Pointer-Based Loads and Stores--these instructions use the CSS format.
 
@@ -409,7 +409,7 @@ attain the greatest code size reduction.
 ==== Register-Based Loads and Stores
 
 [[reg-based-ldnstr]]
-include::images/wavedrom/reg-based-ldnstr.adoc[]
+include::images/wavedrom/reg-based-ldnstr.edn[]
 //.Compressed, register-based load and stores--these instructions use the CL format.
 (((compressed, register-based load and store)))
 These instructions use the CL format.
@@ -446,7 +446,7 @@ _zero_-extended offset, scaled by 8, to the base address in register
 `fld rd′, offset(rs1′)`.
 
 [[c-cs-format-ls]]
-include::images/wavedrom/c-cs-format-ls.adoc[]
+include::images/wavedrom/c-cs-format-ls.edn[]
 //.Compressed, CS format load and store--these instructions use the CS format.
 (((compressed, cs-format load and store)))
 
@@ -490,7 +490,7 @@ instructions. As with base RVI instructions, the offsets of all RVC
 control transfer instructions are in multiples of 2 bytes.
 
 [[c-cj-format-ls]]
-include::images/wavedrom/c-cj-format-ls.adoc[]
+include::images/wavedrom/c-cj-format-ls.edn[]
 //.Compressed, CJ format load and store--these instructions use the CJ format.
 (((compressed, cj-format load and store)))
 
@@ -507,7 +507,7 @@ the jump (`pc+2`) to the link register, `x1`. C.JAL expands to
 `jal x1, offset`.
 
 [[c-cr-format-ls]]
-include::images/wavedrom/c-cr-format-ls.adoc[]
+include::images/wavedrom/c-cr-format-ls.edn[]
 //.Compressed, CR format load and store--these instructions use the CR format.
 (((compressed, cr-format load and store)))
 
@@ -526,7 +526,7 @@ latexmath:[$\textit{rs1}{\neq}\texttt{x0}$]; the code point with
 latexmath:[$\textit{rs1}{=}\texttt{x0}$] corresponds to the C.EBREAK
 instruction.
 
-[TIP]
+[NOTE]
 ====
 Strictly speaking, C.JALR does not expand exactly to a base RVI
 instruction as the value added to the PC to form the link address is 2
@@ -535,7 +535,7 @@ bytes is only a very minor change to the base microarchitecture.
 ====
 
 [[c-cb-format-ls]]
-include::images/wavedrom/c-cb-format-ls.adoc[]
+include::images/wavedrom/c-cb-format-ls.edn[]
 //.Compressed, CB format load and store--these instructions use the CB format.
 (((compressed, cb-format load and store)))
 
@@ -562,7 +562,7 @@ The two constant-generation instructions both use the CI instruction
 format and can target any integer register.
 
 [[c-integer-const-gen]]
-include::images/wavedrom/c-integer-const-gen.adoc[]
+include::images/wavedrom/c-integer-const-gen.edn[]
 //.Integer constant generation format.
 (((compressed, integer constant generation)))
 
@@ -587,7 +587,7 @@ These integer register-immediate operations are encoded in the CI format
 and perform operations on an integer register and a 6-bit immediate.
 
 [[c-integer-register-immediate]]
-include::images/wavedrom/c-int-reg-immed.adoc[]
+include::images/wavedrom/c-int-reg-immed.edn[]
 //.Integer register-immediate format.
 (((compressed, integer register-immediate)))
 
@@ -620,7 +620,7 @@ always 16-byte aligned.
 ====
 
 [[c-ciw]]
-include::images/wavedrom/c-ciw.adoc[]
+include::images/wavedrom/c-ciw.edn[]
 //.CIW format.
 (((compressed, CIW)))
 C.ADDI4SPN is a CIW-format instruction that adds a _zero_-extended
@@ -632,7 +632,7 @@ _nzuimm_≠0; the code points with _nzuimm_=0 are
 reserved.
 
 [[c-ci]]
-include::images/wavedrom/c-ci.adoc[]
+include::images/wavedrom/c-ci.edn[]
 //.CI format.
 (((compressed, CI)))
 
@@ -650,7 +650,7 @@ all base ISAs, the code points with `_rd_=x0` are HINTs, except those
 with _shamt[5]_=1 in RV32C.
 
 [[c-srli-srai]]
-include::images/wavedrom/c-srli-srai.adoc[]
+include::images/wavedrom/c-srli-srai.edn[]
 //.C-SRLI-SRAI format.
 (((compressed, C.SRLI, C.SRAI)))
 
@@ -686,7 +686,7 @@ that RV128C will not be frozen at the same point as RV32C and RV64C, to
 allow evaluation of typical usage of 128-bit address-space codes.
 ====
 [[c-andi]]
-include::images/wavedrom/c-andi.adoc[]
+include::images/wavedrom/c-andi.edn[]
 //.C.ANDI format
 (((compressed, C.ANDI)))
 
@@ -698,7 +698,7 @@ expands to `andi rd′, rd′, imm`.
 ==== Integer Register-Register Operations
 
 [[c-cr]]
-include::images/wavedrom/c-int-reg-to-reg-cr-format.adoc[]
+include::images/wavedrom/c-int-reg-to-reg-cr-format.edn[]
 //C.CR format
 ((((compressed. C.CR))))
 These instructions use the CR format.
@@ -707,7 +707,7 @@ C.MV copies the value in register _rs2_ into register _rd_. C.MV expands
 into `add rd, x0, rs2`. C.MV is only valid when
 `rs2≠x0` the code points with `rs2=x0` correspond to the C.JR instruction. The code points with `rs2≠x0` and `rd=x0` are HINTs.
 
-[TIP]
+[NOTE]
 ====
 _C.MV expands to a different instruction than the canonical MV
 pseudoinstruction, which instead uses ADDI. Implementations that handle
@@ -722,7 +722,7 @@ valid when `rs2≠x0` the code points with `rs2=x0` correspond to the C.JALR
 and C.EBREAK instructions. The code points with `rs2≠x0` and rd=x0 are HINTs.
 
 [[c-ca]]
-include::images/wavedrom/c-int-reg-to-reg-ca-format.adoc[]
+include::images/wavedrom/c-int-reg-to-reg-ca-format.edn[]
 //C.CA format
 ((((compressed. C.CA))))
 
@@ -771,7 +771,7 @@ improvement in static and dynamic compression.
 ==== Defined Illegal Instruction
 
 [[c-def-illegal-inst]]
-include::images/wavedrom/c-def-illegal-inst.adoc[]
+include::images/wavedrom/c-def-illegal-inst.edn[]
 ((((compressed. C.DIINST))))
 
 A 16-bit instruction with all bits zero is permanently reserved as an
@@ -791,7 +791,7 @@ non-existent memory regions.
 ==== NOP Instruction
 
 [[c-nop-instr]]
-include::images/wavedrom/c-nop-instr.adoc[]
+include::images/wavedrom/c-nop-instr.edn[]
 ((((compressed. C.NOPINSTR))))
 
 `C.NOP` is a CI-format instruction that does not change any user-visible
@@ -802,7 +802,7 @@ _imm_=0; the code points with _imm_≠0 encode HINTs.
 ==== Breakpoint Instruction
 
 [[c-breakpoint-instr]]
-include::images/wavedrom/c-breakpoint-instr.adoc[]
+include::images/wavedrom/c-breakpoint-instr.edn[]
 ((((compressed. C.BREAKPOINTINSTR))))
 
 Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`,
diff --git a/src/colophon.adoc b/src/colophon.adoc
index 5f9ef72..42820d7 100644
--- a/src/colophon.adoc
+++ b/src/colophon.adoc
@@ -33,8 +33,8 @@ h|Extension h|Version h|Status
 |*Zmmul* |*1.0* |*Ratified*
 |*A* |*2.1* |*Ratified*
 |*Zawrs* |*1.01* |*Ratified*
-|*Zacas* |*1.0* |*Ratifed*
-|*Zabha* |*1.0* |*Ratifed*
+|*Zacas* |*1.0* |*Ratified*
+|*Zabha* |*1.0* |*Ratified*
 |*RVWMO* |*2.0* |*Ratified*
 |*Ztso* |*1.0* |*Ratified*
 |*CMO* |*1.0* |*Ratified*
diff --git a/src/counters.adoc b/src/counters.adoc
index f4a34af..7ec7210 100644
--- a/src/counters.adoc
+++ b/src/counters.adoc
@@ -14,7 +14,7 @@ counters (CYCLE, TIME, and INSTRET), which have dedicated functions
 (cycle count, real-time clock, and instructions retired, respectively).
 The Zicntr extension depends on the Zicsr extension.
 
-[TIP]
+[NOTE]
 ====
 We recommend provision of these basic counters in implementations as
 they are essential for basic performance analysis, adaptive and dynamic
@@ -27,7 +27,7 @@ Some execution environments might prohibit access to counters, for
 example, to impede timing side-channel attacks.
 ====
 
-include::images/wavedrom/counters-diag.adoc[]
+include::images/wavedrom/counters-diag.edn[]
 
 
 For base ISAs with XLEN&#8805;64, CSR instructions can access
@@ -35,7 +35,7 @@ the full 64-bit CSRs directly. In particular, the RDCYCLE, RDTIME, and
 RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`,
 `time`, and `instret` counters.
 
-[TIP]
+[NOTE]
 ====
 The counter pseudoinstructions are mapped to the read-only
 `csrrs rd, counter, x0` canonical form, but the other read-only CSR
@@ -47,7 +47,7 @@ For base ISAs with XLEN=32, the Zicntr extension enables the three
 RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 bits, and
 the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the
 upper 32 bits of the respective counters.
-[TIP]
+[NOTE]
 ====
 We required the counters be 64 bits wide, even when XLEN=32, as
 otherwise it is very difficult for software to determine if values have
@@ -67,7 +67,7 @@ overflow in practice. The rate at which the cycle counter advances will
 depend on the implementation and operating environment. The execution
 environment should provide a means to determine the current rate
 (cycles/second) at which the cycle counter is incrementing.
-[TIP]
+[NOTE]
 ====
 RDCYCLE is intended to return the number of cycles executed by the
 processor core, not the hart. Precisely defining what is a "core" is
@@ -128,7 +128,7 @@ should be constant within a small error bound. The environment should
 provide a means to determine the accuracy of the clock (i.e., the
 maximum relative error between the nominal and actual real-time clock
 periods).
-[TIP]
+[NOTE]
 ====
 On some simple platforms, cycle count might represent a valid
 implementation of RDTIME, in which case RDTIME and RDCYCLE may return
@@ -141,7 +141,7 @@ bound should be set based on the requirements of the platform.
 
 The real-time clocks of all harts must be synchronized to within one
 tick of the real-time clock.
-[TIP]
+[NOTE]
 ====
 As with other architectural mandates, it suffices to appear "as if"
 harts are synchronized to within one tick of the real-time clock, i.e.,
@@ -154,7 +154,7 @@ hart from some arbitrary start point in the past. RDINSTRETH is only
 present when XLEN=32 and reads bits 63-32 of the same instruction
 counter. The underlying 64-bit counter should never overflow in
 practice.
-[TIP]
+[NOTE]
 ====
 Instructions that cause synchronous exceptions, including ECALL and
 EBREAK, are not considered to retire and hence do not increment the
@@ -180,7 +180,7 @@ hardware performance counters, `hpmcounter3-hpmcounter31`. When
 XLEN=32, the upper 32 bits of these performance counters are accessible
 via additional CSRs `hpmcounter3h- hpmcounter31h`. The Zihpm extension
 depends on the Zicsr extension.
-[TIP]
+[NOTE]
 ====
 In some applications, it is important to be able to read multiple
 counters at the same instant in time. When run under a multitasking
@@ -202,7 +202,7 @@ exception or may return a constant value.
 The execution environment should provide a means to determine the number
 and width of the implemented counters, and an interface to configure the
 events to be counted by each counter.
-[TIP]
+[NOTE]
 ====
 For execution environments implemented on RISC-V privileged platforms,
 the privileged architecture manual describes privileged CSRs controlling
diff --git a/src/d-st-ext.adoc b/src/d-st-ext.adoc
index 7c5eb4c..fcd90c4 100644
--- a/src/d-st-ext.adoc
+++ b/src/d-st-ext.adoc
@@ -58,7 +58,7 @@ so, the _n_ least-significant bits of the input are used as
 the input value, otherwise the input value is treated as an
 _n_-bit canonical NaN.
 
-[TIP]
+[NOTE]
 ====
 Earlier versions of this document did not define the behavior of feeding
 the results of narrower or wider operands into an operation, except to
@@ -103,7 +103,7 @@ value from the floating-point registers to memory.
 The double-precision value may be a NaN-boxed single-precision value.
 ====
 
-include::images/wavedrom/double-ls.adoc[]
+include::images/wavedrom/double-ls.edn[]
 [[double-ls]]
 //.Double-precision load and store
 
@@ -119,7 +119,7 @@ The double-precision floating-point computational instructions are
 defined analogously to their single-precision counterparts, but operate
 on double-precision operands and produce double-precision results.
 
-include::images/wavedrom/double-fl-compute.adoc[]
+include::images/wavedrom/double-fl-compute.edn[]
 [[fl-compute]]
 //.Double-precision float computational
 
@@ -143,7 +143,7 @@ All floating-point to integer and integer to floating-point conversion
 instructions round according to the _rm_ field. Note FCVT.D.W[U] always
 produces an exact result and is unaffected by rounding mode.
 
-include::images/wavedrom/double-fl-convert-mv.adoc[]
+include::images/wavedrom/double-fl-convert-mv.edn[]
 [[fl-convert-mv]]
 //.Double-precision float convert and move
 
@@ -157,7 +157,7 @@ never round.
 (((double-precision, to single-precision)))
 (((single-precision, to double-precision )))
 
-include::images/wavedrom/fcvt-sd-ds.adoc[]
+include::images/wavedrom/fcvt-sd-ds.edn[]
 [[fcvt-sd-ds]]
 //.Double-precision FCVT.S.D and FCVT.D.S
 
@@ -166,7 +166,7 @@ FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision
 sign-injection instruction.
 //FSGNJ.D, FSGNJN.D, and FSGNJX.D
 
-include::images/wavedrom/fsjgnjnx-d.adoc[]
+include::images/wavedrom/fsjgnjnx-d.edn[]
 //.Double-precision sign-injection
 
 For XLEN&#8805;64 only, instructions are provided to move bit
@@ -180,11 +180,11 @@ register _rd_.
 FMV.X.D and FMV.D.X do not modify the bits being transferred; in
 particular, the payloads of non-canonical NaNs are preserved.
 
-include::images/wavedrom/d-xwwx.adoc[]
+include::images/wavedrom/d-xwwx.edn[]
 [[fmvxddx]]
 //.Double-precision float move to _rd_
 
-[TIP]
+[NOTE]
 ====
 Early versions of the RISC-V ISA had additional instructions to allow
 RV32 systems to transfer between the upper and lower portions of a
@@ -214,7 +214,7 @@ analogously to their single-precision counterparts, but operate on
 double-precision operands.
 (((floating-point, compare)))
 
-include::images/wavedrom/double-fl-compare.adoc[]
+include::images/wavedrom/double-fl-compare.edn[]
 [[fl-compare]]
 //.Double-precision float compare
 
@@ -225,8 +225,6 @@ defined analogously to its single-precision counterpart, but operates on
 double-precision operands.
 (((floating-point, classify)))
 
-include::images/wavedrom/double-fl-class.adoc[]
+include::images/wavedrom/double-fl-class.edn[]
 [[fl-class]]
 //.Double-precision float classify
-
-
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc
index 96d5b44..a5a1816 100644
--- a/src/f-st-ext.adoc
+++ b/src/f-st-ext.adoc
@@ -21,7 +21,7 @@ instructions operate on values in the floating-point register file.
 Floating-point load and store instructions transfer floating-point
 values between registers and memory. Instructions to transfer values to and from the integer register file are also provided.
 
-[TIP]
+[NOTE]
 ====
 We considered a unified register file for both integer and
 floating-point values as this simplifies software register allocation
@@ -87,7 +87,7 @@ operations and holds the accrued exception flags, as shown in <<fcsr>>.
 
 [[fcsr, Floating-Point Control and Status Register]]
 .Floating-point control and status register
-include::images/wavedrom/float-csr.adoc[]
+include::images/wavedrom/float-csr.edn[]
 
 The `fcsr` register can be read and written with the FRCSR and FSCSR
 instructions, which are assembler pseudoinstructions built on the
@@ -189,7 +189,7 @@ quiet bit. For single-precision floating-point, this corresponds to the pattern
 (((NaN, generation)))
 (((NaN, propagation)))
 
-[TIP]
+[NOTE]
 ====
 We considered propagating NaN payloads, as is recommended by the
 standard, but this decision would have increased hardware cost.
@@ -231,7 +231,7 @@ signals.
 
 Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register _rs1_ and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register _rd_. FSW stores a single-precision value from floating-point register _rs2_ to memory.
 
-include::images/wavedrom/sp-load-store-2.adoc[]
+include::images/wavedrom/sp-load-store-2.edn[]
 [[sp-ldst]]
 //.SP load and store
 
@@ -283,7 +283,7 @@ minimumNumber and maximumNumber operations, rather than the IEEE
 handling of signaling NaNs.
 ====
 
-include::images/wavedrom/spfloat.adoc[]
+include::images/wavedrom/spfloat.edn[]
 [[spfloat]]
 //.Single-Precision Floating-Point Computational Instructions
 (((floating point, fused multiply-add)))
@@ -315,7 +315,7 @@ RISC-V FNMSUB and FNMADD instruction names are swapped compared to x86
 and ARM.
 ====
 
-include::images/wavedrom/spfloat2.adoc[]
+include::images/wavedrom/spfloat2.edn[]
 [[fnmaddsub]]
 //.F[N]MADD/F[N]MSUB instructions
 
@@ -389,7 +389,7 @@ All floating-point conversion instructions set the Inexact exception
 flag if the rounded result differs from the operand value and the
 Invalid exception flag is not set.
 
-include::images/wavedrom/spfloat-cn-cmp.adoc[]
+include::images/wavedrom/spfloat-cn-cmp.edn[]
 [[fcvt]]
 //.SP float convert and move
 
@@ -405,7 +405,7 @@ FSGNJN.S _rx, ry, ry_ moves the negation of _ry_ to _rx_ (assembler
 pseudoinstruction FNEG.S _rx, ry_); and FSGNJX.S _rx, ry, ry_ moves the absolute value of _ry_ to _rx_ (assembler pseudoinstruction FABS.S _rx,
 ry_).
 
-include::images/wavedrom/spfloat-sign-inj.adoc[]
+include::images/wavedrom/spfloat-sign-inj.edn[]
 [[inj]]
 
 [NOTE]
@@ -428,11 +428,11 @@ preserved.
 The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.
 ====
 
-include::images/wavedrom/spfloat-mv.adoc[]
+include::images/wavedrom/spfloat-mv.edn[]
 [[spfloat-mv]]
 //.SP floating point move
 
-[TIP]
+[NOTE]
 ====
 The base floating-point ISA was defined so as to allow implementations
 to employ an internal recoding of the floating-point format in registers to simplify handling of subnormal values and possibly to reduce functional unit latency. To this end, the F extension avoids
@@ -454,7 +454,7 @@ _signaling_ comparisons: that is, they set the invalid operation
 exception flag if either input is NaN. FEQ.S performs a _quiet_
 comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN.
 
-include::images/wavedrom/spfloat-comp.adoc[]
+include::images/wavedrom/spfloat-comp.edn[]
 [[spfloat-comp]]
 //.SP floating point compare
 
@@ -478,7 +478,7 @@ _rd_ are cleared. Note that exactly one bit in _rd_ will be set.
 FCLASS.S does not set the floating-point exception flags.
 (((floating-point, classification)))
 
-include::images/wavedrom/spfloat-classify.adoc[]
+include::images/wavedrom/spfloat-classify.edn[]
 [[spfloat-classify]]
 //.SP floating point classify
 
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc
index 167a809..6887f4d 100644
--- a/src/hypervisor.adoc
+++ b/src/hypervisor.adoc
@@ -158,6 +158,7 @@ In this chapter, we use the term _HSXLEN_ to refer to the effective XLEN
 when executing in HS-mode, and _VSXLEN_ to refer to the effective XLEN
 when executing in VS-mode.
 
+[[sec:hstatus]]
 ==== Hypervisor Status (`hstatus`) Register 
 
 The `hstatus` register is an HSXLEN-bit read/write register formatted as
@@ -179,7 +180,7 @@ The VSXL field controls the effective XLEN for VS-mode (known as
 VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN). When
 HSXLEN=32, the VSXL field does not exist, and VSXLEN=32. When HSXLEN=64,
 VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,
-shown in <<misabase>> on page <<misabase, 19>>. In particular, an
+shown in <<misabase>>. In particular, an
 implementation may make VSXL be a read-only field whose value always
 ensures that VSXLEN=HSXLEN.
 
@@ -1233,7 +1234,7 @@ controls the privilege level of the access. The explicit memory access
 is done as though in VU-mode when SPVP=0, and as though in VS-mode when
 SPVP=1. As usual when V=1, two-stage address translation is applied, and
 the HS-level `sstatus`.SUM is ignored. HS-level `sstatus`.MXR makes
-execute-only pages readable for both stages of address translation
+execute-only pages readable by explicit loads for both stages of address translation
 (VS-stage and G-stage), whereas `vsstatus`.MXR affects only the first
 translation stage (VS-stage).
 
@@ -1601,7 +1602,7 @@ there is no option to disable two-stage address translation when V=1,
 either stage of translation can be effectively disabled by zeroing the
 corresponding `vsatp` or `hgatp` register.
 
-The `vsstatus` field MXR, which makes execute-only pages readable, only
+The `vsstatus` field MXR, which makes execute-only pages readable by explicit loads, only
 overrides VS-stage page protection. Setting MXR at VS-level does not
 override guest-physical page protections. Setting MXR at HS-level,
 however, overrides both VS-stage and G-stage execute-only permissions.
@@ -2481,7 +2482,7 @@ with the encodings of basic loads and stores, as illustrated by
 <<pseudoinsts-basis>>.
 
 [[pseudoinsts-basis]]
-.Standard instructions corresponding to the special psudoinstructions of <<pseudoinsts>>.
+.Standard instructions corresponding to the special pseudoinstructions of <<pseudoinsts>>.
 [%autowidth,float="center",align="center",cols="<,<",options="header"]
 |===
 |Encoding |Instruction
diff --git a/src/images/wavedrom/atomic-mem.adoc b/src/images/wavedrom/atomic-mem.edn
index 1e95eb4..1e95eb4 100644
--- a/src/images/wavedrom/atomic-mem.adoc
+++ b/src/images/wavedrom/atomic-mem.edn
diff --git a/src/images/wavedrom/c-andi.adoc b/src/images/wavedrom/c-andi.edn
index 3ea3206..3ea3206 100644
--- a/src/images/wavedrom/c-andi.adoc
+++ b/src/images/wavedrom/c-andi.edn
diff --git a/src/images/wavedrom/c-breakpoint-instr.adoc b/src/images/wavedrom/c-breakpoint-instr.edn
index 6ae1890..6ae1890 100644
--- a/src/images/wavedrom/c-breakpoint-instr.adoc
+++ b/src/images/wavedrom/c-breakpoint-instr.edn
diff --git a/src/images/wavedrom/c-cb-format-ls.adoc b/src/images/wavedrom/c-cb-format-ls.edn
index 5c90133..5c90133 100644
--- a/src/images/wavedrom/c-cb-format-ls.adoc
+++ b/src/images/wavedrom/c-cb-format-ls.edn
diff --git a/src/images/wavedrom/c-ci.adoc b/src/images/wavedrom/c-ci.edn
index aacf2be..aacf2be 100644
--- a/src/images/wavedrom/c-ci.adoc
+++ b/src/images/wavedrom/c-ci.edn
diff --git a/src/images/wavedrom/c-ciw.adoc b/src/images/wavedrom/c-ciw.edn
index b167e1f..b167e1f 100644
--- a/src/images/wavedrom/c-ciw.adoc
+++ b/src/images/wavedrom/c-ciw.edn
diff --git a/src/images/wavedrom/c-cj-format-ls.adoc b/src/images/wavedrom/c-cj-format-ls.edn
index d5fa6d1..d5fa6d1 100644
--- a/src/images/wavedrom/c-cj-format-ls.adoc
+++ b/src/images/wavedrom/c-cj-format-ls.edn
diff --git a/src/images/wavedrom/c-cr-format-ls.adoc b/src/images/wavedrom/c-cr-format-ls.edn
index b989e2c..b989e2c 100644
--- a/src/images/wavedrom/c-cr-format-ls.adoc
+++ b/src/images/wavedrom/c-cr-format-ls.edn
diff --git a/src/images/wavedrom/c-cs-format-ls.adoc b/src/images/wavedrom/c-cs-format-ls.edn
index 31f4ccf..31f4ccf 100644
--- a/src/images/wavedrom/c-cs-format-ls.adoc
+++ b/src/images/wavedrom/c-cs-format-ls.edn
diff --git a/src/images/wavedrom/c-def-illegal-inst.adoc b/src/images/wavedrom/c-def-illegal-inst.edn
index 414a19e..414a19e 100644
--- a/src/images/wavedrom/c-def-illegal-inst.adoc
+++ b/src/images/wavedrom/c-def-illegal-inst.edn
diff --git a/src/images/wavedrom/c-int-reg-immed.adoc b/src/images/wavedrom/c-int-reg-immed.edn
index f509065..f509065 100644
--- a/src/images/wavedrom/c-int-reg-immed.adoc
+++ b/src/images/wavedrom/c-int-reg-immed.edn
diff --git a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn
index 67e77b0..67e77b0 100644
--- a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc
+++ b/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn
diff --git a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn
index ddfa0f8..ddfa0f8 100644
--- a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc
+++ b/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn
diff --git a/src/images/wavedrom/c-integer-const-gen.adoc b/src/images/wavedrom/c-integer-const-gen.edn
index b6ae85b..977ddb0 100644
--- a/src/images/wavedrom/c-integer-const-gen.adoc
+++ b/src/images/wavedrom/c-integer-const-gen.edn
@@ -4,7 +4,7 @@
 ....
 {reg: [
   {bits: 2, name: 'op', attr: ['2','C1', 'C1']},
-  {bits: 5, name: 'imm[4:0]',    attr: ['5','imm[4:0]','imm[16:12]']},
+  {bits: 5, name: 'imm[4:0]',    attr: ['5','imm[4:0]','nzimm[16:12]']},
   {bits: 5, name: 'rd',     attr: ['5','dest != 0', 'dest != {0, 2}']},
   {bits: 1, name: 'imm[5]',    attr: ['1','imm[5]', 'nzimm[17]'],},
   {bits: 3, name: 'funct3',    attr: ['3','C.LI', 'C.LUI'],},
diff --git a/src/images/wavedrom/c-mop.adoc b/src/images/wavedrom/c-mop.edn
index 9b850a5..9b850a5 100644
--- a/src/images/wavedrom/c-mop.adoc
+++ b/src/images/wavedrom/c-mop.edn
diff --git a/src/images/wavedrom/c-nop-instr.adoc b/src/images/wavedrom/c-nop-instr.edn
index 89da752..89da752 100644
--- a/src/images/wavedrom/c-nop-instr.adoc
+++ b/src/images/wavedrom/c-nop-instr.edn
diff --git a/src/images/wavedrom/c-sp-load-store-css.adoc b/src/images/wavedrom/c-sp-load-store-css.edn
index a398c7f..a398c7f 100644
--- a/src/images/wavedrom/c-sp-load-store-css.adoc
+++ b/src/images/wavedrom/c-sp-load-store-css.edn
diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.edn
index f890ac8..f890ac8 100644
--- a/src/images/wavedrom/c-sp-load-store.adoc
+++ b/src/images/wavedrom/c-sp-load-store.edn
diff --git a/src/images/wavedrom/c-srli-srai.adoc b/src/images/wavedrom/c-srli-srai.edn
index 78a1076..78a1076 100644
--- a/src/images/wavedrom/c-srli-srai.adoc
+++ b/src/images/wavedrom/c-srli-srai.edn
diff --git a/src/images/wavedrom/counters-diag.adoc b/src/images/wavedrom/counters-diag.edn
index a29d567..a29d567 100644
--- a/src/images/wavedrom/counters-diag.adoc
+++ b/src/images/wavedrom/counters-diag.edn
diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.edn
index 30ad1b3..30ad1b3 100644
--- a/src/images/wavedrom/cr-register.adoc
+++ b/src/images/wavedrom/cr-register.edn
diff --git a/src/images/wavedrom/cr-registers-new.adoc b/src/images/wavedrom/cr-registers-new.adoc
deleted file mode 100644
index 05331c8..0000000
--- a/src/images/wavedrom/cr-registers-new.adoc
+++ /dev/null
@@ -1,62 +0,0 @@
-[wavedrom, ,svg]
-....
-### CR : Register
-${wd({reg: [
-  {bits: 2, name: 'op' },
-  {bits: 5, name: 'rs2' },
-  {bits: 5, name: 'rd / rs1ʹ },
-  {bits: 4, name: 'funct4' },
-
-  {bits: 2, name: 'op' },
-  {bits: 5, name: 'imm' },
-  {bits: 5, name: 'rd / rs1' },
-  {bits: 1, name: 'imm' },
-  {bits: 3, name: 'funct3' },
-
-  {bits: 2, name: 'op' },
-  {bits: 5, name: 'rs2' },
-  {bits: 6, name: 'imm' },
-  {bits: 3, name: 'funct3' },
-
-  {bits: 2, name: 'op' },
-  {bits: 3, name: 'rdʹ' },
-  {bits: 8, name: 'imm' },
-  {bits: 3, name: 'funct3' },
-
-  {bits: 2, name: 'op' },
-  {bits: 3, name: 'rdʹ' },
-  {bits: 2, name: 'imm' },
-  {bits: 3, name: 'rs1ʹ' },
-  {bits: 3, name: 'imm' },
-  {bits: 3, name: 'funct3' },
-
-  {bits: 2, name: 'op' },
-  {bits: 3, name: 'rs2ʹ' },
-  {bits: 2, name: 'imm' },
-  {bits: 3, name: 'rs1ʹ' },
-  {bits: 3, name: 'imm' },
-  {bits: 3, name: 'funct3' },
-
-  {bits: 2, name: 'op' },
-  {bits: 3, name: 'rs2ʹ' },
-  {bits: 2, name: 'funct2' },
-  {bits: 3, name: 'rd` / rs1ʹ' },
-  {bits: 6, name: 'funct6' },
-
-  {bits: 2, name: 'op' },
-  {bits: 5, name: 'offset' },
-  {bits: 3, name: 'rd` / rs1ʹ' },
-  {bits: 3, name: 'offset' },
-  {bits: 3, name: 'funct3' },
-
-  {bits: 2,  name: 'op' },
-  {bits: 11, name: 'jump target' },
-  {bits: 3,  name: 'funct3' },
-], config: {
-  hflip: true,
-  compact: true,
-  bits: 16 * 9, lanes: 9,
-  margin: {right: width / 4},
-  label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS : Store', 'CA : Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']}
-}})}
-....
diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.edn
index 19d853e..19d853e 100644
--- a/src/images/wavedrom/csr-instr.adoc
+++ b/src/images/wavedrom/csr-instr.edn
diff --git a/src/images/wavedrom/ct-conditional.adoc b/src/images/wavedrom/ct-conditional.edn
index e021907..e021907 100644
--- a/src/images/wavedrom/ct-conditional.adoc
+++ b/src/images/wavedrom/ct-conditional.edn
diff --git a/src/images/wavedrom/ct-unconditional-2.adoc b/src/images/wavedrom/ct-unconditional-2.edn
index 95f103e..95f103e 100644
--- a/src/images/wavedrom/ct-unconditional-2.adoc
+++ b/src/images/wavedrom/ct-unconditional-2.edn
diff --git a/src/images/wavedrom/ct-unconditional.adoc b/src/images/wavedrom/ct-unconditional.edn
index 3dfbd94..3dfbd94 100644
--- a/src/images/wavedrom/ct-unconditional.adoc
+++ b/src/images/wavedrom/ct-unconditional.edn
diff --git a/src/images/wavedrom/d-xwwx.adoc b/src/images/wavedrom/d-xwwx.edn
index e5fb261..e5fb261 100644
--- a/src/images/wavedrom/d-xwwx.adoc
+++ b/src/images/wavedrom/d-xwwx.edn
diff --git a/src/images/wavedrom/division-op.adoc b/src/images/wavedrom/division-op.edn
index 0dff0e3..0dff0e3 100644
--- a/src/images/wavedrom/division-op.adoc
+++ b/src/images/wavedrom/division-op.edn
diff --git a/src/images/wavedrom/double-fl-class.adoc b/src/images/wavedrom/double-fl-class.edn
index 2779d1a..2779d1a 100644
--- a/src/images/wavedrom/double-fl-class.adoc
+++ b/src/images/wavedrom/double-fl-class.edn
diff --git a/src/images/wavedrom/double-fl-compare.adoc b/src/images/wavedrom/double-fl-compare.edn
index 550bb00..550bb00 100644
--- a/src/images/wavedrom/double-fl-compare.adoc
+++ b/src/images/wavedrom/double-fl-compare.edn
diff --git a/src/images/wavedrom/double-fl-compute.adoc b/src/images/wavedrom/double-fl-compute.edn
index 8f3922d..8f3922d 100644
--- a/src/images/wavedrom/double-fl-compute.adoc
+++ b/src/images/wavedrom/double-fl-compute.edn
diff --git a/src/images/wavedrom/double-fl-convert-mv.adoc b/src/images/wavedrom/double-fl-convert-mv.edn
index 15222d3..15222d3 100644
--- a/src/images/wavedrom/double-fl-convert-mv.adoc
+++ b/src/images/wavedrom/double-fl-convert-mv.edn
diff --git a/src/images/wavedrom/double-ls.adoc b/src/images/wavedrom/double-ls.edn
index 0191a0c..0191a0c 100644
--- a/src/images/wavedrom/double-ls.adoc
+++ b/src/images/wavedrom/double-ls.edn
diff --git a/src/images/wavedrom/env_call-breakpoint.adoc b/src/images/wavedrom/env-call-breakpoint.edn
index 5814faf..5814faf 100644
--- a/src/images/wavedrom/env_call-breakpoint.adoc
+++ b/src/images/wavedrom/env-call-breakpoint.edn
diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc b/src/images/wavedrom/fcvt-sd-ds.edn
index a192ffa..a192ffa 100644
--- a/src/images/wavedrom/fcvt-sd-ds.adoc
+++ b/src/images/wavedrom/fcvt-sd-ds.edn
diff --git a/src/images/wavedrom/float-csr.adoc b/src/images/wavedrom/float-csr.edn
index 56be164..56be164 100644
--- a/src/images/wavedrom/float-csr.adoc
+++ b/src/images/wavedrom/float-csr.edn
diff --git a/src/images/wavedrom/flt-pt-to-int-move.adoc b/src/images/wavedrom/flt-pt-to-int-move.edn
index 861085e..861085e 100644
--- a/src/images/wavedrom/flt-pt-to-int-move.adoc
+++ b/src/images/wavedrom/flt-pt-to-int-move.edn
diff --git a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn
index 830cb2a..830cb2a 100644
--- a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc
+++ b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn
diff --git a/src/images/wavedrom/fnmaddsub.adoc b/src/images/wavedrom/fnmaddsub.adoc
deleted file mode 100644
index ce63985..0000000
--- a/src/images/wavedrom/fnmaddsub.adoc
+++ /dev/null
@@ -1,16 +0,0 @@
-
-//FNMSUP and FNMADD
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']},
-  {bits: 5, name: 'rd',     attr: 'dest'},
-  {bits: 3, name: 'funct3',  attr: 'RM'},
-  {bits: 5, name: 'rs1',    attr: 'src1'},
-  {bits: 5, name: 'rs2',    attr: 'src2'},
-  {bits: 2, name: 'fmt',    attr: 'S'},
-  {bits: 5, name: 'rs3',    attr: 'src3'},
-]}
-....
-
diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc b/src/images/wavedrom/fsjgnjnx-d.edn
index 6247a94..6247a94 100644
--- a/src/images/wavedrom/fsjgnjnx-d.adoc
+++ b/src/images/wavedrom/fsjgnjnx-d.edn
diff --git a/src/images/wavedrom/half-ls.adoc b/src/images/wavedrom/half-ls.edn
index 1d74b69..1d74b69 100644
--- a/src/images/wavedrom/half-ls.adoc
+++ b/src/images/wavedrom/half-ls.edn
diff --git a/src/images/wavedrom/half-pr-flt-pt-class.adoc b/src/images/wavedrom/half-pr-flt-pt-class.edn
index d2af321..d2af321 100644
--- a/src/images/wavedrom/half-pr-flt-pt-class.adoc
+++ b/src/images/wavedrom/half-pr-flt-pt-class.edn
diff --git a/src/images/wavedrom/half-pr-flt-pt-compare.adoc b/src/images/wavedrom/half-pr-flt-pt-compare.edn
index 47e2e9f..47e2e9f 100644
--- a/src/images/wavedrom/half-pr-flt-pt-compare.adoc
+++ b/src/images/wavedrom/half-pr-flt-pt-compare.edn
diff --git a/src/images/wavedrom/half-prec-conv-and-mv.adoc b/src/images/wavedrom/half-prec-conv-and-mv.edn
index 7f05de4..7f05de4 100644
--- a/src/images/wavedrom/half-prec-conv-and-mv.adoc
+++ b/src/images/wavedrom/half-prec-conv-and-mv.edn
diff --git a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn
index f95854d..f95854d 100644
--- a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc
+++ b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn
diff --git a/src/images/wavedrom/half-store.adoc b/src/images/wavedrom/half-store.adoc
deleted file mode 100644
index bdb9058..0000000
--- a/src/images/wavedrom/half-store.adoc
+++ /dev/null
@@ -1,11 +0,0 @@
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: 'STORE-FP'},
-  {bits: 5,  name: 'imm[4:0]',  attr: 'offset'},
-  {bits: 3,  name: 'width',     attr: 'H'},
-  {bits: 5,  name: 'rs1',       attr: 'base'},
-  {bits: 5,  name: 'rs2',       attr: 'src'},
-  {bits: 12, name: 'imm[11:5]', attr: 'offset'},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/hint-nopv_rv32i.adoc b/src/images/wavedrom/hint-nopv_rv32i.adoc
deleted file mode 100644
index b26a6d1..0000000
--- a/src/images/wavedrom/hint-nopv_rv32i.adoc
+++ /dev/null
@@ -1,55 +0,0 @@
-//### RV32I
-//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (2.9)
-//{ADDI, SLTI, SLTIU, XORI, ORI, ANDI} x0, ? ( ${ 6 * 1 << 17} )
-[wavedrom, ,svg]
-....
-{reg: [
-    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
-    {name: 'rd',     bits: 5, attr: 0},
-    {name: 'funct3',  bits: 3, attr: ['ADDI', 'SLTI', 'SLTIU', 'XORI', 'ORI', 'ANDI']},
-    {bits: 17}
-], config: {hspace: width}}
-....
-//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
-    {name: 'rd',     bits: 5, attr: 0},
-    {name: 'funct3',  bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
-    {bits: 10},
-    {name: 'imm?',   bits: 7, attr: [0, 0, 32]}
-], config: {hspace: width}}
-....
-//{LUI, AUIPC} x0, ? ( ${ 2 * (1 << 20) } )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'opcode', bits: 7,  attr: ['AUIPC', 'LUI']},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {bits: 20}
-], config: {hspace: width}}
-....
-//{ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND} x0, ?, ? ( ${ 10 * 1 << 10} )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP',     bits: 7, attr: 0b0110011},
-    {name: 'rd',     bits: 5, attr: 0},
-    {name: 'funct3',  bits: 3, attr: 'ADD SUB SLL SLT SLTU XOR SRL SRA OR AND'.split(' ',
-    {bits: 10},
-    {name: 'funct7',  bits: 7, attr: [0, 0, 0, 0, 0, 0, 32, 32, 0, 0]}
-], config: {hspace: width}}
-....
-
-//RV32I_extra = (
-//  3 * 31 +
-//  31 +
-//  7 * 31 +
-//  3 * 31 +
-//  2 * 31
-//)
-
diff --git a/src/images/wavedrom/hint-nopv_rv64i.adoc b/src/images/wavedrom/hint-nopv_rv64i.adoc
deleted file mode 100644
index ee78cf8..0000000
--- a/src/images/wavedrom/hint-nopv_rv64i.adoc
+++ /dev/null
@@ -1,57 +0,0 @@
-//### RV64I
-//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (4.4)
-//All RV32I NOPs plus:
-//ADDIW x0, ? ( ${ 1 << 17 } )
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP-IMM-32', bits: 7,  attr: 0b0011011},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {name: 'funct3',  bits: 3,  attr: 'ADDIW'},
-    {bits: 17}
-], config: {hspace: width}}
-....
-//Extra bit for the shift ammont:
-//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
-
-[wavedrom, ,svg]
-....
-{reg: [
-    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
-    {name: 'rd',     bits: 5, attr: 0},
-    {name: 'funct3',  bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
-    {bits: 10},
-    {name: 'imm?',   bits: 7, attr: [1, 33, 33]}
-], config: {hspace: width}}
-....
-//{SLLIW, SRLIW, SRAIW} x0, ?( ${ 3 * 1 << 10} )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP-IMM-32', bits: 7,  attr: 0b0011011},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {name: 'funct3',  bits: 3,  attr: ['SLLIW', 'SRLIW', 'SRAIW']},
-    {bits: 10},
-    {name: 'imm?',   bits: 7, attr: [0, 32, 32]}
-], config: {hspace: width}}
-....
-//SLL, SLT, SRA ( ??? )
-//{ADDW, SLLW, SRLW, SUBW, SRAW} x0, ?, ? ( ${ 5 * 1 << 10 } )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP-32', bits: 7,  attr: 0b0111011},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {name: 'funct3',  bits: 3, attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']},
-    {bits: 10},
-    {name: 'funct7',  bits: 7, attr: [0, 0, 32, 0, 32]}
-], config: {hspace: width}}
-....
-
-//RV64I_extra = (
-//  4 * 31 +
-//  5 * 31 +
-//  31
-//`
diff --git a/src/images/wavedrom/immediate_variants.adoc b/src/images/wavedrom/immediate-variants.edn
index 8f9be0c..8f9be0c 100644
--- a/src/images/wavedrom/immediate_variants.adoc
+++ b/src/images/wavedrom/immediate-variants.edn
diff --git a/src/images/wavedrom/immediate.adoc b/src/images/wavedrom/immediate.edn
index 3dec16b..3dec16b 100644
--- a/src/images/wavedrom/immediate.adoc
+++ b/src/images/wavedrom/immediate.edn
diff --git a/src/images/wavedrom/immediate_variants2.adoc b/src/images/wavedrom/immediate_variants2.adoc
deleted file mode 100644
index 05402be..0000000
--- a/src/images/wavedrom/immediate_variants2.adoc
+++ /dev/null
@@ -1,56 +0,0 @@
-## 2.3 Immediate Encoding Variants
-### Figure 2.3
-
-RISC-V base instruction formats showing immediate variants.
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'rd'},
-  {bits: 3,  name: 'func3'},
-  {bits: 5,  name: 'rs1'},
-  {bits: 5,  name: 'rs2'},
-  {bits: 7,  name: 'funct7'}
-], config: {label: {right: 'R-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'rd'},
-  {bits: 3,  name: 'func3'},
-  {bits: 5,  name: 'rs1'},
-  {bits: 12, name: 'imm[11:0]'},
-], config: {label: {right: 'I-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'imm[4:0]'},
-  {bits: 3,  name: 'func3'},
-  {bits: 5,  name: 'rs1'},
-  {bits: 5,  name: 'rs2'},
-  {bits: 7,  name: 'imm[11:5]'}
-], config: {label: {right: 'S-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 1,  name: '[11]'},
-  {bits: 4,  name: 'imm[4:1]'},
-  {bits: 3,  name: 'func3'},
-  {bits: 5,  name: 'rs1'},
-  {bits: 5,  name: 'rs2'},
-  {bits: 6,  name: 'imm[10:5]'},
-  {bits: 1,  name: '[12]'}
-], config: {label: {right: 'B-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'rd'},
-  {bits: 20, name: 'imm[31:12]'}
-], config: {label: {right: 'U-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'rd'},
-  {bits: 8,  name: 'imm[19:12]'},
-  {bits: 1,  name: '[11]'},
-  {bits: 10, name: 'imm[10:1]'},
-  {bits: 1,  name: '[20]'}
-], config: {label: {right: 'J-Type'}}})}
-\ No newline at end of file
diff --git a/src/images/wavedrom/instruction_formats.adoc b/src/images/wavedrom/instruction-formats.edn
index 0741210..0741210 100644
--- a/src/images/wavedrom/instruction_formats.adoc
+++ b/src/images/wavedrom/instruction-formats.edn
diff --git a/src/images/wavedrom/int-comp-lui-aiupc.adoc b/src/images/wavedrom/int-comp-lui-aiupc.edn
index dfb77d1..dfb77d1 100644
--- a/src/images/wavedrom/int-comp-lui-aiupc.adoc
+++ b/src/images/wavedrom/int-comp-lui-aiupc.edn
diff --git a/src/images/wavedrom/int-comp-slli-srli-srai.adoc b/src/images/wavedrom/int-comp-slli-srli-srai.edn
index 3e86d08..3e86d08 100644
--- a/src/images/wavedrom/int-comp-slli-srli-srai.adoc
+++ b/src/images/wavedrom/int-comp-slli-srli-srai.edn
diff --git a/src/images/wavedrom/int_reg-reg.adoc b/src/images/wavedrom/int-reg-reg.edn
index 3fd19f7..3fd19f7 100644
--- a/src/images/wavedrom/int_reg-reg.adoc
+++ b/src/images/wavedrom/int-reg-reg.edn
diff --git a/src/images/wavedrom/integer_computational.adoc b/src/images/wavedrom/integer-computational.edn
index 707f06f..707f06f 100644
--- a/src/images/wavedrom/integer_computational.adoc
+++ b/src/images/wavedrom/integer-computational.edn
diff --git a/src/images/wavedrom/load-reserve-st-conditional.adoc b/src/images/wavedrom/load-reserve-st-conditional.edn
index c1addd3..c1addd3 100644
--- a/src/images/wavedrom/load-reserve-st-conditional.adoc
+++ b/src/images/wavedrom/load-reserve-st-conditional.edn
diff --git a/src/images/wavedrom/load_store.adoc b/src/images/wavedrom/load-store.edn
index ac23d35..ac23d35 100644
--- a/src/images/wavedrom/load_store.adoc
+++ b/src/images/wavedrom/load-store.edn
diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.adoc b/src/images/wavedrom/m-st-ext-for-int-mult.edn
index 77a3507..77a3507 100644
--- a/src/images/wavedrom/m-st-ext-for-int-mult.adoc
+++ b/src/images/wavedrom/m-st-ext-for-int-mult.edn
diff --git a/src/images/wavedrom/mem_order.adoc b/src/images/wavedrom/mem-order.edn
index c7e0ba4..c7e0ba4 100644
--- a/src/images/wavedrom/mem_order.adoc
+++ b/src/images/wavedrom/mem-order.edn
diff --git a/src/images/wavedrom/menvcfgreg.adoc b/src/images/wavedrom/menvcfgreg.edn
index 5ed6fb6..5ed6fb6 100644
--- a/src/images/wavedrom/menvcfgreg.adoc
+++ b/src/images/wavedrom/menvcfgreg.edn
diff --git a/src/images/wavedrom/mm-env-call.adoc b/src/images/wavedrom/mm-env-call.edn
index 703c0be..703c0be 100644
--- a/src/images/wavedrom/mm-env-call.adoc
+++ b/src/images/wavedrom/mm-env-call.edn
diff --git a/src/images/wavedrom/mop-r.adoc b/src/images/wavedrom/mop-r.edn
index 55347e0..55347e0 100644
--- a/src/images/wavedrom/mop-r.adoc
+++ b/src/images/wavedrom/mop-r.edn
diff --git a/src/images/wavedrom/mop-rr.adoc b/src/images/wavedrom/mop-rr.edn
index 879e372..879e372 100644
--- a/src/images/wavedrom/mop-rr.adoc
+++ b/src/images/wavedrom/mop-rr.edn
diff --git a/src/images/wavedrom/mseccfg.adoc b/src/images/wavedrom/mseccfg.edn
index 82242ca..82242ca 100644
--- a/src/images/wavedrom/mseccfg.adoc
+++ b/src/images/wavedrom/mseccfg.edn
diff --git a/src/images/wavedrom/mstatushreg.adoc b/src/images/wavedrom/mstatushreg.edn
index 702ea11..702ea11 100644
--- a/src/images/wavedrom/mstatushreg.adoc
+++ b/src/images/wavedrom/mstatushreg.edn
diff --git a/src/images/wavedrom/mstatusreg-rv321.adoc b/src/images/wavedrom/mstatusreg-rv321.edn
index cc77fc2..cc77fc2 100644
--- a/src/images/wavedrom/mstatusreg-rv321.adoc
+++ b/src/images/wavedrom/mstatusreg-rv321.edn
diff --git a/src/images/wavedrom/mstatusreg.adoc b/src/images/wavedrom/mstatusreg.edn
index db24626..db24626 100644
--- a/src/images/wavedrom/mstatusreg.adoc
+++ b/src/images/wavedrom/mstatusreg.edn
diff --git a/src/images/wavedrom/nop-v.adoc b/src/images/wavedrom/nop-v.adoc
deleted file mode 100644
index 0c990e4..0000000
--- a/src/images/wavedrom/nop-v.adoc
+++ /dev/null
@@ -1,29 +0,0 @@
-//# NOP-V
-
-The RISC-V [User-Level ISA Specification](https://riscv.org/specifications/) defines NOP instruction as follows:
-
-* The NOP instruction does not change any user-visible state, except for advancing the pc.
-* NOP is encoded as \`ADDI x0, x0, 0\`.
-
-[wavedrom, , ]
-----
-{reg:[
-    {name: 'opcode', bits: 7,  attr: 0b0010011},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {name: 'funct3',  bits: 3,  attr: 0},
-    {name: 'rs1',    bits: 5,  attr: 0},
-    {name: 'imm',    bits: 12, attr: 0}
-], config: {hspace: width}}
-----
-
-
-NOTE: NOPs can be used to align code segments to microarchitecturally significant address boundaries, or to leave space for inline code modifications. Although **there are many possible ways** to encode a NOP, we define a canonical NOP encoding to allow microarchitectural optimizations as well as for more readable disassembly output.
-
-How many other possible ways to encode NOP?
-----
-rd = 0
-----
-
-Any Integer Computational instruction writing into \`x0\` is NOP.
-
-`
diff --git a/src/images/wavedrom/nop.adoc b/src/images/wavedrom/nop.edn
index b566909..b566909 100644
--- a/src/images/wavedrom/nop.adoc
+++ b/src/images/wavedrom/nop.edn
diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc b/src/images/wavedrom/quad-cnvrt-intch-xqqx.edn
index a388033..a388033 100644
--- a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc
+++ b/src/images/wavedrom/quad-cnvrt-intch-xqqx.edn
diff --git a/src/images/wavedrom/quad-cnvrt-mv.adoc b/src/images/wavedrom/quad-cnvrt-mv.edn
index 840118d..840118d 100644
--- a/src/images/wavedrom/quad-cnvrt-mv.adoc
+++ b/src/images/wavedrom/quad-cnvrt-mv.edn
diff --git a/src/images/wavedrom/quad-cnvt-interchange.adoc b/src/images/wavedrom/quad-cnvt-interchange.edn
index 54adc1f..54adc1f 100644
--- a/src/images/wavedrom/quad-cnvt-interchange.adoc
+++ b/src/images/wavedrom/quad-cnvt-interchange.edn
diff --git a/src/images/wavedrom/quad-compute.adoc b/src/images/wavedrom/quad-compute.edn
index 2451ac9..2451ac9 100644
--- a/src/images/wavedrom/quad-compute.adoc
+++ b/src/images/wavedrom/quad-compute.edn
diff --git a/src/images/wavedrom/quad-float-clssfy.adoc b/src/images/wavedrom/quad-float-clssfy.edn
index 325239e..325239e 100644
--- a/src/images/wavedrom/quad-float-clssfy.adoc
+++ b/src/images/wavedrom/quad-float-clssfy.edn
diff --git a/src/images/wavedrom/quad-float-compare.adoc b/src/images/wavedrom/quad-float-compare.edn
index 86e8f83..86e8f83 100644
--- a/src/images/wavedrom/quad-float-compare.adoc
+++ b/src/images/wavedrom/quad-float-compare.edn
diff --git a/src/images/wavedrom/quad-ls.adoc b/src/images/wavedrom/quad-ls.edn
index d855534..d855534 100644
--- a/src/images/wavedrom/quad-ls.adoc
+++ b/src/images/wavedrom/quad-ls.edn
diff --git a/src/images/wavedrom/reg-based-ldnstr.adoc b/src/images/wavedrom/reg-based-ldnstr.edn
index 031ea1a..031ea1a 100644
--- a/src/images/wavedrom/reg-based-ldnstr.adoc
+++ b/src/images/wavedrom/reg-based-ldnstr.edn
diff --git a/src/images/wavedrom/rv64_lui-auipc.adoc b/src/images/wavedrom/rv64-lui-auipc.edn
index 5850133..5850133 100644
--- a/src/images/wavedrom/rv64_lui-auipc.adoc
+++ b/src/images/wavedrom/rv64-lui-auipc.edn
diff --git a/src/images/wavedrom/rv64i-base-int.adoc b/src/images/wavedrom/rv64i-base-int.edn
index 4ff3b83..4ff3b83 100644
--- a/src/images/wavedrom/rv64i-base-int.adoc
+++ b/src/images/wavedrom/rv64i-base-int.edn
diff --git a/src/images/wavedrom/rv64i_int-reg-reg.adoc b/src/images/wavedrom/rv64i-int-reg-reg.edn
index 6d29ec7..6d29ec7 100644
--- a/src/images/wavedrom/rv64i_int-reg-reg.adoc
+++ b/src/images/wavedrom/rv64i-int-reg-reg.edn
diff --git a/src/images/wavedrom/rv64i-slli.adoc b/src/images/wavedrom/rv64i-slli.edn
index b261564..b261564 100644
--- a/src/images/wavedrom/rv64i-slli.adoc
+++ b/src/images/wavedrom/rv64i-slli.edn
diff --git a/src/images/wavedrom/rv64i-slliw.adoc b/src/images/wavedrom/rv64i-slliw.edn
index 0ca01ba..0ca01ba 100644
--- a/src/images/wavedrom/rv64i-slliw.adoc
+++ b/src/images/wavedrom/rv64i-slliw.edn
diff --git a/src/images/wavedrom/sp-load-store-2.adoc b/src/images/wavedrom/sp-load-store-2.edn
index a95b861..a95b861 100644
--- a/src/images/wavedrom/sp-load-store-2.adoc
+++ b/src/images/wavedrom/sp-load-store-2.edn
diff --git a/src/images/wavedrom/sp-load-store.adoc b/src/images/wavedrom/sp-load-store.edn
index 6b1fe49..6b1fe49 100644
--- a/src/images/wavedrom/sp-load-store.adoc
+++ b/src/images/wavedrom/sp-load-store.edn
diff --git a/src/images/wavedrom/spfloat-classify.adoc b/src/images/wavedrom/spfloat-classify.edn
index 52ec8bc..52ec8bc 100644
--- a/src/images/wavedrom/spfloat-classify.adoc
+++ b/src/images/wavedrom/spfloat-classify.edn
diff --git a/src/images/wavedrom/spfloat-cn-cmp.adoc b/src/images/wavedrom/spfloat-cn-cmp.edn
index 0e5db87..0e5db87 100644
--- a/src/images/wavedrom/spfloat-cn-cmp.adoc
+++ b/src/images/wavedrom/spfloat-cn-cmp.edn
diff --git a/src/images/wavedrom/spfloat-comp.adoc b/src/images/wavedrom/spfloat-comp.edn
index 05012a7..05012a7 100644
--- a/src/images/wavedrom/spfloat-comp.adoc
+++ b/src/images/wavedrom/spfloat-comp.edn
diff --git a/src/images/wavedrom/spfloat-mv.adoc b/src/images/wavedrom/spfloat-mv.edn
index 47a63ee..47a63ee 100644
--- a/src/images/wavedrom/spfloat-mv.adoc
+++ b/src/images/wavedrom/spfloat-mv.edn
diff --git a/src/images/wavedrom/spfloat-sign-inj.adoc b/src/images/wavedrom/spfloat-sign-inj.edn
index 8c81976..8c81976 100644
--- a/src/images/wavedrom/spfloat-sign-inj.adoc
+++ b/src/images/wavedrom/spfloat-sign-inj.edn
diff --git a/src/images/wavedrom/spfloat-zfh.adoc b/src/images/wavedrom/spfloat-zfh.edn
index 4221c2d..4221c2d 100644
--- a/src/images/wavedrom/spfloat-zfh.adoc
+++ b/src/images/wavedrom/spfloat-zfh.edn
diff --git a/src/images/wavedrom/spfloat.adoc b/src/images/wavedrom/spfloat.edn
index 97679bd..97679bd 100644
--- a/src/images/wavedrom/spfloat.adoc
+++ b/src/images/wavedrom/spfloat.edn
diff --git a/src/images/wavedrom/spfloat2-zfh.adoc b/src/images/wavedrom/spfloat2-zfh.edn
index 64d3fa7..64d3fa7 100644
--- a/src/images/wavedrom/spfloat2-zfh.adoc
+++ b/src/images/wavedrom/spfloat2-zfh.edn
diff --git a/src/images/wavedrom/spfloat2.adoc b/src/images/wavedrom/spfloat2.edn
index cee5bdc..cee5bdc 100644
--- a/src/images/wavedrom/spfloat2.adoc
+++ b/src/images/wavedrom/spfloat2.edn
diff --git a/src/images/wavedrom/sploat2.adoc b/src/images/wavedrom/sploat2.adoc
deleted file mode 100644
index e69de29..0000000
--- a/src/images/wavedrom/sploat2.adoc
+++ /dev/null
diff --git a/src/images/wavedrom/trap-return.adoc b/src/images/wavedrom/trap-return.edn
index 7467ad6..7467ad6 100644
--- a/src/images/wavedrom/trap-return.adoc
+++ b/src/images/wavedrom/trap-return.edn
diff --git a/src/images/wavedrom/v-inst-table.adoc b/src/images/wavedrom/v-inst-table.edn
index 0c02220..0c02220 100644
--- a/src/images/wavedrom/v-inst-table.adoc
+++ b/src/images/wavedrom/v-inst-table.edn
diff --git a/src/images/wavedrom/valu-format.adoc b/src/images/wavedrom/valu-format.edn
index 95732e7..95732e7 100644
--- a/src/images/wavedrom/valu-format.adoc
+++ b/src/images/wavedrom/valu-format.edn
diff --git a/src/images/wavedrom/vcfg-format.adoc b/src/images/wavedrom/vcfg-format.edn
index 0219e6b..0219e6b 100644
--- a/src/images/wavedrom/vcfg-format.adoc
+++ b/src/images/wavedrom/vcfg-format.edn
diff --git a/src/images/wavedrom/vfrec7.adoc b/src/images/wavedrom/vfrec7.edn
index d33f44e..d33f44e 100644
--- a/src/images/wavedrom/vfrec7.adoc
+++ b/src/images/wavedrom/vfrec7.edn
diff --git a/src/images/wavedrom/vfrsqrt7.adoc b/src/images/wavedrom/vfrsqrt7.edn
index 8ebc621..8ebc621 100644
--- a/src/images/wavedrom/vfrsqrt7.adoc
+++ b/src/images/wavedrom/vfrsqrt7.edn
diff --git a/src/images/wavedrom/vmem-format.adoc b/src/images/wavedrom/vmem-format.edn
index 58cc6bf..58cc6bf 100644
--- a/src/images/wavedrom/vmem-format.adoc
+++ b/src/images/wavedrom/vmem-format.edn
diff --git a/src/images/wavedrom/vtype-format.adoc b/src/images/wavedrom/vtype-format.edn
index 9e6ab34..9e6ab34 100644
--- a/src/images/wavedrom/vtype-format.adoc
+++ b/src/images/wavedrom/vtype-format.edn
diff --git a/src/images/wavedrom/wfi.adoc b/src/images/wavedrom/wfi.edn
index 870e2a1..870e2a1 100644
--- a/src/images/wavedrom/wfi.adoc
+++ b/src/images/wavedrom/wfi.edn
diff --git a/src/images/wavedrom/zifencei-fetch.adoc b/src/images/wavedrom/zifencei-fetch.adoc
deleted file mode 100644
index 660c134..0000000
--- a/src/images/wavedrom/zifencei-fetch.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: 'MISC-MEM'},
-  {bits: 5,  name: 'rd',    attr: 0},
-  {bits: 3,  name: 'funct3', attr: 'FENCE.I'},
-  {bits: 5,  name: 'rs1',   attr: 0},
-  {bits: 12, name: 'func12', attr: 0},
-]}
-....
diff --git a/src/images/wavedrom/zifencei-ff.adoc b/src/images/wavedrom/zifencei-ff.edn
index 24cf87b..24cf87b 100644
--- a/src/images/wavedrom/zifencei-ff.adoc
+++ b/src/images/wavedrom/zifencei-ff.edn
diff --git a/src/images/wavedrom/zihintpause-hint.adoc b/src/images/wavedrom/zihintpause-hint.edn
index 34c73a7..34c73a7 100644
--- a/src/images/wavedrom/zihintpause-hint.adoc
+++ b/src/images/wavedrom/zihintpause-hint.edn
diff --git a/src/intro.adoc b/src/intro.adoc
index 6fc871b..6390f60 100644
--- a/src/intro.adoc
+++ b/src/intro.adoc
@@ -33,7 +33,7 @@ efficiency.
 * An ISA that simplifies experiments with new privileged architecture
 designs.
 
-[TIP]
+[NOTE]
 ====
 Commentary on our design decisions is formatted as in this paragraph.
 This non-normative text can be skipped if the reader is only interested
@@ -64,7 +64,7 @@ volume provides the design of the first ("classic") privileged
 architecture. The manuals use IEC 80000-13:2008 conventions, with a byte
 of 8 bits.
 
-[TIP]
+[NOTE]
 ====
 In the unprivileged ISA design, we tried to remove any dependence on
 particular microarchitectural features, such as cache line size, or on
@@ -144,7 +144,7 @@ environments for guest operating systems.
 harts on an underlying x86 system, and which can provide either a
 user-level or a supervisor-level execution environment.
 
-[TIP]
+[NOTE]
 ====
 A bare hardware platform can be considered to define an EEI, where the
 accessible harts, memory, and other devices populate the environment,
@@ -176,7 +176,7 @@ constitute forward progress:
 * Any other event defined by an extension to constitute forward
 progress.
 
-[TIP]
+[NOTE]
 ====
 The term hart was introduced in the work on Lithe cite:[lithe-pan-hotpar09] and cite:[lithe-pan-pldi10] to provide a term to
 represent an abstract execution resource as opposed to a software thread
@@ -230,7 +230,7 @@ base integer instruction set supporting a flat 128-bit address space
 representation for signed integer values.
 
 
-[TIP]
+[NOTE]
 ====
 Although 64-bit address spaces are a requirement for larger systems, we
 believe 32-bit address spaces will remain adequate for many embedded and
@@ -382,7 +382,7 @@ harts may be entirely the same, or entirely different, or may be partly
 different but sharing some subset of resources, mapped into the same or
 different address ranges.
 
-[TIP]
+[NOTE]
 ====
 For a purely "bare metal" environment, all harts may see an identical
 address space, accessed entirely by physical addresses. However, when
@@ -552,7 +552,7 @@ instructions. These instructions are considered to be of minimal length:
 bits. The encoding with bits [ILEN-1:0] all ones is also illegal; this
 instruction is considered to be ILEN bits long.
 
-[TIP]
+[NOTE]
 ====
 We consider it a feature that any length of instruction containing all
 zero bits is not legal, as this quickly traps erroneous jumps into
@@ -587,7 +587,7 @@ instruction specification.
 (((bi-endian)))
 (((endian, bi-)))
 
-[TIP]
+[NOTE]
 ====
 We originally chose little-endian byte ordering for the RISC-V memory
 system because little-endian systems are currently dominant commercially
diff --git a/src/m-st-ext.adoc b/src/m-st-ext.adoc
index fc08be2..1c036cb 100644
--- a/src/m-st-ext.adoc
+++ b/src/m-st-ext.adoc
@@ -5,7 +5,7 @@ This chapter describes the standard integer multiplication and division
 instruction extension, which is named "M" and contains instructions
 that multiply or divide values held in two integer registers.
 
-[TIP]
+[NOTE]
 ====
 We separate integer multiply and divide out from the base to simplify
 low-end implementations, or for applications where integer multiply and
@@ -15,7 +15,7 @@ accelerators.
 
 === Multiplication Operations
 
-include::images/wavedrom/m-st-ext-for-int-mult.adoc[]
+include::images/wavedrom/m-st-ext-for-int-mult.edn[]
 [[m-st-ext-for-int-mult]]
 //.Multiplication operation instructions
 (((MUL, MULH)))
@@ -52,7 +52,7 @@ to shift both arguments left by 32 bits, then use MULH[[S]U].
 
 === Division Operations
 
-include::images/wavedrom/division-op.adoc[]
+include::images/wavedrom/division-op.edn[]
 [[division-op]]
 //.Division operation instructions
 (((MUL, DIV)))
@@ -113,7 +113,7 @@ latexmath:[$-1$] |latexmath:[$2^{L}-1$] +
 //|Overflow (signed only) |latexmath:[$-2^{L-1}$] |latexmath:[$-1$] |– |– |latexmath:[$-2^{L-1}$] |0
 //|===
 
-[TIP]
+[NOTE]
 ====
 We considered raising exceptions on integer divide by zero, with these
 exceptions causing a trap in most execution environments. However, this
diff --git a/src/machine.adoc b/src/machine.adoc
index a81f7bb..0d5ab4f 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -368,18 +368,18 @@ S-level ISA.
 
 [[mstatusreg-rv32]]
 .Machine-mode status (`mstatus`) register for RV32
-include::images/wavedrom/mstatusreg-rv321.adoc[]
+include::images/wavedrom/mstatusreg-rv321.edn[]
 
 [[mstatusreg]]
 .Machine-mode status (`mstatus`) register for RV64
-include::images/wavedrom/mstatusreg.adoc[]
+include::images/wavedrom/mstatusreg.edn[]
 
 For RV32 only, `mstatush` is a 32-bit read/write register formatted as
 shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.
 
 [[mstatushreg]]
 .Additional machine-mode status (`mstatush`) register  for RV32.
-include::images/wavedrom/mstatushreg.adoc[]
+include::images/wavedrom/mstatushreg.edn[]
 
 [[privstack]]
 ===== Privilege and Global Interrupt-Enable Stack in `mstatus` register
@@ -1575,9 +1575,9 @@ counters, the counters can be directly exposed to lower privilege modes.
 The `cycle`, `instret`, and `hpmcountern` CSRs are read-only shadows of
 `mcycle`, `minstret`, and `mhpmcounter n`, respectively. The `time` CSR
 is a read-only shadow of the memory-mapped `mtime` register.
-Analogously, on RV32I the `cycleh`, `instreth` and `hpmcounternh` CSRs
+Analogously, when XLEN=32, the `cycleh`, `instreth` and `hpmcounternh` CSRs
 are read-only shadows of `mcycleh`, `minstreth` and `mhpmcounternh`,
-respectively. On RV32I the `timeh` CSR is a read-only shadow of the
+respectively. When XLEN=32, the `timeh` CSR is a read-only shadow of the
 upper 32 bits of the memory-mapped `mtime` register, while `time`
 shadows only the lower 32 bits of `mtime`.
 
@@ -2100,7 +2100,7 @@ privileged than M.
 
 [[menvcfgreg]]
 .Machine environment configuration (`menvcfg`) register.
-include::images/wavedrom/menvcfgreg.adoc[]
+include::images/wavedrom/menvcfgreg.edn[]
 
 
 If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
@@ -2227,7 +2227,7 @@ shown in <<mseccfg>>, that controls security features.
 
 [[mseccfg]]
 .Machine security configuration (`mseccfg`) register.
-include::images/wavedrom/mseccfg.adoc[]
+include::images/wavedrom/mseccfg.edn[]
 
 The definitions of the SSEED and USEED fields will be furnished by the
 forthcoming entropy-source extension, Zkr. Their allocations within
@@ -2336,13 +2336,19 @@ For RV64, naturally aligned 64-bit memory accesses to the `mtime` and
 ....
 
 
+The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.
+When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the
+memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of
+`mtime`.
+When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh`
+eventually, but not necessarily immediately.
 
 
 === Machine-Mode Privileged Instructions
 
 ==== Environment Call and Breakpoint
 
-include::images/wavedrom/mm-env-call.adoc[]
+include::images/wavedrom/mm-env-call.edn[]
 
 The ECALL instruction is used to make a request to the supporting
 execution environment. When executed in U-mode, S-mode, or M-mode, it
@@ -2382,7 +2388,7 @@ not increment the `minstret` CSR.
 Instructions to return from trap are encoded under the PRIV minor
 opcode.
 
-include::images/wavedrom/trap-return.adoc[]
+include::images/wavedrom/trap-return.edn[]
 
 To return after handling a trap, there are separate trap return
 instructions per privilege level, MRET and SRET. MRET is always
@@ -2419,7 +2425,7 @@ privileged modes, and optionally available to U-mode. This instruction
 may raise an illegal-instruction exception when TW=1 in `mstatus`, as
 described in <<virt-control>>.
 
-include::images/wavedrom/wfi.adoc[]
+include::images/wavedrom/wfi.edn[]
 
 If an enabled interrupt is present or later becomes present while the
 hart is stalled, the interrupt trap will be taken on the following
@@ -2513,7 +2519,9 @@ the platform mandates a different reset value for some PMP registers’ A
 and L fields. If the hypervisor extension is implemented, the
 `hgatp`.MODE and `vsatp`.MODE fields are reset to 0. If the Smrnmi
 extension is implemented, the `mnstatus`.NMIE field is reset to 0. No
- *WARL* field contains an illegal value. All other hart state is UNSPECIFIED.
+ *WARL* field contains an illegal value. If the Zicfilp extension is
+implemented, the `mseccfg`.MLPE field is reset to 0. All other hart
+state is UNSPECIFIED.
 
 The `mcause` values after reset have implementation-specific
 interpretation, but the value 0 should be returned on implementations
diff --git a/src/mm-formal.adoc b/src/mm-formal.adoc
index 9f2c942..58e35ee 100644
--- a/src/mm-formal.adoc
+++ b/src/mm-formal.adoc
@@ -597,7 +597,7 @@ continue executing.
 Transitions specific to `sc` instructions:
 
 [disc]
-* <<early_sc_fail, Early sc fail>>: This causes the `sc` to fail, either a spontaneous fail or becauset is not paired with a program-order-previous `lr`.
+* <<early_sc_fail, Early sc fail>>: This causes the `sc` to fail, either a spontaneous fail or because it is not paired with a program-order-previous `lr`.
 
 * <<paired_sc, Paired sc>>: This transition indicates the `sc` is paired with an `lr` and might
 succeed.
@@ -1049,10 +1049,10 @@ load is acquire-RCsc.
 ===== Satisfy memory load operation from memory
 
 For an instruction instance latexmath:[$i$] of a non-AMO load
-instruction or an AMO instruction in the context of the <<do_amo, Saitsfy, commit and propagate operations of an AMO>> transition,
+instruction or an AMO instruction in the context of the <<do_amo, Satisfy, commit and propagate operations of an AMO>> transition,
 any memory load operation latexmath:[$mlo$] in
 latexmath:[$i.\textit{mem\_loads}$] that has unsatisfied slices, can be
-satisfied from memory if all the conditions of <sat_by_forwarding, Saitsfy memory load operation by forwarding from unpropagated stores>> are satisfied. Action:
+satisfied from memory if all the conditions of <sat_by_forwarding, Satisfy memory load operation by forwarding from unpropagated stores>> are satisfied. Action:
 let latexmath:[$msoss$] be the memory store operation slices from memory
 covering the unsatisfied slices of latexmath:[$mlo$], and apply the
 action of <<do_amo, Satisfy memory operation by forwarding from unpropagates stores>>.
@@ -1259,7 +1259,7 @@ Plain(_store_continuation(false)_).
 For efficiency, the `rmem` tool allows this transition only when it is
 not possible to take the <<commit_sc, Commit and propagate store operation of an sc>> transition. This does not affect the set of
 allowed final states, but when explored interactively, if the `sc`
-should fail one should use the <<early_sc_fail, Eaarly sc fail>> transition instead of waiting for this transition.
+should fail one should use the <<early_sc_fail, Early sc fail>> transition instead of waiting for this transition.
 ====
 [[complete_stores]]
 ===== Complete store operations
diff --git a/src/naming.adoc b/src/naming.adoc
index 6ddb92a..09c728b 100644
--- a/src/naming.adoc
+++ b/src/naming.adoc
@@ -115,7 +115,7 @@ with the letters "Sh".
 If multiple hypervisor-level extensions are listed, they should be ordered
 alphabetically.
 
-NOTE: Many augmentations to the hypervisor-level archtecture are more
+NOTE: Many augmentations to the hypervisor-level architecture are more
 naturally defined as supervisor-level extensions, following the scheme
 described in the previous section.
 The "Sh" prefix is used by the few hypervisor-level extensions that have no
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc
index 76beaa7..6c07f76 100644
--- a/src/priv-preface.adoc
+++ b/src/priv-preface.adoc
@@ -95,10 +95,10 @@ implemented.
 * Defined hardware error and software check exception codes.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
-* Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
+* Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension.
 * Relaxed behavior of some HINTs when MXLEN > XLEN.
 
-Finally, the following clarifications and document improvments have been made
+Finally, the following clarifications and document improvements have been made
 since the last document release:
 
 * Transliterated the document from LaTeX into AsciiDoc.
@@ -118,6 +118,7 @@ be set to a nonzero value but sometimes not.
 * Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
 * Clarified that timer and count-overflow interrupts' arrival in
   interrupt-pending registers is not immediate.
+* Clarified that MXR affects only explicit memory accesses.
 
 [.big]*_Preface to Version 20211203_*
 
diff --git a/src/q-st-ext.adoc b/src/q-st-ext.adoc
index 3940ea7..1cb969f 100644
--- a/src/q-st-ext.adoc
+++ b/src/q-st-ext.adoc
@@ -17,7 +17,7 @@ value.
 New 128-bit variants of LOAD-FP and STORE-FP instructions are added,
 encoded with a new value for the funct3 width field.
 
-include::images/wavedrom/quad-ls.adoc[]
+include::images/wavedrom/quad-ls.edn[]
 [[quad-ls]]
 //.Quad-precision load and store
 
@@ -47,7 +47,7 @@ The quad-precision floating-point computational instructions are defined
 analogously to their double-precision counterparts, but operate on
 quad-precision operands and produce quad-precision results.
 
-include::images/wavedrom/quad-compute.adoc[]
+include::images/wavedrom/quad-compute.edn[]
 [[quad-compute]]
 //.Quad-precision computational
 
@@ -64,7 +64,7 @@ FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or
 from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only
 instructions. Note FCVT.Q.L[U] always produces an exact result and is unaffected by rounding mode.
 
-include::images/wavedrom/quad-cnvrt-mv.adoc[]
+include::images/wavedrom/quad-cnvrt-mv.edn[]
 [[quad-cnvrt-mv]]
 //.Quad-precision convert and move
 
@@ -76,7 +76,7 @@ single-precision floating-point number, or vice-versa, respectively.
 FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to
 a double-precision floating-point number, or vice-versa, respectively.
 
-include::images/wavedrom/quad-cnvt-interchange.adoc[]
+include::images/wavedrom/quad-cnvt-interchange.edn[]
 [[quad-convrt-interchange]]
 //.Quad-precision convert and move interchangeably
 
@@ -84,7 +84,7 @@ Floating-point to floating-point sign-injection instructions, FSGNJ.Q,
 FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision
 sign-injection instruction.
 
-include::images/wavedrom/quad-cnvrt-intch-xqqx.adoc[]
+include::images/wavedrom/quad-cnvrt-intch-xqqx.edn[]
 [[quad-cnvrt-intch-xqqx]]
 //.Quad-precision convert and move interchangeably XQ-QX
 
@@ -103,7 +103,7 @@ The quad-precision floating-point compare instructions are defined
 analogously to their double-precision counterparts, but operate on
 quad-precision operands.
 
-include::images/wavedrom/quad-float-compare.adoc[]
+include::images/wavedrom/quad-float-compare.edn[]
 [[quad-float-compare]]
 //.Quad-precision floatinf-point compare
 
@@ -113,7 +113,7 @@ The quad-precision floating-point classify instruction, FCLASS.Q, is
 defined analogously to its double-precision counterpart, but operates on
 quad-precision operands.
 
-include::images/wavedrom/quad-float-clssfy.adoc[]
+include::images/wavedrom/quad-float-clssfy.edn[]
 [[quad-float-clssfy]]
 //.Quad-precision floating point classify
 
diff --git a/src/riscv-unprivileged.adoc b/src/riscv-unprivileged.adoc
index a755403..b71d372 100644
--- a/src/riscv-unprivileged.adoc
+++ b/src/riscv-unprivileged.adoc
@@ -27,15 +27,16 @@ include::../docs-resources/global-config.adoc[]
 :example-caption: Example
 :listing-caption: Listing
 :sectnums:
+:sectnumlevels: 5
 :toc: left
-:toclevels: 5
+:toclevels: 5 
 :source-highlighter: pygments
 ifdef::backend-pdf[]
 :source-highlighter: rouge
 endif::[]
 :table-caption: Table
 :figure-caption: Figure
-:xrefstyle: short
+:xrefstyle: short 
 :chapter-refsig: Chapter
 :section-refsig: Section
 :appendix-refsig: Appendix
diff --git a/src/rv128.adoc b/src/rv128.adoc
index 62af109..9098dcb 100644
--- a/src/rv128.adoc
+++ b/src/rv128.adoc
@@ -11,7 +11,7 @@ flat 128-bit address space. The variant is a straightforward
 extrapolation of the existing RV32I and RV64I designs.
 (((RV128, design)))
 
-[TIP]
+[NOTE]
 ====
 The primary reason to extend integer register width is to support larger
 address spaces. It is not clear when a flat address space larger than 64
diff --git a/src/rv32.adoc b/src/rv32.adoc
index 9714df4..7de4ef0 100644
--- a/src/rv32.adoc
+++ b/src/rv32.adoc
@@ -3,7 +3,7 @@
 
 This chapter describes the RV32I base integer instruction set.
 
-[TIP]
+[NOTE]
 ====
 RV32I was designed to be sufficient to form a compiler target and to
 support modern operating system environments. The ISA was also designed
@@ -174,7 +174,7 @@ bits in the instruction and have been allocated to reduce hardware
 complexity. In particular, the sign bit for all immediates is always in
 bit 31 of the instruction to speed sign-extension circuitry.
 
-include::images/wavedrom/instruction_formats.adoc[]
+include::images/wavedrom/instruction-formats.edn[]
 [[base_instr,Base instruction formats]]
 RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction's immediate field as is usually done.
 
@@ -201,7 +201,7 @@ to keep the ISA as simple as possible.
 There are a further two variants of the instruction formats (B/J) based
 on the handling of immediates, as shown in <<baseinstformatsimm>>.
 
-include::images/wavedrom/immediate_variants.adoc[]
+include::images/wavedrom/immediate-variants.edn[]
 [[baseinstformatsimm,Base instruction formats immediate variants.]]
 //.RISC-V base instruction formats showing immediate variants.
 
@@ -224,7 +224,7 @@ each of the base instruction formats, and is labeled to show which
 instruction bit (inst[_y_]) produces each bit of the immediate value.
 [[immtypes, Immediate types]]
 .Types of immediate produced by RISC-V instructions. 
-include::images/wavedrom/immediate.adoc[]
+include::images/wavedrom/immediate.edn[]
 
 The fields are labeled with the instruction bits used to construct their value.  Sign extensions always uses inst[31].
 
@@ -258,7 +258,7 @@ destination is register _rd_ for both register-immediate and
 register-register instructions. No integer computational instructions
 cause arithmetic exceptions.
 
-[TIP]
+[NOTE]
 ====
 We did not include special instruction-set support for overflow checks
 on integer arithmetic operations in the base instruction set, as many
@@ -291,7 +291,7 @@ comparing the results of ADD and ADDW on the operands.
 
 ==== Integer Register-Immediate Instructions
 
-include::images/wavedrom/integer_computational.adoc[]
+include::images/wavedrom/integer-computational.edn[]
 //.Integer Computational Instructions
 
 ADDI adds the sign-extended 12-bit immediate to register _rs1_.
@@ -312,7 +312,7 @@ XOR on register _rs1_ and the sign-extended 12-bit immediate and place
 the result in _rd_. Note, XORI _rd, rs1, -1_ performs a bitwise logical
 inversion of register _rs1_ (assembler pseudoinstruction NOT _rd, rs_).
 
-include::images/wavedrom/int-comp-slli-srli-srai.adoc[]
+include::images/wavedrom/int-comp-slli-srli-srai.edn[]
 [[int-comp-slli-srli-srai]]
 //.Integer register-immediate, SLLI, SRLI, SRAI
 
@@ -324,7 +324,7 @@ shifted into the lower bits); SRLI is a logical right shift (zeros are
 shifted into the upper bits); and SRAI is an arithmetic right shift (the
 original sign bit is copied into the vacated upper bits).
 
-include::images/wavedrom/int-comp-lui-aiupc.adoc[]
+include::images/wavedrom/int-comp-lui-aiupc.edn[]
 [[int-comp-lui-aiupc]]
 //.Integer register-immediate, U-immediate
 
@@ -364,7 +364,7 @@ the _rs1_ and _rs2_ registers as source operands and write the result
 into register _rd_. The _funct7_ and _funct3_ fields select the type of
 operation.
 
-include::images/wavedrom/int_reg-reg.adoc[]
+include::images/wavedrom/int-reg-reg.edn[]
 [[int-reg-reg]]
 //.Integer register-register
 
@@ -383,7 +383,7 @@ the lower 5 bits of register _rs2_.
 
 ==== NOP Instruction
 
-include::images/wavedrom/nop.adoc[]
+include::images/wavedrom/nop.edn[]
 [[nop]]
 //.NOP instructions
 
@@ -444,7 +444,7 @@ than the regular link register.
 Plain unconditional jumps (assembler pseudoinstruction J) are encoded as
 a JAL with _rd_=`x0`.
 
-include::images/wavedrom/ct-unconditional.adoc[]
+include::images/wavedrom/ct-unconditional.edn[]
 [[ct-unconditional]]
 //.The unconditional-jump instruction, JAL
 
@@ -456,7 +456,13 @@ instruction following the jump (`pc`+4) is written to register _rd_.
 Register `x0` can be used as the destination if the result is not
 required.
 
-include::images/wavedrom/ct-unconditional-2.adoc[]
+Plain unconditional indirect jumps (assembler pseudoinstruction JR) are
+encoded as a JALR with _rd_=`x0`.
+Procedure returns in the standard calling convention (assembler
+pseudoinstruction RET) are encoded as a JALR with _rd_=`x0`, _rs1_=`x1`, and
+_imm_=0.
+
+include::images/wavedrom/ct-unconditional-2.edn[]
 [[ct-unconditional-2]]
 //.The indirect unconditional-jump instruction, JALR
 
@@ -550,7 +556,7 @@ is sign-extended and added to the address of the branch instruction to
 give the target address. The conditional branch range is
 &#177;4 KiB.
 
-include::images/wavedrom/ct-conditional.adoc[]
+include::images/wavedrom/ct-conditional.edn[]
 [[ct-conditional]]
 //.Conditional branches
 
@@ -581,7 +587,7 @@ a conditional branch instruction with an always-true condition. RISC-V
 jumps are also PC-relative and support a much wider offset range than
 branches, and will not pollute conditional-branch prediction tables.
 
-[TIP]
+[NOTE]
 ====
 The conditional branches were designed to include arithmetic comparison
 operations between two registers (as also done in PA-RISC, Xtensa, and
@@ -666,7 +672,7 @@ even though the load value is discarded.
 The EEI will define whether the memory system is little-endian or
 big-endian. In RISC-V, endianness is byte-address invariant.
 
-[TIP]
+[NOTE]
 ====
 In a system for which endianness is byte-address invariant, the
 following property holds: if a byte is stored to memory at some address
@@ -686,7 +692,7 @@ significance. Loads similarly transfer the contents of the greater
 memory byte addresses to the less-significant register bytes.
 ====
 
-include::images/wavedrom/load_store.adoc[]
+include::images/wavedrom/load-store.edn[]
 [[load-store,load and store]]
 //.Load and store instructions
 
@@ -731,7 +737,7 @@ by address misalignment result in a contained trap (allowing software
 running inside the execution environment to handle the trap) or a fatal
 trap (terminating execution).
 
-[TIP]
+[NOTE]
 ====
 Misaligned accesses are occasionally required when porting legacy code,
 and help performance on applications when using any form of packed-SIMD
@@ -775,7 +781,7 @@ are aligned.
 [[fence]]
 === Memory Ordering Instructions
 
-include::images/wavedrom/mem_order.adoc[]
+include::images/wavedrom/mem-order.edn[]
 [[mem-order]]
 //.Memory ordering instructions
 
@@ -853,7 +859,7 @@ Base implementations shall treat all such reserved configurations as
 normal fences with _fm_=0000, and standard software shall use only
 non-reserved configurations.
 
-[TIP]
+[NOTE]
 ====
 We chose a relaxed memory model to allow high performance from simple
 machine implementations and from likely future coprocessor or
@@ -865,6 +871,7 @@ ignore the _predecessor_ and _successor_ fields and always execute a
 conservative fence on all operations.
 ====
 
+[[ecall-ebreak]]
 === Environment Call and Breakpoints
 `SYSTEM` instructions are used to access system functionality that might
 require privileged access and are encoded using the I-type instruction
@@ -875,7 +882,7 @@ described in <<csrinsts>>, and the base
 unprivileged instructions are described in the following section.
 
 
-[TIP]
+[NOTE]
 ====
 The SYSTEM instructions are defined to allow simpler implementations to
 always trap to a single software trap handler. More sophisticated
@@ -883,7 +890,7 @@ implementations might execute more of each system instruction in
 hardware.
 ====
 
-include::images/wavedrom/env_call-breakpoint.adoc[]
+include::images/wavedrom/env-call-breakpoint.edn[]
 [[env-call]]
 //.Environment call and breakpoint instructions
 
@@ -906,7 +913,7 @@ to reflect that they can be used more generally than to call a
 supervisor-level operating system or debugger.
 ====
 
-[TIP]
+[NOTE]
 ====
 EBREAK was primarily designed to be used by a debugger to cause
 execution to stop and fall back into the debugger. EBREAK is also used
@@ -924,7 +931,7 @@ to distinguish a semihosting EBREAK from a debugger inserted EBREAK.
 ....
     slli x0, x0, 0x1f   # Entry NOP
     ebreak              # Break to debugger
-    srai x0, x0, 7      # NOP encoding the semihosting call number 7
+    srai x0, x0, 7      # Exit NOP
 ....
 
 Note that these three instructions must be 32-bit-wide instructions,
@@ -986,7 +993,7 @@ HINT space is reserved for standard HINTs. The remainder of the HINT
 space is designated for custom HINTs: no standard HINTs will ever be
 defined in this subspace.
 
-[TIP]
+[NOTE]
 ====
 We anticipate standard hints to eventually include memory-system spatial
 and temporal locality hints, branch prediction hints, thread-scheduling
@@ -1063,3 +1070,5 @@ hints, security tags, and instrumentation flags for simulation/emulation.
 |SLTU |_rd_=`x0` |latexmath:[$2^{10}$]
 |===
 
+TIP: When allocating `slli x0, x0, 0x1f` or `srai x0, x0, 7` as custom HINTs,
+take note of their use in semihosting calls, as described in <<ecall-ebreak>>.
diff --git a/src/rv32e.adoc b/src/rv32e.adoc
index c30b598..35c996f 100644
--- a/src/rv32e.adoc
+++ b/src/rv32e.adoc
@@ -22,7 +22,7 @@ RV64I are also compatible with RV32E and RV64E, respectively.
 RV32E and RV64E reduce the integer register count to 16 general-purpose
 registers, (`x0-x15`), where `x0` is a dedicated zero register.
 
-[TIP]
+[NOTE]
 ====
 We have found that in the small RV32I core implementations, the upper 16
 registers consume around one quarter of the total area of the core
diff --git a/src/rv64.adoc b/src/rv64.adoc
index 531158a..8e3b60b 100644
--- a/src/rv64.adoc
+++ b/src/rv64.adoc
@@ -39,7 +39,7 @@ ensure reasonable performance for 32-bit values.
 
 ==== Integer Register-Immediate Instructions
 
-include::images/wavedrom/rv64i-base-int.adoc[]
+include::images/wavedrom/rv64i-base-int.edn[]
 [[rv64i-base-int]]
 //.RV64I register-immediate instructions
 
@@ -50,7 +50,7 @@ immediate to register _rs1_ and produces the proper sign extension of a
 writes the sign extension of the lower 32 bits of register _rs1_ into
 register _rd_ (assembler pseudoinstruction SEXT.W).
 
-include::images/wavedrom/rv64i-slli.adoc[]
+include::images/wavedrom/rv64i-slli.edn[]
 [[rv64i-slli]]
 //.RV64I register-immediate (descr ADDIW) instructions
 
@@ -67,7 +67,7 @@ copied into the vacated upper bits).
 (((RV64I, SRLIW)))
 (((RV64I, RV64I-only)))
 
-include::images/wavedrom/rv64i-slliw.adoc[]
+include::images/wavedrom/rv64i-slliw.edn[]
 [[rv64i-slliw]]
 
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously
@@ -82,7 +82,7 @@ were defined to cause illegal-instruction exceptions, whereas now they
 are marked as reserved. This is a backwards-compatible change.
 ====
 
-include::images/wavedrom/rv64_lui-auipc.adoc[]
+include::images/wavedrom/rv64-lui-auipc.edn[]
 [[rv64_lui-auipc]]
 //.RV64I register-immediate (descr) instructions
 
@@ -108,7 +108,7 @@ with LD, AUIPC with JALR, etc. in RV64I is
 ==== Integer Register-Register Operations
 
 //this diagramdoesn't match the tex specification
-include::images/wavedrom/rv64i_int-reg-reg.adoc[]
+include::images/wavedrom/rv64i-int-reg-reg.edn[]
 [[int_reg-reg]]
 //.RV64I integer register-register instructions
 
@@ -136,7 +136,7 @@ results to 64 bits. The shift amount is given by _rs2[4:0]_.
 RV64I extends the address space to 64 bits. The execution environment
 will define what portions of the address space are legal to access.
 
-include::images/wavedrom/load_store.adoc[]
+include::images/wavedrom/load-store.edn[]
 [[load_store]]
 //.Load and store instructions
 
diff --git a/src/scalar-crypto.adoc b/src/scalar-crypto.adoc
index 63064dc..873c43c 100644
--- a/src/scalar-crypto.adoc
+++ b/src/scalar-crypto.adoc
@@ -33,12 +33,6 @@ This is found in <<crypto_scalar_es>>.
 It also contains a mechanism allowing core implementers to provide
 _"Constant Time Execution"_ guarantees in <<crypto_scalar_zkt>>.
 
-A companion document _Volume II: Vector Instructions_, describes
-instruction proposals which build on the RISC-V Vector Extension.
-The Vector Cryptography extension is currently a work in progress
-waiting for the base Vector extension to stabilise.
-We expect to pick up this work in earnest in Q4-2021 or Q1-2022.
-
 [[crypto_scalar_audience]]
 ==== Intended Audience
 
@@ -2313,7 +2307,7 @@ are each represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sigma0 transform for SHA2-512 may be computed on RV32
@@ -2387,7 +2381,7 @@ are each represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sigma0 transform for SHA2-512 may be computed on RV32
@@ -2461,7 +2455,7 @@ are each represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sigma1 transform for SHA2-512 may be computed on RV32
@@ -2535,7 +2529,7 @@ are each represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sigma1 transform for SHA2-512 may be computed on RV32
@@ -2608,7 +2602,7 @@ is represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sum0 transform for SHA2-512 may be computed on RV32
@@ -2682,7 +2676,7 @@ is represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sum1 transform for SHA2-512 may be computed on RV32
@@ -3562,15 +3556,15 @@ The 32-bit contents of `seed` are as follows:
 |`15: 0` |`entropy` |16 bits of randomness, only when `OPST=ES16`.
 |=======================================================================
 
-The `seed` CSR must be accessed with a read-write instruction. A read-only
-instruction such as `CSRRS/CSRRC` with `rs1=x0` or `CSRRSI/CSRRCI` with
-`uimm=0` will raise an illegal instruction exception.
+Attempts to access the `seed` CSR using a read-only CSR-access instruction
+(`CSRRS`/`CSRRC` with `rs1=x0` or `CSRRSI`/`CSRRCI` with `uimm=0`) raise an
+illegal instruction exception; any other CSR-access instruction may be used
+to access `seed`.
 The write value (in `rs1` or `uimm`) must be ignored by implementations.
 The purpose of the write is to signal polling and flushing.
 
-The instruction `csrrw rd, seed, x0` can be used for fetching seed status
-and entropy values. It is available on both RV32 and RV64 base architectures
-and will zero-extend the 32-bit word to XLEN bits.
+Software normally uses the instruction `csrrw rd, seed, x0` to read the `seed`
+CSR.
 
 Encoding::
 [wavedrom, , svg]
@@ -4639,7 +4633,9 @@ refreshed (reseeded) for forward and backward security.
 
 ==== Specific Rationale and Considerations
 
-===== (<<crypto_scalar_seed_csr>>) The `seed` CSR 
+=====  The `seed` CSR 
+
+See <<crypto_scalar_seed_csr>>.
 
 The interface was designed to be simple so that a vendor- and
 device-independent driver component (e.g., in Linux kernel,
@@ -4659,7 +4655,7 @@ a write operation on this particular CSR.
 A blocking instruction may have been easier to use, but most users should
 be querying a (D)RBG instead of an entropy source.
 Without a polling-style mechanism, the entropy source could hang for
-thousands of cycles under some circumstances. A `wfi` ot `pause`
+thousands of cycles under some circumstances. A `wfi` or `pause`
 mechanism (at least potentially) allows energy-saving sleep on MCUs
 and context switching on higher-end CPUs.
 
@@ -4675,7 +4671,9 @@ conditioning discussed in <<crypto_scalar_appx_es_crypto-cond>>),
 and the desire to have all of the bits "in the same place" on
 both RV32 and RV64 architectures for programming convenience.
 
-===== (<<crypto_scalar_es_req_90b>>) NIST SP 800-90B
+===== NIST SP 800-90B
+
+See <<crypto_scalar_es_req_90b>>.
 
 SP 800-90C cite:[BaKeRo:21] states that each conditioned block of n bits
 is required to have n+64 bits of input entropy to attain full entropy.
@@ -4706,7 +4704,9 @@ Section 4.4 of cite:[TuBaKe:18]: the repetition count test and adaptive
 proportion test, or show that the same flaws will be detected
 by vendor-defined tests.
 
-===== (<<crypto_scalar_es_req_ptg2>>) BSI AIS-31
+===== BSI AIS-31
+
+See <<crypto_scalar_es_req_ptg2>>.
 
 PTG.2 is one of the security and functionality classes defined in
 BSI AIS 20/31 cite:[KiSc11]. The PTG.2 source requirements work as a
@@ -4739,7 +4739,9 @@ PTG.2 modules built and certified to the AIS-31 standard can also meet the
 "full entropy" condition after 2:1 cryptographic conditioning, but not
 necessarily so. The technical validation process is somewhat different.
 
-===== (<<crypto_scalar_es_req_virt>>) Virtual Sources
+===== Virtual Sources
+
+<<crypto_scalar_es_req_virt>>.
 
 All sources that are not direct physical sources (meeting the SP 800-90B
 or the AIS-31 PTG.2 requirements) need to meet the security requirements
@@ -4755,7 +4757,9 @@ standards and applications. The 256-bit requirement maps to
 in Suite B and the newer U.S. Government CNSA Suite cite:[NS15].
 
 [[crypto_scalar_appx_es_access]]
-===== (<<crypto_scalar_es_access>>) Security Considerations for Direct Hardware Access
+===== Security Considerations for Direct Hardware Access
+
+<<crypto_scalar_es_access>>.
 
 The ISA implementation and system design must try to ensure that the
 hardware-software interface minimizes avenues for adversarial
@@ -4763,7 +4767,7 @@ information flow even if not explicitly forbidden in the specification.
 
 For security, virtualization requires both conditioning and DRBG processing
 of physical entropy output. It is recommended if a single physical entropy
-source is shared between multiple different virtual machnies or if the 
+source is shared between multiple different virtual machines or if the 
 guest OS is untrusted. A virtual entropy source is significantly more
 resistant to depletion attacks and also lessens the risk from covert channels.
 
@@ -4939,7 +4943,7 @@ operational at the same time.
 The noise source state shall be protected from adversarial
 knowledge or influence to the greatest extent possible. The methods
 used for this shall be documented, including a description of the
-(conceptual) security boundarys role in protecting the noise source
+(conceptual) security boundary's role in protecting the noise source
 from adversarial observation or influence.
 
 An entropy source is a singular resource, subject to depletion
diff --git a/src/smcntrpmf.adoc b/src/smcntrpmf.adoc
index ca87901..c47402f 100644
--- a/src/smcntrpmf.adoc
+++ b/src/smcntrpmf.adoc
@@ -34,7 +34,7 @@ mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode fil
 
 When all __x__INH bits are zero, event counting is enabled in all modes.
 
-For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.  Bits 57:56 are reserved for possible future modes.  
+For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.
 
 For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR.
 
diff --git a/src/smepmp.adoc b/src/smepmp.adoc
index 0f602c5..7bffde7 100644
--- a/src/smepmp.adoc
+++ b/src/smepmp.adoc
@@ -118,7 +118,7 @@ Also when ``mseccfg.MML`` is set, according to 4b it’s not possible to add a _
 +
 [NOTE]
 ====
-If ``mseccfg.RLB`` is not used and left unset, it wil be locked as soon as a PMP rule/entry with the ``pmpcfg.L`` bit set is configured.
+If ``mseccfg.RLB`` is not used and left unset, it will be locked as soon as a PMP rule/entry with the ``pmpcfg.L`` bit set is configured.
 ====
 +
 [IMPORTANT]
@@ -151,7 +151,7 @@ To make sure that shared data regions can’t be executed and shared code region
 +
 [NOTE]
 ====
-For adding _Shared-region_ rules with executable privileges to share code segments between M-mode and S/U-mode, ``mseccfg.RLB`` needs to be implemented, or else such rules can only be added together with ``mseccfg.MML`` being set on *PMP Reset*. That's because the reserved encoding ``pmpcfg.RW=01`` being used for _Shared-region_ rules is only defined when ``mseccfg.MML`` is set, and 4b prevents the adition of rules with executable privileges on M-mode after ``mseccfg.MML`` is set unless ``mseccfg.RLB`` is also set.
+For adding _Shared-region_ rules with executable privileges to share code segments between M-mode and S/U-mode, ``mseccfg.RLB`` needs to be implemented, or else such rules can only be added together with ``mseccfg.MML`` being set on *PMP Reset*. That's because the reserved encoding ``pmpcfg.RW=01`` being used for _Shared-region_ rules is only defined when ``mseccfg.MML`` is set, and 4b prevents the addition of rules with executable privileges on M-mode after ``mseccfg.MML`` is set unless ``mseccfg.RLB`` is also set.
 ====
 +
 [NOTE]
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index d79d733..fee952f 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -711,6 +711,7 @@ instruction bits is implemented, `stval` must also be able to hold all
 values less than latexmath:[$2^N$], where latexmath:[$N$] is the smaller
 of SXLEN and ILEN.
 
+[[sec:senvcfg]]
 ==== Supervisor Environment Configuration (`senvcfg`) Register 
 
 The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as
@@ -1183,7 +1184,7 @@ without the need to execute an SFENCE.VMA instruction. Changing
 immediately, without the need to execute an SFENCE.VMA instruction.
 Likewise, changes to `satp`.ASID take effect immediately.
 
-[TIP]
+[NOTE]
 ====
 The following common situations typically require executing an
 SFENCE.VMA instruction:
diff --git a/src/unpriv-cfi.adoc b/src/unpriv-cfi.adoc
index a700715..ed17e74 100644
--- a/src/unpriv-cfi.adoc
+++ b/src/unpriv-cfi.adoc
@@ -773,7 +773,7 @@ data values.
 ----
   if privilege_mode != M && menvcfg.SSE == 0
       raise illegal-instruction exception
-  if S-mode not implemented
+  else if S-mode not implemented
       raise illegal-instruction exception
   else if privilege_mode == U && senvcfg.SSE == 0
       raise illegal-instruction exception
@@ -797,7 +797,7 @@ address in `rs1`.
 ----
   if privilege_mode != M && menvcfg.SSE == 0
       raise illegal-instruction exception
-  if S-mode not implemented
+  else if S-mode not implemented
       raise illegal-instruction exception
   else if privilege_mode == U && senvcfg.SSE == 0
       raise illegal-instruction exception
diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc
index 467d8de..30e44dc 100644
--- a/src/v-st-ext.adoc
+++ b/src/v-st-ext.adoc
@@ -156,7 +156,7 @@ The `vtype` register has five fields, `vill`, `vma`, `vta`,
 `vsew[2:0]`, and `vlmul[2:0]`.  Bits `vtype[XLEN-2:8]` should be
 written with zero, and non-zero values in this field are reserved.
 
-include::images/wavedrom/vtype-format.adoc[]
+include::images/wavedrom/vtype-format.edn[]
 
 NOTE: A small implementation supporting ELEN=32 requires only seven
 bits of state in `vtype`: two bits for `ma` and `ta`, two bits for
@@ -878,11 +878,11 @@ floating-point load/store 12-bit immediate field to provide further
 vector instruction encoding, with bit 25 holding the standard vector
 mask bit (see <<sec-vector-mask-encoding>>).
 
-include::images/wavedrom/vmem-format.adoc[]
+include::images/wavedrom/vmem-format.edn[]
 
-include::images/wavedrom/valu-format.adoc[]
+include::images/wavedrom/valu-format.edn[]
 
-include::images/wavedrom/vcfg-format.adoc[]
+include::images/wavedrom/vcfg-format.edn[]
 
 Vector instructions can have scalar or vector source operands and
 produce scalar or vector results, and most vector instructions can be
@@ -1143,11 +1143,11 @@ their arguments, and write the new value of `vl` into `rd`.
  vsetvl  rd, rs1, rs2      # rd = new vl, rs1 = AVL, rs2 = new vtype value
 ----
 
-include::images/wavedrom/vcfg-format.adoc[]
+include::images/wavedrom/vcfg-format.edn[]
 
 ==== `vtype` encoding
 
-include::images/wavedrom/vtype-format.adoc[]
+include::images/wavedrom/vtype-format.edn[]
 
 The new `vtype` value is encoded in the immediate fields of `vsetvli`
 and `vsetivli`, and in the `rs2` register for `vsetvl`.
@@ -1345,7 +1345,7 @@ floating-point load/store 12-bit immediate field to provide further
 vector instruction encoding, with bit 25 holding the standard vector
 mask bit (see <<sec-vector-mask-encoding>>).
 
-include::images/wavedrom/vmem-format.adoc[]
+include::images/wavedrom/vmem-format.edn[]
 
 [cols="4,12"]
 |===
@@ -2171,7 +2171,7 @@ The vector arithmetic instructions use a new major opcode (OP-V =
 1010111~2~) which neighbors OP-FP.  The three-bit `funct3` field is
 used to define sub-categories of vector instructions.
 
-include::images/wavedrom/valu-format.adoc[]
+include::images/wavedrom/valu-format.edn[]
 
 [[sec-arithmetic-encoding]]
 ==== Vector Arithmetic Instruction encoding
@@ -3459,7 +3459,7 @@ The following table gives the seven MSBs of the output significand as a
 function of the LSB of the normalized input exponent and the six MSBs of the
 normalized input significand; the other bits of the output significand are zero.
 
-include::images/wavedrom/vfrsqrt7.adoc[]
+include::images/wavedrom/vfrsqrt7.edn[]
 
 NOTE: For example, when SEW=32, vfrsqrt7(0x00718abc ({approx} 1.043e-38)) = 0x5f080000 ({approx} 9.800e18), and vfrsqrt7(0x7f765432 ({approx} 3.274e38)) = 0x1f820000 ({approx} 5.506e-20).
 
@@ -3546,7 +3546,7 @@ The following table gives the seven MSBs of the normalized output significand
 as a function of the seven MSBs of the normalized input significand; the other
 bits of the normalized output significand are zero.
 
-include::images/wavedrom/vfrec7.adoc[]
+include::images/wavedrom/vfrec7.edn[]
 
 If the normalized output exponent is 0 or -1, the result is subnormal: the
 output exponent is 0, and the output significand is given by concatenating
@@ -5245,7 +5245,7 @@ this constraint is backwards-compatible.
 
 NOTE: This constraint prevents element groups being broken across
 stripmining iterations in vector-length-agnostic code when a
-VLMAX-size vector would otherwise be able to accomodate a whole number
+VLMAX-size vector would otherwise be able to accommodate a whole number
 of element groups.
 
 NOTE: If EEW is encoded statically in the instruction, or if an
@@ -5322,5 +5322,5 @@ the mask element group is set).
 
 === Vector Instruction Listing
 
-include::images/wavedrom/v-inst-table.adoc[]
+include::images/wavedrom/v-inst-table.edn[]
 
diff --git a/src/vector-crypto.adoc b/src/vector-crypto.adoc
index 695a46a..8c422e1 100644
--- a/src/vector-crypto.adoc
+++ b/src/vector-crypto.adoc
@@ -559,7 +559,7 @@ efficiently.
 [NOTE]
 ====
 This Zvkb extension is a proper subset of the Zvbb extension.
-Zvkb allows for vector crypto implementations without incuring
+Zvkb allows for vector crypto implementations without incurring
 the the cost of implementing the additional bitmanip instructions
 in the Zvbb extension: vbrev.v, vclz.v, vctz.v, vcpop.v, and vwsll.[vv,vx,vi].
 ====
@@ -1107,7 +1107,7 @@ proper subset of <<Zvbb>>
 - vmerge.v[ivx]m
 
 ===== permute
-In the `.vv` and `.xv` forms of the `vragather[ei16]` instructions,
+In the `.vv` and `.xv` forms of the `vrgather[ei16]` instructions,
 the values in `vs1` and `rs1` are used for control and therefore are exempt from DIEL.
 
 - vrgather.v[ivx]
@@ -3190,7 +3190,7 @@ next state.
 // output is the new values of _a, b, e_ and _f_ after performing 2 rounds of the hash
 // computation. The new values, _c_, _d_, _g_, and _h_, are equal to the input values for _a_, _b_, // _e_, _f_ respectively.
 
-// [TIP]
+// [NOTE]
 // .Note to software developers
 // ====
 // The MessageSchedplus constant input to this instruction is generated by Software
@@ -3198,7 +3198,7 @@ next state.
 // round constant as defined in the NIST specification (see <<zvknh>>).
 // ====
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The NIST standard (see <<zvknh>>) requires the final hash to be in big-endian byte ordering
@@ -3217,7 +3217,7 @@ Having a high and low version of this instruction typically improves performance
 interleaving independent hashing operations (i.e., when hashing several files at once).
 ====
 
-// [TIP]
+// [NOTE]
 // .Note to software developers
 // ====
 // These instructions take in two SEW words _W1_ and _W0_ which are the next two words of the message
@@ -3378,7 +3378,7 @@ Eleven of the last 16 `SEW`-sized message-schedule words from `vd` (oldest), `vs
 and `vs1` (most recent) are processed to produce the
 next 4 message-schedule words.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The first 16 SEW-sized words of the message schedule come from the _message block_
@@ -3389,7 +3389,7 @@ All of the subsequent message schedule words are produced by this instruction an
 therefore do not require an endian swap.
 ====
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 Software is required to pack the words into element groups
@@ -3419,7 +3419,7 @@ lower indices indicating older words.
 // {W~11~, W~10~, W~9~, W~4~} +
 // {W~15~, W~14~, W~13~, W~12~}`
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The {W~11~, W~10~, W~9~, W~4~} element group can easily be formed by using a vector
diff --git a/src/zfa.adoc b/src/zfa.adoc
index 942aeef..20223d8 100644
--- a/src/zfa.adoc
+++ b/src/zfa.adoc
@@ -57,13 +57,13 @@ like FMV.W.X, but with _rs2_=1.
 |31 |_Canonical NaN_ |`0` |`11111111` |`100...000`
 |===
 
-[TIP]
+[NOTE]
 ====
 The preferred assembly syntax for entries 1, 30, and 31 is `min`, `inf`,
 and `nan`, respectively. For entries 0 through 29 (including entry 1),
 the assembler will accept decimal constants in C-like syntax.
 ====
-[TIP]
+[NOTE]
 ====
 The set of 32 constants was chosen by examining floating-point
 libraries, including the C standard math library, and to optimize
@@ -170,7 +170,7 @@ FCVT.W.D with the same input operand.
 This instruction is only provided if the D extension is implemented. It
 is encoded like FCVT.W.D, but with the rs2 field set to 8 and the _rm_
 field set to 1 (RTZ). Other _rm_ values are _reserved_.
-[TIP]
+[NOTE]
 ====
 The assembly syntax requires the RTZ rounding mode to be explicitly
 specified, i.e., `fcvtmod.w.d rd, rs1, rtz`.
diff --git a/src/zfh.adoc b/src/zfh.adoc
index ab30e3d..e363a1c 100644
--- a/src/zfh.adoc
+++ b/src/zfh.adoc
@@ -27,7 +27,7 @@ halflatexmath:[$+$]singlelatexmath:[$\rightarrow$]half.
 New 16-bit variants of LOAD-FP and STORE-FP instructions are added,
 encoded with a new value for the funct3 width field.
 
-include::images/wavedrom/sp-load-store.adoc[]
+include::images/wavedrom/sp-load-store.edn[]
 [[sp-load-store]]
 //.Half-precision load and store instructions
 
@@ -58,9 +58,9 @@ The half-precision floating-point computational instructions are defined
 analogously to their single-precision counterparts, but operate on
 half-precision operands and produce half-precision results.
 
-include::images/wavedrom/spfloat-zfh.adoc[]
+include::images/wavedrom/spfloat-zfh.edn[]
 
-include::images/wavedrom/spfloat2-zfh.adoc[]
+include::images/wavedrom/spfloat2-zfh.edn[]
 
 === Half-Precision Conversion and Move Instructions
 
@@ -75,7 +75,7 @@ FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or
 from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only
 instructions.
 
-include::images/wavedrom/half-prec-conv-and-mv.adoc[]
+include::images/wavedrom/half-prec-conv-and-mv.edn[]
 [[half-prec-conv-and-mv]]
 
 New floating-point-to-floating-point conversion instructions are added.
@@ -90,14 +90,14 @@ is present, FCVT.Q.H or FCVT.H.Q converts a half-precision
 floating-point number to a quad-precision floating-point number, or
 vice-versa, respectively.
 
-include::images/wavedrom/half-prec-flpt-to-flpt-conv.adoc[]
+include::images/wavedrom/half-prec-flpt-to-flpt-conv.edn[]
 [[half-prec-flpt-to-flpt-conv]]
 
 Floating-point to floating-point sign-injection instructions, FSGNJ.H,
 FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision
 sign-injection instruction.
 
-include::images/wavedrom/flt-to-flt-sgn-inj-instr.adoc[]
+include::images/wavedrom/flt-to-flt-sgn-inj-instr.edn[]
 [[flt-to-flt-sgn-inj-instr]]
 
 Instructions are provided to move bit patterns between the
@@ -113,7 +113,7 @@ floating-point register _rd_, NaN-boxing the result.
 FMV.X.H and FMV.H.X do not modify the bits being transferred; in
 particular, the payloads of non-canonical NaNs are preserved.
 
-include::images/wavedrom/flt-pt-to-int-move.adoc[]
+include::images/wavedrom/flt-pt-to-int-move.edn[]
 [[flt-pt-to-int-move]]
 
 === Half-Precision Floating-Point Compare Instructions
@@ -122,7 +122,7 @@ The half-precision floating-point compare instructions are defined
 analogously to their single-precision counterparts, but operate on
 half-precision operands.
 
-include::images/wavedrom/half-pr-flt-pt-compare.adoc[]
+include::images/wavedrom/half-pr-flt-pt-compare.edn[]
 [[half-pr-flt-pt-compare]]
 
 === Half-Precision Floating-Point Classify Instruction
@@ -131,7 +131,7 @@ The half-precision floating-point classify instruction, FCLASS.H, is
 defined analogously to its single-precision counterpart, but operates on
 half-precision operands.
 
-include::images/wavedrom/half-pr-flt-pt-class.adoc[]
+include::images/wavedrom/half-pr-flt-pt-class.edn[]
 [[half-pr-flt-class]]
 
 === "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point
diff --git a/src/zfinx.adoc b/src/zfinx.adoc
index 035222d..aae57fe 100644
--- a/src/zfinx.adoc
+++ b/src/zfinx.adoc
@@ -64,7 +64,7 @@ registers is compatible with the existing RV64 calling conventions, which leave
 === Zdinx
 
 The Zdinx extension provides analogous double-precision floating-point
-instructions. The Zdinx extension requires the Zfinx extension.
+instructions. The Zdinx extension depends upon the Zfinx extension.
 
 The Zdinx extension adds all of the instructions that the D extension
 adds, _except_ for the transfer instructions FLD, FSD, FMV.D.X, FMV.X.D,
@@ -105,7 +105,7 @@ however.
 === Zhinx
 
 The Zhinx extension provides analogous half-precision floating-point
-instructions. The Zhinx extension requires the Zfinx extension.
+instructions. The Zhinx extension depends upon the Zfinx extension.
 
 The Zhinx extension adds all of the instructions that the Zfh extension
 adds, _except_ for the transfer instructions FLH, FSH, FMV.H.X, and
@@ -120,7 +120,7 @@ number.
 
 The Zhinxmin extension provides minimal support for 16-bit
 half-precision floating-point instructions that operate on the `x`
-registers. The Zhinxmin extension requires the Zfinx extension.
+registers. The Zhinxmin extension depends upon the Zfinx extension.
 
 The Zhinxmin extension includes the following instructions from the
 Zhinx extension: FCVT.S.H and FCVT.H.S. If the Zdinx extension is
diff --git a/src/zicsr.adoc b/src/zicsr.adoc
index 0e16de4..8d3db68 100644
--- a/src/zicsr.adoc
+++ b/src/zicsr.adoc
@@ -24,7 +24,7 @@ CSR specifier is encoded in the 12-bit _csr_ field of the instruction
 held in bits 31-20. The immediate forms use a 5-bit zero-extended
 immediate encoded in the _rs1_ field.
 
-include::images/wavedrom/csr-instr.adoc[]
+include::images/wavedrom/csr-instr.edn[]
 
 The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in
 the CSRs and integer registers. CSRRW reads the old value of the CSR,
diff --git a/src/zifencei.adoc b/src/zifencei.adoc
index 666effb..a234c67 100644
--- a/src/zifencei.adoc
+++ b/src/zifencei.adoc
@@ -17,7 +17,7 @@ snooping/invalidation overhead by writing translated instructions to
 memory regions that are known not to reside in the I-cache.
 ====
 '''
-[TIP]
+[NOTE]
 ====
 The FENCE.I instruction was designed to support a wide variety of
 implementations. A simple implementation can flush the local instruction
@@ -61,7 +61,7 @@ given address specified in _rs1_, and/or allowing software to use an ABI
 that relies on machine-mode cache-maintenance operations.
 ====
 
-include::images/wavedrom/zifencei-ff.adoc[]
+include::images/wavedrom/zifencei-ff.edn[]
 [[zifencei-ff]]
 //.FENCE.I instruction
 (((FENCE.I, synchronization)))
diff --git a/src/zihintntl.adoc b/src/zihintntl.adoc
index 8e225cb..7ddbb4b 100644
--- a/src/zihintntl.adoc
+++ b/src/zihintntl.adoc
@@ -178,7 +178,7 @@ preferentially take the interrupt before the NTL, rather than between
 the NTL and the memory access.
 ====
 '''
-[TIP]
+[NOTE]
 ====
 Since the NTL instructions are encoded as ADDs, they can be used within
 LR/SC loops without voiding the forward-progress guarantee. But, since
diff --git a/src/zihintpause.adoc b/src/zihintpause.adoc
index 9df71f3..12fde13 100644
--- a/src/zihintpause.adoc
+++ b/src/zihintpause.adoc
@@ -40,7 +40,7 @@ performance.
 PAUSE is encoded as a FENCE instruction with _pred_=`W`, _succ_=`0`, _fm_=`0`,
 _rd_=`x0`, and _rs1_=`x0`.
 
-//include::images/wavedrom/zihintpause-hint.adoc[]
+//include::images/wavedrom/zihintpause-hint.edn[]
 //[zihintpause-hint]
 //.Zihintpause fence instructions
 
diff --git a/src/zimop.adoc b/src/zimop.adoc
index ab88a4a..307d9a1 100644
--- a/src/zimop.adoc
+++ b/src/zimop.adoc
@@ -32,7 +32,7 @@ Unless redefined by another extension, these instructions simply write 0 to
 `x[rd]`.  Their encoding allows future extensions to define them to read `x[rs1]`,
 as well as write `x[rd]`.
 
-include::images/wavedrom/mop-r.adoc[]
+include::images/wavedrom/mop-r.edn[]
 [[mop-r]]
 
 The Zimop extension additionally defines 8 MOP instructions named
@@ -41,7 +41,7 @@ Unless redefined by another extension, these instructions simply
 write 0 to `x[rd]`.  Their encoding allows future extensions to define them to
 read `x[rs1]` and `x[rs2]`, as well as write `x[rd]`.
 
-include::images/wavedrom/mop-rr.adoc[]
+include::images/wavedrom/mop-rr.edn[]
 [[mop-rr]]
 
 NOTE: The recommended assembly syntax for MOP.R.__n__ is MOP.R.__n__ rd, rs1,
@@ -74,9 +74,9 @@ are defined to _not_ write any register.
 Their encoding allows future extensions to define them to read register
 `x[__n__]`.
 
-The Zcmop extension requires the Zca extension.
+The Zcmop extension depends upon the Zca extension.
 
-include::images/wavedrom/c-mop.adoc[]
+include::images/wavedrom/c-mop.edn[]
 [[c-mop]]
 
 NOTE: Very few suitable 16-bit encoding spaces exist.  This space was chosen