diff options
Diffstat (limited to 'src/f-st-ext.adoc')
| -rw-r--r-- | src/f-st-ext.adoc | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc index 96d5b44..a5a1816 100644 --- a/src/f-st-ext.adoc +++ b/src/f-st-ext.adoc @@ -21,7 +21,7 @@ instructions operate on values in the floating-point register file. Floating-point load and store instructions transfer floating-point values between registers and memory. Instructions to transfer values to and from the integer register file are also provided. -[TIP] +[NOTE] ==== We considered a unified register file for both integer and floating-point values as this simplifies software register allocation @@ -87,7 +87,7 @@ operations and holds the accrued exception flags, as shown in <<fcsr>>. [[fcsr, Floating-Point Control and Status Register]] .Floating-point control and status register -include::images/wavedrom/float-csr.adoc[] +include::images/wavedrom/float-csr.edn[] The `fcsr` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the @@ -189,7 +189,7 @@ quiet bit. For single-precision floating-point, this corresponds to the pattern (((NaN, generation))) (((NaN, propagation))) -[TIP] +[NOTE] ==== We considered propagating NaN payloads, as is recommended by the standard, but this decision would have increased hardware cost. @@ -231,7 +231,7 @@ signals. Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register _rs1_ and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register _rd_. FSW stores a single-precision value from floating-point register _rs2_ to memory. -include::images/wavedrom/sp-load-store-2.adoc[] +include::images/wavedrom/sp-load-store-2.edn[] [[sp-ldst]] //.SP load and store @@ -283,7 +283,7 @@ minimumNumber and maximumNumber operations, rather than the IEEE handling of signaling NaNs. ==== -include::images/wavedrom/spfloat.adoc[] +include::images/wavedrom/spfloat.edn[] [[spfloat]] //.Single-Precision Floating-Point Computational Instructions (((floating point, fused multiply-add))) @@ -315,7 +315,7 @@ RISC-V FNMSUB and FNMADD instruction names are swapped compared to x86 and ARM. ==== -include::images/wavedrom/spfloat2.adoc[] +include::images/wavedrom/spfloat2.edn[] [[fnmaddsub]] //.F[N]MADD/F[N]MSUB instructions @@ -389,7 +389,7 @@ All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. -include::images/wavedrom/spfloat-cn-cmp.adoc[] +include::images/wavedrom/spfloat-cn-cmp.edn[] [[fcvt]] //.SP float convert and move @@ -405,7 +405,7 @@ FSGNJN.S _rx, ry, ry_ moves the negation of _ry_ to _rx_ (assembler pseudoinstruction FNEG.S _rx, ry_); and FSGNJX.S _rx, ry, ry_ moves the absolute value of _ry_ to _rx_ (assembler pseudoinstruction FABS.S _rx, ry_). -include::images/wavedrom/spfloat-sign-inj.adoc[] +include::images/wavedrom/spfloat-sign-inj.edn[] [[inj]] [NOTE] @@ -428,11 +428,11 @@ preserved. The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools. ==== -include::images/wavedrom/spfloat-mv.adoc[] +include::images/wavedrom/spfloat-mv.edn[] [[spfloat-mv]] //.SP floating point move -[TIP] +[NOTE] ==== The base floating-point ISA was defined so as to allow implementations to employ an internal recoding of the floating-point format in registers to simplify handling of subnormal values and possibly to reduce functional unit latency. To this end, the F extension avoids @@ -454,7 +454,7 @@ _signaling_ comparisons: that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a _quiet_ comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN. -include::images/wavedrom/spfloat-comp.adoc[] +include::images/wavedrom/spfloat-comp.edn[] [[spfloat-comp]] //.SP floating point compare @@ -478,7 +478,7 @@ _rd_ are cleared. Note that exactly one bit in _rd_ will be set. FCLASS.S does not set the floating-point exception flags. (((floating-point, classification))) -include::images/wavedrom/spfloat-classify.adoc[] +include::images/wavedrom/spfloat-classify.edn[] [[spfloat-classify]] //.SP floating point classify |