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| author | Andrew Waterman <andrew@sifive.com> | 2024-07-11 18:40:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-07-11 18:40:25 -0700 |
| commit | f2116b9f1194710fa275da6d360d5a4c8ceb6bc5 (patch) | |
| tree | 6e95c54f0bda21165e875e3517decace9dbb2da5 /src | |
| parent | b508ca01eac9d777d47e1b84ba27e975c0d8960f (diff) | |
| download | riscv-isa-manual-f2116b9f1194710fa275da6d360d5a4c8ceb6bc5.zip riscv-isa-manual-f2116b9f1194710fa275da6d360d5a4c8ceb6bc5.tar.gz riscv-isa-manual-f2116b9f1194710fa275da6d360d5a4c8ceb6bc5.tar.bz2 | |
Fix mnemonics of Zbkx/Zbkb instructions
Resolves #1522
Diffstat (limited to 'src')
| -rw-r--r-- | src/b-st-ext.adoc | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc index 7b0a0a5..9605aa8 100644 --- a/src/b-st-ext.adoc +++ b/src/b-st-ext.adoc @@ -912,7 +912,7 @@ common operations in cryptographic workloads. | ✓ | ✓ -| rev.b +| brev8 | <<insns-revb>> | ✓ @@ -984,12 +984,12 @@ latency does not depend on the (secret) data being operated on. |✓ |✓ -|xperm.n _rd_, _rs1_, _rs2_ +|xperm4 _rd_, _rs1_, _rs2_ |<<#insns-xpermn>> |✓ |✓ -|xperm.b _rd_, _rs1_, _rs2_ +|xperm8 _rd_, _rs1_, _rs2_ |<<#insns-xpermb>> |=== @@ -2569,13 +2569,13 @@ Included in:: <<< [#insns-revb,reftext="Reverse bits in bytes"] -==== rev.b +==== brev8 Synopsis:: Reverse the bits in each byte of a source register. Mnemonic:: -rev.b _rd_, _rs_ +brev8 _rd_, _rs_ Encoding:: [wavedrom, , svg] @@ -3472,13 +3472,13 @@ Included in:: <<< [#insns-xpermb,reftext="Crossbar permutation (bytes)"] -==== xperm.b +==== xperm8 Synopsis:: Byte-wise lookup of indices into a vector in registers. Mnemonic:: -xperm.b _rd_, _rs1_, _rs2_ +xperm8 _rd_, _rs1_, _rs2_ Encoding:: [wavedrom, , svg] @@ -3495,7 +3495,7 @@ Encoding:: .... Description:: -The xperm.b instruction operates on bytes. +The xperm8 instruction operates on bytes. The _rs1_ register contains a vector of XLEN/8 8-bit elements. The _rs2_ register contains a vector of XLEN/8 8-bit indexes. The result is each element in _rs2_ replaced by the indexed element in _rs1_, @@ -3533,13 +3533,13 @@ Included in:: <<< [#insns-xpermn,reftext="Crossbar permutation (nibbles)"] -==== xperm.n +==== xperm4 Synopsis:: Nibble-wise lookup of indices into a vector. Mnemonic:: -xperm.n _rd_, _rs1_, _rs2_ +xperm4 _rd_, _rs1_, _rs2_ Encoding:: [wavedrom, , svg] @@ -3556,7 +3556,7 @@ Encoding:: .... Description:: -The xperm.n instruction operates on nibbles. +The xperm4 instruction operates on nibbles. The _rs1_ register contains a vector of XLEN/4 4-bit elements. The _rs2_ register contains a vector of XLEN/4 4-bit indexes. The result is each element in _rs2_ replaced by the indexed element in _rs1_, |