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author | Bruce Hoult <bruce@hoult.org> | 2018-12-20 10:56:21 -0800 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2018-12-20 10:56:21 -0800 |
commit | c65e409ed4a755178631e34f2dc5f0f95f488dc6 (patch) | |
tree | c011eca05592823347cbfeea1e7c75240e00dddc /src | |
parent | 39695b4bb92425a611ca3989d49bcbe5136a3ca8 (diff) | |
download | riscv-isa-manual-c65e409ed4a755178631e34f2dc5f0f95f488dc6.zip riscv-isa-manual-c65e409ed4a755178631e34f2dc5f0f95f488dc6.tar.gz riscv-isa-manual-c65e409ed4a755178631e34f2dc5f0f95f488dc6.tar.bz2 |
Clarify sign extension of W and D instructions (#313)
Diffstat (limited to 'src')
-rw-r--r-- | src/rv128.tex | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/rv128.tex b/src/rv128.tex index 64515e3..7ba3cf7 100644 --- a/src/rv128.tex +++ b/src/rv128.tex @@ -41,11 +41,13 @@ RV128I builds upon RV64I in the same way RV64I builds upon RV32I, with integer registers extended to 128 bits (i.e., XLEN=128). Most integer computational instructions are unchanged as they are defined to operate on XLEN bits. The RV64I ``*W'' integer instructions that -operate on 32-bit values in the low bits of a register are retained, -and a new set of ``*D'' integer instructions that operate on 64-bit -values held in the low bits of the 128-bit integer registers are -added. The ``*D'' instructions consume two major opcodes (OP-IMM-64 -and OP-64) in the standard 32-bit encoding. +operate on 32-bit values in the low bits of a register are retained +but now sign extend their results from bit 31 to bit 127. A new set of +``*D'' integer instructions are added that operate on 64-bit values +held in the low bits of the 128-bit integer registers and sign extend +their results from bit 63 to bit 127. The ``*D'' instructions consume +two major opcodes (OP-IMM-64 and OP-64) in the standard 32-bit +encoding. \begin{commentary} To improve compatibility with RV64, in a reverse of how RV32 to RV64 |