diff options
| author | elisa <elisa@riscv.org> | 2021-11-15 12:20:04 -0800 |
|---|---|---|
| committer | elisa <elisa@riscv.org> | 2021-11-15 12:20:04 -0800 |
| commit | 4f7e910f4d3bfb3008bbf9f017c61159ed09dfa6 (patch) | |
| tree | 1a4313afc5d32b535017b7e12a99de800a02e25e /src | |
| parent | c159e5863a3584e13ab0e8c516623ca297aa0618 (diff) | |
| download | riscv-isa-manual-4f7e910f4d3bfb3008bbf9f017c61159ed09dfa6.zip riscv-isa-manual-4f7e910f4d3bfb3008bbf9f017c61159ed09dfa6.tar.gz riscv-isa-manual-4f7e910f4d3bfb3008bbf9f017c61159ed09dfa6.tar.bz2 | |
fixes to memory ordering and csr diagrams
Diffstat (limited to 'src')
| -rw-r--r-- | src/images/wavedrom/csr-instr.adoc | 22 | ||||
| -rw-r--r-- | src/images/wavedrom/mem_order.adoc | 2 | ||||
| -rw-r--r-- | src/riscv-isa-unpr-conv-review.pdf | bin | 8394670 -> 8397961 bytes |
3 files changed, 12 insertions, 12 deletions
diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.adoc index 27c973c..263a75c 100644 --- a/src/images/wavedrom/csr-instr.adoc +++ b/src/images/wavedrom/csr-instr.adoc @@ -4,21 +4,21 @@ [wavedrom, ,] .... {reg: [ - {bits: 7, name: 'opcode', attr: 'SYSTEM', type: 8}, - {bits: 5, name: 'rd', attr: 'dest', type: 2}, - {bits: 3, name: 'func3', attr: ['CSRRW', 'CSRRS', 'CSRRC'], type: 8}, - {bits: 5, name: 'rs1', attr: 'source', type: 4}, - {bits: 12, name: 'csr', attr: 'source/dest', type: 4}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM',], type: 8}, + {bits: 5, name: 'rd', attr: ['3', 'dest','dest', 'dest' ], type: 2}, + {bits: 3, name: 'func3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC'], type: 8}, + {bits: 5, name: 'rs1', attr: ['5', 'source','source','source',], type: 4}, + {bits: 12, name: 'csr', attr: ['12', 'source/dest','source/dest','source/dest'], type: 4}, ]} .... -[wavedrom, ,svg] +[wavedrom, ,] .... {reg: [ - {bits: 7, name: 'opcode', attr: 'SYSTEM', type: 8}, - {bits: 5, name: 'rd', attr: 'dest', type: 2}, - {bits: 3, name: 'func3', attr: ['CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8}, - {bits: 5, name: 'rs1', attr: 'uimm[4:0]', type: 3}, - {bits: 12, name: 'csr', attr: 'source/dest', type: 4}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'], type: 8}, + {bits: 5, name: 'rd', attr: ['3', 'dest','dest', 'dest' ], type: 2}, + {bits: 3, name: 'func3', attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8}, + {bits: 5, name: 'rs1', attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'], type: 3}, + {bits: 12, name: 'csr', attr: ['12', 'source/dest','source/dest','source/dest'], type: 4}, ]} .... diff --git a/src/images/wavedrom/mem_order.adoc b/src/images/wavedrom/mem_order.adoc index c7ac36d..4b2d35c 100644 --- a/src/images/wavedrom/mem_order.adoc +++ b/src/images/wavedrom/mem_order.adoc @@ -1,6 +1,6 @@ //## 2.7 Memory Ordering Instructions -[wavedrom, , ] +[wavedrom,mem-order ,] .... {reg: [ {bits: 7, name: 'opcode', attr: 'MISC-MEM', type: 8}, diff --git a/src/riscv-isa-unpr-conv-review.pdf b/src/riscv-isa-unpr-conv-review.pdf Binary files differindex ce37973..fc3adf4 100644 --- a/src/riscv-isa-unpr-conv-review.pdf +++ b/src/riscv-isa-unpr-conv-review.pdf |