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author | Andrew Waterman <andrew@sifive.com> | 2020-05-31 17:12:17 -0700 |
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committer | GitHub <noreply@github.com> | 2020-05-31 17:12:17 -0700 |
commit | a22c84f1147a230b32fbec7d578b3a71b2062cd4 (patch) | |
tree | 593b0d36c900b790ca7bcd5193146a7d5bc59db9 /src | |
parent | bfebfb11af3ae7646ced8a21bac78e6922b40ddb (diff) | |
parent | 83f346fdf4a12d82b7b7c698d06022a2cd68e7cd (diff) | |
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Merge pull request #525 from riscv/64-pmp-entries
Extend PMP scheme to support 64 regions
Diffstat (limited to 'src')
-rw-r--r-- | src/machine.tex | 73 | ||||
-rw-r--r-- | src/priv-csrs.tex | 5 | ||||
-rw-r--r-- | src/priv-preface.tex | 1 |
3 files changed, 51 insertions, 28 deletions
diff --git a/src/machine.tex b/src/machine.tex index 94c58f4..9e20ee5 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -3011,17 +3011,22 @@ PMP violations are always trapped precisely at the processor. PMP entries are described by an 8-bit configuration register and one MXLEN-bit address register. Some PMP settings additionally use the address register -associated with the preceding PMP entry. Up to 16 PMP entries are supported. -If any PMP entries are implemented, then all PMP CSRs must be implemented, -but all PMP CSR fields are \warl\ and may be hardwired to zero. PMP CSRs -are only accessible to M-mode. +associated with the preceding PMP entry. +Up to 64 PMP entries are supported. +Implementations may implement zero, 16, or 64 PMP CSRs. +All PMP CSR fields are \warl\ and may be hardwired to zero. +PMP CSRs are only accessible to M-mode. The PMP configuration registers are densely packed into CSRs to minimize -context-switch time. For RV32, four CSRs, {\tt pmpcfg0}--{\tt pmpcfg3}, hold -the configurations {\tt pmp0cfg}--{\tt pmp15cfg} for the 16 PMP entries, as -shown in Figure~\ref{pmpcfg-rv32}. For RV64, {\tt pmpcfg0} and {\tt pmpcfg2} -hold the configurations for the 16 PMP entries, as shown in -Figure~\ref{pmpcfg-rv64}, whereas {\tt pmpcfg1} and {\tt pmpcfg3} are illegal. +context-switch time. +For RV32, sixteen CSRs, {\tt pmpcfg0}--{\tt pmpcfg15}, hold the configurations +{\tt pmp0cfg}--{\tt pmp63cfg} for the 64 PMP entries, as shown in +Figure~\ref{pmpcfg-rv32}. +For RV64, eight even-numbered CSRs, +{\tt pmpcfg0}, {\tt pmpcfg2}, \ldots, {\tt pmpcfg14}, hold the configurations +for the 64 PMP entries, as shown in Figure~\ref{pmpcfg-rv64}. +For RV64, the odd-numbered configuration registers, +{\tt pmpcfg1}, {\tt pmpcfg3}, \ldots, {\tt pmpcfg15}, are illegal. \begin{commentary} RV64 systems use {\tt pmpcfg2}, rather than {\tt pmpcfg1}, to hold @@ -3058,28 +3063,19 @@ entries 8--11 appear in {\tt pmpcfg2}[31:0] for both RV32 and RV64. \tt pmpcfg1 \\ \cline{1-4} 8 & 8 & 8 & 8 & \\ +~ \\ +\multicolumn{4}{c}{\Huge\vdots} & \ \\ +~ \\ \instbitrange{31}{24} & \instbitrange{23}{16} & \instbitrange{15}{8} & \instbitrange{7}{0} & \\ \cline{1-4} -\multicolumn{1}{|c|}{pmp11cfg} & -\multicolumn{1}{c|}{pmp10cfg} & -\multicolumn{1}{c|}{pmp9cfg} & -\multicolumn{1}{c|}{pmp8cfg} & -\tt pmpcfg2 \\ -\cline{1-4} -8 & 8 & 8 & 8 & \\ -\instbitrange{31}{24} & -\instbitrange{23}{16} & -\instbitrange{15}{8} & -\instbitrange{7}{0} & \\ -\cline{1-4} -\multicolumn{1}{|c|}{pmp15cfg} & -\multicolumn{1}{c|}{pmp14cfg} & -\multicolumn{1}{c|}{pmp13cfg} & -\multicolumn{1}{c|}{pmp12cfg} & -\tt pmpcfg3 \\ +\multicolumn{1}{|c|}{pmp63cfg} & +\multicolumn{1}{c|}{pmp62cfg} & +\multicolumn{1}{c|}{pmp61cfg} & +\multicolumn{1}{c|}{pmp60cfg} & +\tt pmpcfg15 \\ \cline{1-4} 8 & 8 & 8 & 8 & \\ \end{tabular} @@ -3134,6 +3130,29 @@ entries 8--11 appear in {\tt pmpcfg2}[31:0] for both RV32 and RV64. \tt pmpcfg2 \\ \cline{1-8} 8 & 8 & 8 & 8 & 8 & 8 & 8 & 8 & \\ +~ \\ +\multicolumn{8}{c}{\Huge\vdots} & \ \\ +~ \\ +\instbitrange{63}{56} & +\instbitrange{55}{48} & +\instbitrange{47}{40} & +\instbitrange{39}{32} & +\instbitrange{31}{24} & +\instbitrange{23}{16} & +\instbitrange{15}{8} & +\instbitrange{7}{0} & \\ +\cline{1-8} +\multicolumn{1}{|c|}{pmp63cfg} & +\multicolumn{1}{c|}{pmp62cfg} & +\multicolumn{1}{c|}{pmp61cfg} & +\multicolumn{1}{c|}{pmp60cfg} & +\multicolumn{1}{c|}{pmp59cfg} & +\multicolumn{1}{c|}{pmp58cfg} & +\multicolumn{1}{c|}{pmp57cfg} & +\multicolumn{1}{c|}{pmp56cfg} & +\tt pmpcfg14 \\ +\cline{1-8} +8 & 8 & 8 & 8 & 8 & 8 & 8 & 8 & \\ \end{tabular} \end{center} } @@ -3142,7 +3161,7 @@ entries 8--11 appear in {\tt pmpcfg2}[31:0] for both RV32 and RV64. \label{pmpcfg-rv64} \end{figure} -The PMP address registers are CSRs named {\tt pmpaddr0}--{\tt pmpaddr15}. +The PMP address registers are CSRs named {\tt pmpaddr0}--{\tt pmpaddr63}. Each PMP address register encodes bits 33--2 of a 34-bit physical address for RV32, as shown in Figure~\ref{pmpaddr-rv32}. For RV64, each PMP address register encodes bits 55--2 of a 56-bit physical address, as shown in diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index fa6be96..3c7ed75 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -320,10 +320,13 @@ Number & Privilege & Name & Description \\ \tt 0x3A1 & MRW &\tt pmpcfg1 & Physical memory protection configuration, RV32 only. \\ \tt 0x3A2 & MRW &\tt pmpcfg2 & Physical memory protection configuration. \\ \tt 0x3A3 & MRW &\tt pmpcfg3 & Physical memory protection configuration, RV32 only. \\ +& & \multicolumn{1}{c|}{\vdots} & \ \\ +\tt 0x3AE & MRW &\tt pmpcfg14 & Physical memory protection configuration. \\ +\tt 0x3AF & MRW &\tt pmpcfg15 & Physical memory protection configuration, RV32 only. \\ \tt 0x3B0 & MRW &\tt pmpaddr0 & Physical memory protection address register. \\ \tt 0x3B1 & MRW &\tt pmpaddr1 & Physical memory protection address register. \\ & & \multicolumn{1}{c|}{\vdots} & \ \\ -\tt 0x3BF & MRW &\tt pmpaddr15 & Physical memory protection address register. \\ +\tt 0x3EF & MRW &\tt pmpaddr63 & Physical memory protection address register. \\ \hline \end{tabular} \end{center} diff --git a/src/priv-preface.tex b/src/priv-preface.tex index d19a758..19a2d63 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -42,6 +42,7 @@ portability problems in practice: \item Constrained the LR/SC reservation set size and shape when using page-based virtual memory. \item PMP reset values are now platform-defined. +\item An additional 48 optional PMP registers have been defined. \end{itemize} Additionally, the following compatible changes have been made since version |