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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-07 13:42:32 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-07 13:42:32 -0800 |
| commit | f3663bddccd838842154aed6db44d93dfc19d009 (patch) | |
| tree | 041400ca5b4dd0c852e50be0069d7eab8ca17dcd /src | |
| parent | 47ca7ce69c566b4c59923d87ce7c1875f4ff4b80 (diff) | |
| download | riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.zip riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.tar.gz riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.tar.bz2 | |
Tweaks suggested by Bill Huffman
Diffstat (limited to 'src')
| -rw-r--r-- | src/counters.tex | 2 | ||||
| -rw-r--r-- | src/f.tex | 2 | ||||
| -rw-r--r-- | src/riscv-spec.tex | 2 | ||||
| -rw-r--r-- | src/rv64.tex | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/counters.tex b/src/counters.tex index 1700f15..a22a541 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -137,7 +137,7 @@ instruction counter. The underlying 64-bit counter should never overflow in practice. The following code sequence will read a valid 64-bit cycle counter value into -{\tt x3}:{\tt x2}, even if the counter overflows between reading its upper +{\tt x3}:{\tt x2}, even if the counter overflows its lower half between reading its upper and lower halves. \begin{figure}[h!] @@ -95,7 +95,7 @@ control and status register (CSR). It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in Figure~\ref{fcsr}. -\begin{figure*} +\begin{figure*}[h] {\footnotesize \begin{center} \begin{tabular}{K@{}E@{}ccccc} diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex index 17bed0a..d68ef38 100644 --- a/src/riscv-spec.tex +++ b/src/riscv-spec.tex @@ -32,7 +32,7 @@ Arvind, Krste Asanovi\'{c}, Rimas Avi\v{z}ienis, Jacob Bachmeyer, Christopher F. Batten, Allen J. Baum, Alex Bradbury, Scott Beamer, Preston Briggs, Christopher Celio, Chuanhua Chang, David Chisnall, Paul Clayton, Palmer Dabbelt, Roger Espasa, Shaked Flur, Stefan Freudenberger, Jan Gray, Michael -Hamburg, John Hauser, David Horner, Bruce Hoult, Alexandre Joannou, +Hamburg, John Hauser, David Horner, Bruce Hoult, Bill Huffman, Alexandre Joannou, Olof Johansson, Ben Keller, Yunsup Lee, Paul Loewenstein, Daniel Lustig, Yatin Manerkar, Luc Maranget, Margaret Martonosi, Joseph Myers, Vijayanand Nagarajan, Rishiyur Nikhil, Jonas diff --git a/src/rv64.tex b/src/rv64.tex index d9bda29..ef51e62 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -110,7 +110,7 @@ signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with $imm[5] \neq 0$ are reserved. \begin{commentary} - Previously, SLLIW, SRLIW, and SRAIW with imm[5]=0 were defined to + Previously, SLLIW, SRLIW, and SRAIW with $imm[5] \neq 0$ were defined to cause illegal instruction exceptions, whereas now they are marked as reserved. This is a backwards-compatible change. \end{commentary} |