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| author | Kersten Richter <kersten@riscv.org> | 2024-06-11 08:04:52 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-11 08:04:52 -0500 |
| commit | 7df7cdc79e1a0623db6d98fda963f5d02dba389d (patch) | |
| tree | efc8e9b30bc51373c4fc474f93918a03654572e5 | |
| parent | 601d0f907dffd8fc97ca9bfa6eedf7f07be60cda (diff) | |
| parent | c575e53ec36c6b1afbd908fd646da8f4cdc66dd7 (diff) | |
| download | riscv-isa-manual-7df7cdc79e1a0623db6d98fda963f5d02dba389d.zip riscv-isa-manual-7df7cdc79e1a0623db6d98fda963f5d02dba389d.tar.gz riscv-isa-manual-7df7cdc79e1a0623db6d98fda963f5d02dba389d.tar.bz2 | |
Merge branch 'main' into kersten1-patch-2
| -rw-r--r-- | src/hypervisor.adoc | 13 | ||||
| -rw-r--r-- | src/machine.adoc | 7 | ||||
| -rw-r--r-- | src/priv-preface.adoc | 2 |
3 files changed, 15 insertions, 7 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 85cb67f..959af02 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -2061,6 +2061,19 @@ Because TSR and TVM in `mstatus` are intended to impact only S-mode (HS-mode), they are ignored for determining exceptions in VS-mode. ==== +Fields FS and VS in registers `sstatus` and `vsstatus` deviate from the usual +_HS-qualified_ rule. +If an instruction is prevented from executing because FS or VS is zero in +either `sstatus` or `vsstatus`, the exception raised is always an +illegal-instruction exception, never a virtual-instruction exception. + +[NOTE] +==== +Early implementations of the H extension treated FS and VS in `sstatus` and +`vsstatus` specially this way, and the behavior has been codified to maintain +compatibility for software. +==== + <<< [[HSyncExcPrio]] diff --git a/src/machine.adoc b/src/machine.adoc index 1b8c2ff..cd2159b 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1586,13 +1586,6 @@ include::images/bytefield/hpmevents.adoc[] The `mhpmcounters` are *WARL* registers that support up to 64 bits of precision on RV32 and RV64. -[NOTE] -==== -A future revision of this specification will define a mechanism to -generate an interrupt when a hardware performance monitor counter -overflows. -==== - When XLEN=32, reads of the `mcycle`, `minstret`, `mhpmcounter__n__`, and `mhpmevent__n__` CSRs return bits 31-0 of the corresponding register, and writes change only bits 31-0; reads of the `mcycleh`, `minstreth`, `mhpmcounter__n__h`, and `mhpmevent__n__h` diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index c9a6def..55d9db6 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -81,6 +81,8 @@ anticipated to cause software portability problems in practice: Additionally, the following compatible changes have been made to the Machine and Supervisor ISAs since version 1.12: +* Defined the `misa`.B field to reflect that the B extension has been +implemented. * Defined the `misa`.V field to reflect that the V extension has been implemented. * Defined the RV32-only `medelegh` and `hedelegh` CSRs. |