From ad0a305aea6aebda7e26e857886143bb38928f4c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 10 Jun 2024 14:39:52 -0700 Subject: add misa.B to preface --- src/priv-preface.adoc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index c9a6def..55d9db6 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -81,6 +81,8 @@ anticipated to cause software portability problems in practice: Additionally, the following compatible changes have been made to the Machine and Supervisor ISAs since version 1.12: +* Defined the `misa`.B field to reflect that the B extension has been +implemented. * Defined the `misa`.V field to reflect that the V extension has been implemented. * Defined the RV32-only `medelegh` and `hedelegh` CSRs. -- cgit v1.1 From e9704f3cff9e91277aca1045b37330a8f692deeb Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 10 Jun 2024 18:01:17 -0700 Subject: Add note that vsstatus.FS/VS deviate from the HS-qualified rule This isn't a change; it's just a repetition of the information in the vsstatus register section. --- src/hypervisor.adoc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 85cb67f..959af02 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -2061,6 +2061,19 @@ Because TSR and TVM in `mstatus` are intended to impact only S-mode (HS-mode), they are ignored for determining exceptions in VS-mode. ==== +Fields FS and VS in registers `sstatus` and `vsstatus` deviate from the usual +_HS-qualified_ rule. +If an instruction is prevented from executing because FS or VS is zero in +either `sstatus` or `vsstatus`, the exception raised is always an +illegal-instruction exception, never a virtual-instruction exception. + +[NOTE] +==== +Early implementations of the H extension treated FS and VS in `sstatus` and +`vsstatus` specially this way, and the behavior has been codified to maintain +compatibility for software. +==== + <<< [[HSyncExcPrio]] -- cgit v1.1 From c575e53ec36c6b1afbd908fd646da8f4cdc66dd7 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 10 Jun 2024 18:21:04 -0700 Subject: Remove outdated comment Resolves #1450 --- src/machine.adoc | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/machine.adoc b/src/machine.adoc index 1b8c2ff..cd2159b 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1586,13 +1586,6 @@ include::images/bytefield/hpmevents.adoc[] The `mhpmcounters` are *WARL* registers that support up to 64 bits of precision on RV32 and RV64. -[NOTE] -==== -A future revision of this specification will define a mechanism to -generate an interrupt when a hardware performance monitor counter -overflows. -==== - When XLEN=32, reads of the `mcycle`, `minstret`, `mhpmcounter__n__`, and `mhpmevent__n__` CSRs return bits 31-0 of the corresponding register, and writes change only bits 31-0; reads of the `mcycleh`, `minstreth`, `mhpmcounter__n__h`, and `mhpmevent__n__h` -- cgit v1.1