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| author | Andrew Waterman <andrew@sifive.com> | 2024-06-10 18:21:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-06-10 18:21:04 -0700 |
| commit | c575e53ec36c6b1afbd908fd646da8f4cdc66dd7 (patch) | |
| tree | 0c32125cab269bd1e3d11dc8b1ab259b7ccb36ca | |
| parent | e9704f3cff9e91277aca1045b37330a8f692deeb (diff) | |
| download | riscv-isa-manual-c575e53ec36c6b1afbd908fd646da8f4cdc66dd7.zip riscv-isa-manual-c575e53ec36c6b1afbd908fd646da8f4cdc66dd7.tar.gz riscv-isa-manual-c575e53ec36c6b1afbd908fd646da8f4cdc66dd7.tar.bz2 | |
Remove outdated comment
Resolves #1450
| -rw-r--r-- | src/machine.adoc | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/machine.adoc b/src/machine.adoc index 1b8c2ff..cd2159b 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1586,13 +1586,6 @@ include::images/bytefield/hpmevents.adoc[] The `mhpmcounters` are *WARL* registers that support up to 64 bits of precision on RV32 and RV64. -[NOTE] -==== -A future revision of this specification will define a mechanism to -generate an interrupt when a hardware performance monitor counter -overflows. -==== - When XLEN=32, reads of the `mcycle`, `minstret`, `mhpmcounter__n__`, and `mhpmevent__n__` CSRs return bits 31-0 of the corresponding register, and writes change only bits 31-0; reads of the `mcycleh`, `minstreth`, `mhpmcounter__n__h`, and `mhpmevent__n__h` |