riscv-tools/riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2023-05-01	Update OpenOCD cfg files to new syntax	Tim Newsome	3	-13/+13
	We were using a variety of deprecated commands. The driving force behind this was the new way to use `expr{}` as the old way no longer works with mainline OpenOCD.
2020-12-31	Make HiFiveUnleashed tests clean.	Tim Newsome	3	-0/+7
	HiFiveUnleashed-flash fails som address translation tests. Possibly that would be fixed when https://github.com/riscv/riscv-tests/pull/313 merges.
2020-03-18	Specify misa for HiFive Unleashed. (#259)	Tim Newsome	1	-0/+2
	This saves a few seconds every time I run any test.
2019-12-02	Use a small binary to set up HiFive Unleashed. (#221)	Tim Newsome	3	-10/+10
	This binary comes from https://github.com/timsifive/freedom-u540-c000-bootloader/tree/board_setup2, which will hopefully be accepted upstream.
2019-10-15	Add support to run all tests against HiFive Unleashed. (#212)	Tim Newsome	5	-0/+184
	* Parse inf/nan floats. * Enable mstatus.fs in SimpleF18Test Also accept "unable to fetch" message when FPRs aren't supported. * Add config files for HiFive Unleashed. * Add configs to flash HiFive Unleashed. All tests pass.
2018-11-14	Merge pull request #165 from riscv/flash	Tim Newsome	2	-0/+59
	Tweak debug tests to run out of flash.
2018-11-14	Cleanup and renamed test flag to invalid_memory_returns_zero	cgsfv	2	-2/+2

2018-11-13	Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix	cgsfv	2	-2/+4

2018-10-31	Add HiFive1-flash target configuration.	Tim Newsome	2	-0/+59

2018-09-13	Assert if HiFive1 program is too large.	Tim Newsome	1	-0/+2

2018-04-19	Delete E300Sim.pydebug-delete-sim	Megan Wachs	1	-17/+0
	This file is wrong (the .cfg file isn't right) and not used by anything.
2018-04-02	Use `gdb_report_register_access_error enable`	Tim Newsome	1	-0/+3

2018-03-01	Ensure an error when reading a non-existent CSR.	Tim Newsome	1	-0/+4

2018-02-07	Link scripts shouldn't be executable.	Tim Newsome	1	-0/+0

2017-08-28	Make pylint happy.	Tim Newsome	1	-1/+1

2017-08-28	WIP multicore testing.	Tim Newsome	2	-0/+4

2017-08-28	Make the debug tests aware of multicore.	Tim Newsome	5	-13/+28
	Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-10	Give these sim targets a chance of passing.	Tim Newsome	2	-3/+7
	Also make sure vsim.log makes it into the generated log file.
2017-06-26	Move target definition into individual files.	Tim Newsome	9	-0/+158
	Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.