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path: root/debug/targets/RISC-V/spike64-2.py
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2024-05-01[debug tests] increase remotetimeout for all spike-based targets (#553)Anatoly Parshintsev1-1/+1
Spike simulator is very demanding to CPU resources. This causes debug tests to sporadically fail on slower machines. Increasing of gdb's `remotetimeout` should get rid of such failures, unless we run the testsuite on a potato. The only downside is that if OpenOCD is broken, tests can run longer. However, I think this is the sacrifice we can make, since execution time is not affected if everything works as expected.
2023-07-17debug: Add support_unavailable_control property.Tim Newsome1-0/+1
2022-05-31Address pylint warnings. (#385)Tim Newsome1-2/+2
I'm running a newer version of pylint, and thus there are new warnings to be fixed. All very minor.
2021-10-05Remove slen. (#360)Tim Newsome1-11/+4
It's not an argument to spike anymore. Also switch testing the vector unit from multi-gdb to `-rtos hwthread`. This exposes a bug in OpenOCD (which is already fixed).
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome1-0/+1
2020-04-10Change slen to a value that spike supports. (#271)Tim Newsome1-1/+3
2020-02-14Add tests for vector register access (#244)Tim Newsome1-4/+5
* WIP * Add vector register smoketest. Also redo the gdb value parsing code to accommodate the more complicated way that vector registers look. * Test vector access a little more thoroughly. * Revert unnecessary changes.
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome1-1/+2
`make` now takes 31s, `make all` takes 1m53s. The new CheckMisa test ensures that the misa value specified in the configuration is correct.
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-1/+3
* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome1-1/+1
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome1-2/+4
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2018-12-31Add testing of run-test/idle cases.Tim Newsome1-1/+1
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome1-0/+1
Only works against spike, where I've implemented some custom debug registers to test against.
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome1-1/+1
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome1-1/+1
I need this for CompareSections to pass when I instrument spike to be really slow.
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome1-1/+1
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome1-1/+1
2017-08-28Increase remotetimeout for spike targets.Tim Newsome1-0/+1
On overloaded systems, when executing compare-sections, otherwise gdb might hit a timeout and the compare-sections code doesn't deal with it. (You get an error message complaining that 130 is not a valid hex digit.)
2017-08-28Make pylint happy.Tim Newsome1-1/+1
2017-08-28Make the debug tests aware of multicore.Tim Newsome1-0/+11
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.