riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-07-18	Merge pull request #878 from en-sc/en-sc/trigg-eq-check	Tim Newsome	2	-13/+44
2023-07-17	target/riscv: cleanup trigger setup	Evgeniy Naydanov	2	-13/+44
2023-07-17	Merge pull request #879 from riscv/power_dance3	Tim Newsome	3	-40/+103
2023-07-17	Merge pull request #871 from en-sc/en-sc/fix-mdx-err	Tim Newsome	5	-333/+488
2023-07-14	target/riscv: refactor read_memory_progbuf()	Evgeniy Naydanov	5	-333/+488
2023-07-14	target/riscv: dynamic allocate memory for hawindow	Mark Zhuang	1	-6/+15
2023-07-14	target/riscv: update some macro	Mark Zhuang	1	-4/+3
2023-07-12	target/riscv: Message when harts become available.	Tim Newsome	1	-0/+6
2023-07-12	target/breakpoints: Clear software breakpoints from available targets	Tim Newsome	1	-39/+93
2023-07-06	target/riscv: Fix typo in gdb_regno_cacheable() comment.	Tim Newsome	1	-1/+1
2023-07-06	rtos/hwthread: Call rtos_free_threadlist() again.	Tim Newsome	1	-0/+3
2023-07-06	Merge pull request #872 from aap-sc/aap-sc/smp_manipulation	Tim Newsome	1	-0/+3
2023-07-04	target/riscv: Fix the trigger writing sequence	Marek Vrbka	1	-16/+29
2023-07-03	[target/riscv] support for smp group manipulation	Parshintsev Anatoly	1	-0/+3
2023-06-29	Merge pull request #873 from eosea/bscan_tunnel_seg_fault_fix	Tim Newsome	1	-2/+4
2023-06-27	target/riscv: fix haltgroup_supported to info->haltgroup_supported	Mark Zhuang	1	-2/+1
2023-06-22	Add null pointer check before right shift for bscan tunneling.	eolson	1	-2/+4
2023-06-22	rtos/FreeRTOS: solve some conflicting usage of thread id. (#865)	Chao Du	1	-11/+17
2023-06-21	Merge pull request #868 from en-sc/en-sc/upstream-resume-err-2	Tim Newsome	2	-23/+23
2023-06-21	Merge pull request #857 from riscv/power_dance2	Tim Newsome	4	-32/+162
2023-06-21	target/riscv: resume only halted harts	Evgeniy Naydanov	2	-23/+23
2023-06-20	target/riscv: From tick(), set ebreak* if necessary.	Tim Newsome	1	-0/+74
2023-06-20	target/riscv: Track whether ebreak* is set.	Tim Newsome	1	-0/+19
2023-06-20	target/riscv: Add periodic tick() callback	Tim Newsome	2	-0/+15
2023-06-20	target/riscv: Add some event callbacks.	Tim Newsome	2	-0/+21
2023-06-20	target/riscv: Track whether halt groups are supported.	Tim Newsome	1	-1/+4
2023-06-20	target/riscv: Improve update_dcsr()->set_dcsr_ebreak()	Tim Newsome	1	-12/+15
2023-06-20	target/riscv: Tweak set_group().	Tim Newsome	1	-8/+13
2023-06-20	target/riscv: Add debug msg to reset_delays_wait	Tim Newsome	1	-0/+1
2023-06-20	target/riscv: Remove unused riscv013_on_halt function	Tim Newsome	3	-11/+0
2023-06-20	jtag/drivers/xds110: Initialize `written`	Tim Newsome	1	-1/+1
2023-06-15	target/riscv: Early exit magic sequence checks in riscv_semihosting	Tim Newsome	1	-21/+19
2023-06-14	rtos/FreeRTOS: pxCurrentTCB should be used for judgment. (#862)	Chao Du	1	-5/+5
2023-06-09	target/riscv: Remove unnecessary prototypes.	Tim Newsome	1	-10/+0
2023-06-08	Merge pull request #860 from riscv/examine_state	Tim Newsome	1	-3/+3
2023-06-07	target/riscv: set_dcsr_ebreak() while target->state is still changed	Tim Newsome	1	-3/+3
2023-06-07	target/riscv: add register cache flushing and invalidation to protobuf execut...	Marek Vrbka	1	-9/+12
2023-06-05	target/riscv: Select hart in update_dcsr()	Tim Newsome	1	-0/+3
2023-06-02	Merge pull request #854 from en-sc/en-sc/fix-regacc-running	Tim Newsome	1	-7/+8
2023-05-31	target/riscv: fix register access on running target	Evgeniy Naydanov	1	-7/+8
2023-05-26	target/riscv: Set dcsr.ebreak* during examine()	Tim Newsome	1	-16/+27
2023-05-26	target: poll() failure does not mean the target halted.	Tim Newsome	2	-11/+13
2023-05-26	target/riscv: Always clear progbuf cache in examine().	Tim Newsome	1	-3/+3
2023-05-26	target/riscv: Reset DTM when it reports an error.	Tim Newsome	1	-0/+3
2023-05-23	target/riscv: refactor register accesses	Evgeniy Naydanov	2	-170/+232
2023-05-22	target/riscv: improve register caching (prep_, cleanup_)	Evgeniy Naydanov	1	-87/+104
2023-05-22	target/riscv: improve register caching (riscv_write_register)	Evgeniy Naydanov	2	-66/+160
2023-05-22	target/riscv: use `riscv_reg_t` and `enum gbb_regno` consistently	Evgeniy Naydanov	3	-42/+52
2023-05-22	target/riscv: fix register cache flushing	Evgeniy Naydanov	1	-9/+22
2023-05-18	Merge pull request #847 from riscv/data1_cache	Tim Newsome	1	-0/+4