aboutsummaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)AuthorFilesLines
11 daystarget/riscv: select DMI IR on batch access.Evgeniy Naydanov1-0/+2
2024-06-10Merge pull request #1073 from en-sc/en-sc/abs-reg-batchEvgeniy Naydanov3-100/+308
2024-06-07Merge pull request #1044 from en-sc/en-sc/riscv-011-sep-reg-accEvgeniy Naydanov2-18/+102
2024-06-06target/riscv: write registers using batchEvgeniy Naydanov3-100/+308
2024-06-05Merge pull request #1075 from en-sc/en-sc/from_upstreamEvgeniy Naydanov32-224/+262
2024-06-04target/riscv: stop using register_get/set for 0.11 targetsEvgeniy Naydanov2-16/+102
2024-06-04Revert "Initialize all registers in examine"Evgeniy Naydanov1-2/+0
2024-06-04Merge pull request #1056 from aap-sc/aap-sc/no_hit_bit_statusAnatoly Parshintsev2-15/+90
2024-05-31riscv-013: Remove unused typedef slot_tremove-slot_t-from-riscv-013Jan Matyas1-6/+0
2024-05-30Merge up to 437dde701c13e707e5fd912ef6403e09052e4d9b from upstreamEvgeniy Naydanov32-224/+262
2024-05-28target/riscv: do not emit warnings when a non-existent CSR is hiddenParshintsev Anatoly1-1/+1
2024-05-28target/riscv: fix halt reason for targets that do not support hit bit on trig...Parshintsev Anatoly2-15/+90
2024-05-28Merge pull request #1033 from en-sc/en-sc/err-read-abs-argEvgeniy Naydanov3-80/+218
2024-05-26openocd: drop include of target_type.hAntonio Borneo16-41/+26
2024-05-26Fix build with clang even if it sets __GNUC__ to >= 4.4Bernhard Rosenkränzer2-2/+2
2024-05-26target/semihosting: Fix double free()Marc Schink1-3/+1
2024-05-26target/arm_tpiu_swo: Handle errors in pre/post-enable eventsMarc Schink1-5/+11
2024-05-26server/gdb: Use 'bool' data type where appropriateMarc Schink1-13/+13
2024-05-26target/arm_tpiu_swo: Fix division by zeroMarc Schink1-8/+24
2024-05-23target/riscv: read abstract args using batchEvgeniy Naydanov3-80/+218
2024-05-18Merge pull request #1061 from en-sc/en-sc/dm-resetEvgeniy Naydanov1-41/+81
2024-05-17Merge pull request #1029 from MrAlexei/add_decode_wp_rvcEvgeniy Naydanov1-30/+467
2024-05-15target/riscv: only `dmactive` can be written if `dmactive` is lowEvgeniy Naydanov1-41/+81
2024-05-11target/xtensa: avoid IHI for writes to non-executable memoryIan Thompson1-8/+81
2024-05-11gdb_server: enable keep-alive packets for qCRC packetParshintsev Anatoly1-0/+2
2024-05-11cortex_a: drop cortex_a_dap_write_memap_register_u32()Antonio Borneo1-52/+39
2024-05-11cortex_a: drop the command 'cache auto'Antonio Borneo6-47/+32
2024-05-11cortex_a: drop useless cache invalidate on mem writeAntonio Borneo3-26/+0
2024-05-07Merge pull request #1064 from en-sc/en-sc/from_upstreamEvgeniy Naydanov7-9/+445
2024-05-04ipdbg: fix double free of virtual-ir dataDaniel Anselmi1-7/+6
2024-05-04smp: fix SIGSEGV for "smp off" during target examineAntonio Borneo1-1/+1
2024-05-04target: cortex_a: fix regs invalidation when -defer-examineAntonio Borneo1-1/+1
2024-05-04target: aarch64: fix regs invalidation when -defer-examineAntonio Borneo1-1/+1
2024-05-04cortex_m: don't try to halt not-examined targetsAntonio Borneo1-0/+5
2024-05-04target/target: Add 'debug_reason' to current targetMarc Schink1-0/+7
2024-05-04target: cortex_m: fix display of DWT registersAntonio Borneo1-0/+1
2024-05-04jtag: linuxgpiod: minor alignment to coding styleAntonio Borneo1-9/+9
2024-05-02Merge pull request #1028 from en-sc/en-sc/busy-reset-batchEvgeniy Naydanov5-29/+45
2024-04-30Add functions to decode RVC load and store instructionsAleksey Lotosh1-30/+467
2024-04-27Merge pull request #1031 from aap-sc/aap-sc/hart_status_info_fixupEvgeniy Naydanov1-8/+31
2024-04-27Merge pull request #1055 from aap-sc/aap-sc/bp_unitializedEvgeniy Naydanov1-3/+7
2024-04-27Merge up to 04154af5d6cd5fe76a2583778379bdacb5aa6fb0 from upstreamEvgeniy Naydanov7-9/+445
2024-04-26target/riscv: reset delays during batch scansEvgeniy Naydanov5-29/+45
2024-04-26Merge pull request #1025 from en-sc/en-sc/dump-fieldEvgeniy Naydanov5-76/+49
2024-04-26Merge pull request #1046 from en-sc/en-sc/reg-rv011-segfault-propperEvgeniy Naydanov1-4/+4
2024-04-24fix confusing status messages during resumeParshintsev Anatoly1-8/+31
2024-04-24target/riscv: use breakpoint_hw_set/watchpoint_set to properly initialize bp/...Parshintsev Anatoly1-3/+7
2024-04-23target/riscv/riscv-011: pc and dpc should be cached at the same locationEvgeniy Naydanov1-2/+2
2024-04-20target/riscv/riscv-011.c: fix access to non-existent registerEvgeniy Naydanov1-4/+4
2024-04-19target/riscv: decode DMI scans in batch accessEvgeniy Naydanov5-76/+49