riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-04-28	target/riscv: Support VS-stage and G-stage address translation.hypervisor_translate	Tim Newsome	1	-5/+212
2023-04-25	target/riscv: Refactor to create riscv_effective_privilege_mode()	Tim Newsome	1	-7/+34
2023-04-25	target/riscv: Move some code from riscv_address_translate() to riscv_virt2phys()	Tim Newsome	1	-53/+55
2023-04-25	Comment pte_shift	Tim Newsome	1	-0/+1
2023-04-25	target/riscv: Add constants for vsatp, hgatp	Tim Newsome	2	-0/+5
2023-04-11	Merge pull request #835 from en-sc/en-sc/fix-err-resume	Tim Newsome	1	-2/+2
2023-04-11	Merge pull request #833 from zqb-all/read_log128	Tim Newsome	1	-31/+40
2023-04-10	target/riscv: Handle error code in resume_prep	Evgeniy Naydanov	1	-2/+2
2023-04-10	target/riscv: support log memory access128 for read	Mark Zhuang	1	-31/+40
2023-04-07	Merge pull request #823 from panciyan/riscv	Tim Newsome	1	-1/+1
2023-04-06	Merge pull request #821 from en-sc/en-sc/fix-reset-mharts	Tim Newsome	1	-91/+62
2023-04-06	Merge pull request #830 from zqb-all/csr_32bit	Tim Newsome	1	-2/+12
2023-04-05	Merge branch 'riscv' into hypervisor	Tim Newsome	8	-252/+232
2023-04-05	target/riscv: simplify reset	Evgeniy Naydanov	1	-91/+62
2023-04-05	Merge pull request #816 from riscv/from_upstream	Tim Newsome	8	-158/+132
2023-04-04	Merge pull request #819 from zqb-all/fix_size_assert	Tim Newsome	3	-90/+96
2023-04-03	target/riscv: set some csr size to 32	Mark Zhuang	1	-2/+12
2023-03-29	Merge pull request #824 from riscv/aia	Tim Newsome	1	-3/+3
2023-03-29	target/riscv: Set hypervisor bits.	Tim Newsome	2	-3/+9
2023-03-25	target/riscv: [NFC] rename variables named read/write	Mark Zhuang	3	-74/+54
2023-03-25	target/riscv: support log memory access128	Mark Zhuang	1	-18/+44
2023-03-24	target/riscv: Don't ignore maskmax for icount.	Tim Newsome	1	-1/+1
2023-03-24	target/riscv: AIA regs, check for H not V	Tim Newsome	1	-3/+3
2023-03-23	target/riscv: leaf PTE check PTE_W missing	panciyan	1	-1/+1
2023-03-20	Merge pull request #815 from riscv/s_aia	Tim Newsome	5	-96/+250
2023-03-16	Fix build.	Tim Newsome	3	-11/+10
2023-03-16	Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream	Tim Newsome	8	-150/+125
2023-03-16	Merge pull request #800 from en-sc/en-sc/try-all-trigs-in-maybe-add-trig	Tim Newsome	1	-185/+245
2023-03-16	Expose S?aia CSRs if they're on the target.	Tim Newsome	4	-3/+88
2023-03-16	Update encoding.h.	Tim Newsome	1	-93/+162
2023-03-15	Merge pull request #812 from XuHangHub/riscv	Tim Newsome	1	-5/+5
2023-03-15	Try all triggers in maybe_add_trigger_t2 and _t6	Evgeniy Naydanov	1	-185/+245
2023-03-12	target/riscv: fix the bug of using S2 register in read_memory_progbuf	Hang Xu	1	-5/+5
2023-03-10	target/riscv: Remove unused address_in variable.	Tim Newsome	1	-2/+1
2023-02-28	Merge commit 'd1b882f2c014258be5397067e45848fa5465b78b' into from_upstream	Tim Newsome	1	-5/+6
2023-02-16	Merge pull request #799 from riscv/icount	Tim Newsome	1	-15/+126
2023-02-15	target/riscv: hide_csrs configuration option (#787)	Anatoly Parshintsev	2	-0/+48
2023-02-15	Add command "exec_progbuf" (#795)	Jan Matyas	3	-9/+65
2023-02-15	Add `riscv icount` command.	Tim Newsome	1	-15/+126
2023-02-14	Merge pull request #794 from riscv/fix-fence-instruction	Tim Newsome	4	-7/+8
2023-02-10	Merge pull request #797 from riscv/Zve32	Tim Newsome	3	-39/+65
2023-02-10	Don't reuse a single riscv_program.	Tim Newsome	1	-5/+7
2023-02-10	If XLEN=64 and vsew=64 fails, fall back to vsew=32.	Tim Newsome	3	-27/+51
2023-02-10	CSR_MCOUNTEREN should not exist if U-mode is not supported	Parshintsev Anatoly	1	-0/+3
2023-02-08	Print out debug value after the assignment is made.	Tim Newsome	1	-1/+1
2023-02-08	Move yes_no_maybe_t into riscv.h.	Tim Newsome	2	-6/+6
2023-02-01	Fix opcode for the "fence" instruction	Jan Matyas	4	-7/+8
2023-01-10	target/riscv: added support for missing VCSR register	Parshintsev Anatoly	3	-0/+3
2023-01-04	Merge pull request #777 from riscv/itrigger	Tim Newsome	2	-22/+289
2023-01-03	target/riscv: Remove `riscv test_sba_config_reg` command. (#780)	Tim Newsome	3	-404/+0