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path: root/src/target/riscv/riscv.h
AgeCommit message (Expand)AuthorFilesLines
2020-04-20Cache accesses through riscv_[sg]et_register.Tim Newsome1-2/+4
2020-03-26Deal with vlenb being unreadable. (#458)Tim Newsome1-0/+1
2020-03-05Fix address translation when high bits are set. (#453)Tim Newsome1-0/+2
2020-02-20Give control over dcsr.ebreak[msu] bits. (#451)Tim Newsome1-0/+3
2020-02-14Add support for vector register access (#448)Tim Newsome1-0/+20
2019-12-10riscv: translate virtual address to physical address. (#425)Hsiangkai1-0/+16
2019-12-05Increase maximum number of harts (#429)bluew1-1/+1
2019-12-04Remove unused data structure. (#431)Tim Newsome1-5/+0
2019-11-22Fix memory access on some targets. (#428)Tim Newsome1-0/+1
2019-11-12BSCAN batch fix (#422)Greg Savin1-0/+10
2019-11-04Add support for 64-bit memory reads/writes (#419)Tim Newsome1-1/+1
2019-07-18Access memory through the scope of current privilege level (#386)Nils Wistoff1-0/+2
2019-06-10Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)Paul George1-0/+2
2019-05-09Simultaneous halt (#372)Tim Newsome1-8/+5
2019-04-23Support for driving RISC-V DM via Arty's own JTAG chain using BSCAN tunnel (#...Greg Savin1-0/+10
2019-04-03Support simultaneous resume using hasel (#364)Tim Newsome1-8/+14
2019-01-09Add 'riscv set_ir' command to set IR value for JTAG registers.Darius Rad1-3/+3
2019-01-08Add comment for reset_delays_wait.Tim Newsome1-4/+4
2018-12-04Add `riscv reset_delays` for testing.Tim Newsome1-0/+4
2018-08-31Merge remote-tracking branch 'origin/riscv' into sba_testssba_testsMegan Wachs1-0/+1
2018-08-29Merge branch 'riscv' into sba_testsTim Newsome1-11/+21
2018-08-29Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebaseMegan Wachs1-5/+13
2018-08-29Add command to expose custom registers (#293)Tim Newsome1-0/+5
2018-08-27Handle hardware watchpoints hit by RV32 loads and stores (#291)craigblackmore1-0/+1
2018-07-17Merge pull request #279 from riscv/work_areaTim Newsome1-3/+0
2018-07-16Use work area instead of riscv-specific configTim Newsome1-3/+0
2018-06-20Explain why reg_cache_values isn't per-hart.Tim Newsome1-1/+3
2018-06-12target/riscv: add semihosting supportLiviu Ionescu1-0/+3
2018-06-06Update debug defines to match specTim Newsome1-1/+1
2018-05-22Merge remote-tracking branch 'origin/trigger_enum' into riscv-complianceriscv-compliance-devMegan Wachs1-0/+2
2018-05-22Delay trigger enumeration until it's required.Tim Newsome1-0/+2
2018-04-30Merge branch 'riscv' into notice_resetTim Newsome1-3/+4
2018-04-24Code cleanup from feedback.Ryan Macdonald1-2/+0
2018-04-17Merge remote-tracking branch 'origin/notice_reset' into riscv-complianceMegan Wachs1-3/+4
2018-04-12Merge branch 'riscv' into riscv-complianceMegan Wachs1-8/+12
2018-04-11Added address alignment test, code fixups from reviewRyan Macdonald1-2/+2
2018-04-09Fix some build issuesRyan Macdonald1-1/+1
2018-04-09Change #ifdef SIM_ON to be a run-time argRyan Macdonald1-0/+2
2018-04-05Fixed more style issuesRyan Macdonald1-1/+1
2018-04-05Fixed build issuesRyan Macdonald1-1/+2
2018-04-05Checkpoint: finish debug of tests, working on hitting sbbusyerror caseRyan Macdonald1-1/+1
2018-04-04Initial commit of tests for SBA featureRyan Macdonald1-0/+3
2018-04-03Track misa per-hart even in -rtos modeTim Newsome1-3/+2
2018-03-27Don't rely on havereset when deasserting reset.Tim Newsome1-3/+0
2018-03-22Add set_supports_haveresetTim Newsome1-0/+3
2018-03-19Add `riscv set_prefer_sba`Tim Newsome1-0/+2
2018-03-16Propagate errors in more placesTim Newsome1-3/+4
2018-03-06Add riscv dmi_read/dmi_write commands.Tim Newsome1-0/+3
2018-02-27Add `authdata_read` and `authdata_write` commands.Tim Newsome1-0/+3
2018-02-07Handle resuming from a trigger...Tim Newsome1-5/+1
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