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AgeCommit message (Expand)AuthorFilesLines
2020-04-21Don't read registers that we know don't exist.regcacheTim Newsome1-0/+5
2020-04-20Fix whitespace.Tim Newsome1-2/+2
2020-04-20Cache accesses through riscv_[sg]et_register.Tim Newsome2-17/+70
2020-04-13Don't propagate failure to read satp in riscv_mmu() (#466)Tim Newsome1-3/+4
2020-04-10Expose FPRs as single and double for F and D. (#465)Tim Newsome1-1/+17
2020-03-27Document default values for some config options. (#461)Tim Newsome1-3/+4
2020-03-27Fix some clang static checker complaints. (#464)Tim Newsome1-1/+5
2020-03-26Deal with vlenb being unreadable. (#458)Tim Newsome3-3/+8
2020-03-18Update to 1.11 privileged spec. (#455)Tim Newsome1-261/+347
2020-03-05Fix address translation when high bits are set. (#453)Tim Newsome2-6/+23
2020-02-20Give control over dcsr.ebreak[msu] bits. (#451)Tim Newsome4-6/+72
2020-02-14Add support for vector register access (#448)Tim Newsome7-51/+1776
2020-01-27Complain about debug version before authentication. (#441)Tim Newsome1-3/+7
2020-01-13Handle DMI busy in sba write. (#437)Tim Newsome2-55/+54
2020-01-10Don't issue extra FENCE+FENCE.i for the current hart. (#439)Jan Matyas1-0/+4
2020-01-06Upcast mask value to work with 64-bit physical (#436)Tim Newsome1-3/+7
2019-12-31Fix bugs. Do not touch SATP if there is no MMU. (#435)Hsiangkai1-3/+5
2019-12-10riscv: translate virtual address to physical address. (#425)Hsiangkai3-0/+239
2019-12-05Increase maximum number of harts (#429)bluew1-1/+1
2019-12-04Remove unused data structure. (#431)Tim Newsome2-10/+1
2019-11-27Fixed write_memory_progbuf() on RV64. (#426)Jan Matyas1-1/+1
2019-11-22Fix memory access on some targets. (#428)Tim Newsome3-1/+34
2019-11-20Fix: Take into account progbuf writability. (#424)Jan Matyas1-2/+6
2019-11-12BSCAN batch fix (#422)Greg Savin5-45/+73
2019-11-04Add support for 64-bit memory reads/writes (#419)Tim Newsome5-52/+115
2019-10-23pmpcfg[13] only exist on RV32. (#416)Tim Newsome1-0/+2
2019-10-03The compliance test is poorly supported.Tim Newsome1-1/+5
2019-09-27Merge branch 'master' into from_upstreamTim Newsome1-20/+23
2019-09-24Perform SBA writes with batch transactions for improved performance. (#405)darius-bluespec3-18/+60
2019-09-09Fix flashing HiFive Unleashed (#402)Tim Newsome3-16/+39
2019-08-26Use only one hart to run algorithm. (#396)Tim Newsome2-11/+19
2019-08-19Adds support for RISCV Access Memory Abstract Commands (#394)dave-estes-syzexion1-6/+192
2019-07-26Properly detect errors in SBA reads. (#392)Tim Newsome1-19/+26
2019-07-18Access memory through the scope of current privilege level (#386)Nils Wistoff6-0/+137
2019-07-15Optimize reading a single byte/short/word. (#390)Tim Newsome1-4/+61
2019-07-15Write all ones to clear cmderr. (#389)Tim Newsome1-1/+1
2019-07-15Make resume order configurable. (#388)Tim Newsome1-7/+58
2019-07-09Redo fespi flash algorithm (#384)Tim Newsome1-0/+64
2019-07-08RV32E support (#387)Tim Newsome2-12/+31
2019-06-21Reduce abstract command execution by one scan. (#383)Tim Newsome1-37/+40
2019-06-20fix memory leak (#382)jhjung811-0/+1
2019-06-19Improve block read and checksum speed (#381)Tim Newsome3-14/+114
2019-06-14Set mstatus.FS to access FPU CSRs. (#380)Tim Newsome1-3/+12
2019-06-10Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)Paul George3-82/+150
2019-05-21Don't write sbcs while sbbusy is set. (#375)Tim Newsome1-9/+24
2019-05-20RISC-V: Make compliance tests more verbose (#366)Philipp Wagner1-2/+10
2019-05-20RISC-V compliance test: target must be examined (#367)Philipp Wagner1-0/+6
2019-05-16More helpful debug output. (#374)Tim Newsome1-1/+1
2019-05-14helper/command: change prototype of command_print/command_print_samelineAntonio Borneo1-2/+2
2019-05-09Simultaneous halt (#372)Tim Newsome3-170/+221
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