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path: root/src/target/riscv/riscv.c
AgeCommit message (Expand)AuthorFilesLines
2024-05-06Improved handling of unavailable hartsexamine_unavailable_harts_squashcgsfv1-14/+44
2024-01-26Revert "break from long loops on shutdown request"Evgeniy Naydanov1-6/+0
2024-01-25Merge pull request #997 from en-sc/en-sc/priv-accessJan Matyas1-9/+1
2024-01-24target/riscv: report info about target during `poll`Evgeniy Naydanov1-0/+8
2024-01-23target/riscv: move read redirection for `priv` to `riscv-013.c`Evgeniy Naydanov1-9/+1
2024-01-18Merge pull request #992 from en-sc/en-sc/remove-hart-countJan Matyas1-10/+0
2024-01-18Merge pull request #991 from en-sc/en-sc/dm-dmi-address-conversionJan Matyas1-108/+106
2024-01-16target/riscv: fix addressing in `dm_read`/`dm_wirte`Evgeniy Naydanov1-108/+106
2024-01-16target/riscv: remove `riscv_hart_count()`Evgeniy Naydanov1-10/+0
2024-01-09break from long loops on shutdown requestEvgeniy Naydanov1-0/+6
2023-12-22rename dbgbuf to progbufParshintsev Anatoly1-13/+13
2023-12-22introduce execution status for riscv_programParshintsev Anatoly1-2/+2
2023-11-17Merge pull request #963 from kr-sc/kr-sc/no-free-triggersTim Newsome1-1/+1
2023-11-16Merge pull request #958 from riscv/set_field_get_fieldTim Newsome1-4/+1
2023-11-16When an attempt to set watchpoint fails because there is no free triggers Ope...Kirill Radkin1-1/+1
2023-11-15target/riscv: Replace [sg]et_field macros with functions.Tim Newsome1-4/+1
2023-11-13Merge pull request #961 from en-sc/en-sc/coreid-target-riscvTim Newsome1-2/+2
2023-11-10Merge pull request #928 from AnastasiyaChernikova/triggersTim Newsome1-9/+140
2023-11-10target/riscv: clarify usage of `coreid`Evgeniy Naydanov1-2/+2
2023-11-09target/riscv: Replace watchpoint value mask comparison value with macro.Marek Vrbka1-4/+1
2023-11-07Merge pull request #954 from riscv/from_upstreamTim Newsome1-1/+1
2023-11-07Merge pull request #952 from MarekVCodasip/stop-caching-dpcTim Newsome1-2/+0
2023-11-07target/riscv: cache requests to trigger configurationAnastasiya Chernikova1-9/+140
2023-11-06Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' into from_upstreamTim Newsome1-1/+1
2023-11-03target/riscv: gdb_regno_name takes an enum.Tim Newsome1-1/+1
2023-11-03Merge pull request #896 from AnastasiyaChernikova/ac-sc2Tim Newsome1-463/+275
2023-11-03Merge pull request #947 from riscv/from_upstreamTim Newsome1-1/+1
2023-11-03target/riscv: Stop caching writes to DPCMarek Vrbka1-2/+0
2023-11-02target/riscv: Adding register tables to make register names consistentAnastasiya Chernikova1-463/+275
2023-10-30target/riscv: Fix memory access when MMU is enabled and address couldn't be t...Kirill Radkin1-19/+29
2023-10-27Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstreamTim Newsome1-1/+1
2023-10-24Merge pull request #941 from kr-sc/kr-sc/fix-hgatp-mode-upstreamTim Newsome1-1/+1
2023-10-23hgatp_mode in riscv_virt2phys_v defined by vsatp valueKirill Radkin1-1/+1
2023-10-20Revert "target/riscv: Reject size 2 soft breakpoints when C extension not sup...Tim Newsome1-8/+6
2023-10-16Merge pull request #929 from aap-sc/riscvTim Newsome1-17/+58
2023-10-11Merge pull request #917 from kr-sc/kr-sc/disable-triggers-optionTim Newsome1-44/+154
2023-10-07target/riscv: use cacheable read/write function to handle DCSRliangzhen1-0/+23
2023-10-06do not assume DTM version unless dtmcontrol is read successfullyParshintsev Anatoly1-17/+58
2023-10-02provide riscv-specific controls to disable triggers from beeing used for watc...Kirill Radkin1-44/+154
2023-09-29Merge pull request #918 from kr-sc/kr-sc/allow-to-query-status-dcsr-ebreakTim Newsome1-21/+43
2023-09-28Merge pull request #892 from en-sc/en-sc/register-printingTim Newsome1-1/+1
2023-09-26openocd does not allow to query status of dcsr.ebreak{u,s,m}Kirill Radkin1-21/+43
2023-09-22target/riscv: define register printersEvgeniy Naydanov1-1/+1
2023-09-13target/riscv: Don't assert in riscv013_get_register()Tim Newsome1-2/+5
2023-09-08Merge pull request #909 from en-sc/en-sc/cleanup-enumerate-triggersTim Newsome1-74/+122
2023-09-07target/riscv: cleanup riscv_enumerate_triggers()Evgeniy Naydanov1-74/+122
2023-09-04target/riscv: Reject size 2 soft breakpoints when C extension not supportedMarek Vrbka1-6/+8
2023-08-30Merge pull request #906 from MarekVCodasip/zero-no-cacheTim Newsome1-0/+3
2023-08-25target/riscv: Don't write to zero.Marek Vrbka1-0/+3
2023-08-23Merge pull request #904 from kr-sc/kr-sc/support-sv57Tim Newsome1-1/+36
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