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path: root/src/target/riscv/program.c
AgeCommit message (Expand)AuthorFilesLines
2020-02-14Add support for vector register access (#448)Tim Newsome1-1/+2
2019-11-04Add support for 64-bit memory reads/writes (#419)Tim Newsome1-0/+10
2019-07-18Access memory through the scope of current privilege level (#386)Nils Wistoff1-0/+12
2019-05-16More helpful debug output. (#374)Tim Newsome1-1/+1
2018-03-02Don't always error if a debug program failsTim Newsome1-1/+1
2018-01-08Propagate register read errors.Tim Newsome1-1/+3
2017-12-27Get rid of abort() calls.Tim Newsome1-2/+1
2017-12-26Conform to OpenOCD style guide.Tim Newsome1-4/+3
2017-12-19Fix register names.Tim Newsome1-4/+4
2017-10-23Remove unused functionality.Tim Newsome1-225/+0
2017-10-18Pay attention to impebreak.Tim Newsome1-3/+4
2017-10-18Remove unused functionality.Tim Newsome1-61/+2
2017-10-16Memtest{16,32} pass.Tim Newsome1-12/+7
2017-10-13At least some memory writes work.Tim Newsome1-10/+13
2017-10-12Register read/write might be working.Tim Newsome1-1/+2
2017-10-12WIP; doesn't work.Tim Newsome1-71/+0
2017-10-03target/riscv/program.c: fix clang warningLiviu Ionescu1-1/+5
2017-09-18Remove unnecessary abs().Tim Newsome1-1/+1
2017-09-14Add support for F extension.Tim Newsome1-4/+27
2017-08-15Add some keep_alive()s for use with slow targets.Tim Newsome1-0/+2
2017-06-16Tighten up debug output.Tim Newsome1-17/+14
2017-06-06%p already includes 0x (on gcc)Tim Newsome1-4/+4
2017-04-26Add 64-bit and multihart supportPalmer Dabbelt1-0/+491
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