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2024-06-14target/riscv: select DMI IR on batch access.Evgeniy Naydanov1-0/+2
Without the selection the TAP can be left in bypass. Change-Id: I79c6bf74802dc9c9475947d1787a3d0b797f3952 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-06-10Merge pull request #1073 from en-sc/en-sc/abs-reg-batchEvgeniy Naydanov3-100/+308
target/riscv: write registers using batch
2024-06-07Merge pull request #1044 from en-sc/en-sc/riscv-011-sep-reg-accEvgeniy Naydanov2-18/+102
target/riscv: stop using register_get/set for 0.11 targets
2024-06-06target/riscv: write registers using batchEvgeniy Naydanov3-100/+308
This allows to eliminate up to two DMI NOPs. Change-Id: I09a18bd896fce2392d1b65d4efb38b53e334a358 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-06-05Merge pull request #1075 from en-sc/en-sc/from_upstreamEvgeniy Naydanov38-244/+470
Merge up to 437dde701c13e707e5fd912ef6403e09052e4d9b from upstream
2024-06-04target/riscv: stop using register_get/set for 0.11 targetsEvgeniy Naydanov2-16/+102
Caching is somewhat handled in `riscv-011.c`. Handling it additionaly in `riscv.c` may cause problems. Sice there is no simulator that supports RISC-V Debug Specification v0.11, so it is not feaseable to automate testing. This commit separates 0.11 register accesses and unlocks further development in this area. Change-Id: I73ff17ef85106c4ababa38319f446f6c384a1750 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-06-04Revert "Initialize all registers in examine"Evgeniy Naydanov1-2/+0
This reverts commit 9d4df3420c51e75bcc1d6162fc9cc680d6fd2481. I believe the reasoning behind this workaround is no longer valid. Change-Id: Ie8705f75eb8ad7b72fc8ffcf39125be764cb43be
2024-06-04Merge pull request #1056 from aap-sc/aap-sc/no_hit_bit_statusAnatoly Parshintsev2-15/+90
target/riscv: fix halt reason for targets that do not support hit bit on triggers
2024-06-04Merge pull request #1077 from riscv-collab/remove-slot_t-from-riscv-013Evgeniy Naydanov1-6/+0
riscv-013: Remove unused typedef slot_t
2024-05-31riscv-013: Remove unused typedef slot_tremove-slot_t-from-riscv-013Jan Matyas1-6/+0
Code cleanup: "slot_t" is unused in riscv013 - remove it. Change-Id: I9d5a0cf8446a180b1d13a9ce2c86d904b946cf28 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2024-05-30Merge up to 437dde701c13e707e5fd912ef6403e09052e4d9b from upstreamEvgeniy Naydanov38-244/+470
Conflict in src/rtos/FreeRTOS.c due to fbea7d5d38d0dcbdd71cb574da9bd12c78b568cf -- resolved by replacing `target->type->name` with a call to `target_type_name()`. Change-Id: I56702c6133894458903de7a4d764903004aa8b86
2024-05-30Merge pull request #1072 from aap-sc/aap-sc/fix_warnings_on_hide_csrsEvgeniy Naydanov1-1/+1
target/riscv: do not emit warnings when a non-existent CSR is hidden
2024-05-28target/riscv: do not emit warnings when a non-existent CSR is hiddenParshintsev Anatoly1-1/+1
hide_csrs should not emit warnings on an attempt to hide non-exitents CSR. hide_csrs funcitonality is intended to be used for scenarios when we don`t want certain groups of registers to be available in GDB. Typically this is needed to simplify integration with various IDE. In such scenarious it may be impractical/unfeseable to figure out which register is present on a target. So reporting a situation when a user wants to hide a non-existent register creates way too much noise. This commit reduces severity of relevant debug message to LOG_TARGET_DEBUG
2024-05-28target/riscv: fix halt reason for targets that do not support hit bit on ↵Parshintsev Anatoly2-15/+90
triggers Before this patch the following behavior is observed on targets that do not support hit bit: ``` bp 0x80000004 4 hw resume 0x80000000 riscv.cpu halted due to watchpoint ``` This happens because the current implementation relies on the presence of hit bit way too much. While working on this patch few defects in hit bit-based trigger detection were discovered, added appropriate TODOs.
2024-05-28Merge pull request #1033 from en-sc/en-sc/err-read-abs-argEvgeniy Naydanov3-80/+218
target/riscv: read abstract args using batch
2024-05-26Documentation: fix warning "unbalanced square brackets"R. Diez1-1/+1
Change-Id: I17b716533f5c9371600f0d932bf9b81c95c349e7 Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8261 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-05-26Documentation: Fix 2 warnings "Underfull \hbox (badness 10000)"R. Diez1-3/+2
The link to product GW16042 was broken, so it has been reduced to the manufacturer's website, which fixes the warning as a side effect. The link to Raisonance RLink was broken, and the new one is shorter, which fixes the warning as a side effect. Change-Id: I4df9acf2d994d51cd8f375bdac6c803270029506 Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8264 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-05-26ChangeLog: fix warning "Wide character in print" from git2clR. Diez1-1/+6
Change-Id: Iaefd989413753fb59642c3887807abd6ddac4b53 Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8262 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2024-05-26configure.ac: show the dummy adapter in the configuration summaryR. Diez1-9/+15
The dummy adapter now uses the same config logic as most adapters. Its name has changed from "dummy port driver" to "Dummy Adapter". Change-Id: Ic9ee617aab1f54215835d4d8db03f6637b797082 Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de> Reviewed-on: https://review.openocd.org/c/openocd/+/7340 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-05-26openocd: drop include of target_type.hAntonio Borneo16-41/+26
Few files include target_type.h even if it is not needed. Drop the include. Other files access directly to target type's name instead of using the proper API target_type_name(). Use the API and drop the include. Change-Id: I86c0e0bbad51db93500c0efa27b7d6f1a67a02c2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8260 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-05-26Fix build with clang even if it sets __GNUC__ to >= 4.4Bernhard Rosenkränzer2-2/+2
clang doesn't support the gnu_printf attribute that OpenOCD uses if __GNUC__ and __GNUC_MINOR__ indicates gcc >= 4.4. Most clang builds set __GNUC__/__GNUC_MINOR__ to 4.2 for historical reasons, so they don't trigger this condition; however, some builds set it to something much higher to work around code using __GNUC__ to determine if a feature that does exist in clang (but not gcc 4.2) is available, causing OpenOCD to use attribute gnu_printf. The problem can be reproduced without a special clang build by adding -fgnuc-version=14.1 to CFLAGS. Change-Id: I3c0832d4201578b116c5214203f95b6153dad30e Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8258 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-05-26target/semihosting: Fix double free()Marc Schink1-3/+1
Do not free the service in 'connection_closed_handler' because it is free'd by the server infrastructure. Checkpatch-ignore: COMMIT_LOG_LONG_LINE This error was detected with valgrind: ==272468== Invalid free() / delete / delete[] / realloc() ==272468== at 0x484B27F: free (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so) ==272468== by 0x1F34C7: remove_service (server.c:374) ==272468== by 0x2ED3D5: semihosting_tcp_close_cnx (semihosting_common.c:1819) ==272468== by 0x2ED3D5: handle_common_semihosting_redirect_command (semihosting_common.c:1926) ==272468== by 0x1FC703: exec_command (command.c:520) ==272468== by 0x1FC703: jim_command_dispatch (command.c:931) ==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd) ==272468== by 0x1FFFFFFFFF: ??? ==272468== by 0x53ED09F: ??? ==272468== by 0x300000001: ??? ==272468== by 0x1FFEFFF7FF: ??? ==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd) ==272468== by 0x2: ??? ==272468== Address 0x5fff650 is 0 bytes inside a block of size 24 free'd ==272468== at 0x484B27F: free (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so) ==272468== by 0x2ECA42: semihosting_service_connection_closed_handler (semihosting_common.c:1807) ==272468== by 0x1F2E39: remove_connection.isra.0 (server.c:164) ==272468== by 0x1F349E: remove_connections (server.c:350) ==272468== by 0x1F349E: remove_service (server.c:364) ==272468== by 0x2ED3D5: semihosting_tcp_close_cnx (semihosting_common.c:1819) ==272468== by 0x2ED3D5: handle_common_semihosting_redirect_command (semihosting_common.c:1926) ==272468== by 0x1FC703: exec_command (command.c:520) ==272468== by 0x1FC703: jim_command_dispatch (command.c:931) ==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd) ==272468== by 0x1FFFFFFFFF: ??? ==272468== by 0x53ED09F: ??? ==272468== by 0x300000001: ??? ==272468== by 0x1FFEFFF7FF: ??? ==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd) ==272468== Block was alloc'd at ==272468== at 0x484DA83: calloc (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so) ==272468== by 0x2ED326: handle_common_semihosting_redirect_command (semihosting_common.c:1931) ==272468== by 0x1FC703: exec_command (command.c:520) ==272468== by 0x1FC703: jim_command_dispatch (command.c:931) ==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd) ==272468== by 0x1FFFFFFFFF: ??? ==272468== by 0x53ED09F: ??? ==272468== by 0x400000002: ??? ==272468== by 0x1FFEFFF7FF: ??? ==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd) ==272468== by 0x2: ??? ==272468== Change-Id: I3e5323f145a98d1ff9ea7d03f87ed96140f49a18 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8257 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-05-26tcl/target/nrf52: Configure trace port speedMarc Schink1-0/+20
Configure the TRACECONFIG.TRACEPORTSPEED register depending on the trace clock speed. Also catch invalid trace clock speeds. Change-Id: I1ece1cc59da539732d2d71f296fd55799c195387 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8256 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-05-26tcl/target/nrf52: Use 'error' instead of 'echo'Marc Schink1-6/+3
Use 'error' instead of 'echo' for error messages. Otherwise, capturing is always started, for example with an unsupported device. While at it, make the error messages more consistent and clear. Change-Id: I83c9abfb4514e6b638c4be14651e67f768af8bad Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8255 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: <post@frankplowman.com>
2024-05-26target/arm_tpiu_swo: Handle errors in pre/post-enable eventsMarc Schink1-5/+11
Currently, errors in pre/post-enable events are ignored and capturing is always started, even if necessary device configuration fails. This behaviour is confusing to users. Also, the TPIU must be disabled before re-configuration is possible. Start capturing and enable TPIU only if no errors in pre/post-enable events occurred. Change-Id: I422033e36ca006e38aa4504d491b7947def1237a Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8254 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-05-26server/gdb: Use 'bool' data type where appropriateMarc Schink1-13/+13
Change-Id: Ic23c5469334337963185b69fcabeedf70c2c7ae9 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8253 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-05-26target/arm_tpiu_swo: Fix division by zeroMarc Schink1-8/+24
When external capturing is configured (default), the SWO pin frequency is required. Enforce this to avoid a division by zero error. While at it, ensure that the 'out_filename' variable always contains a valid string. This saves a few checks and makes the code more clean and readable. Change-Id: If8c1dae9549dd10e2f21d5b896414d47edac9fc2 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8224 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-05-23target/riscv: read abstract args using batchEvgeniy Naydanov3-80/+218
This would elliminate the need for an extra nop in-between the two reads in case of a 64-bit register. Change-Id: I2cddc14f7f78181bbda5f931c4e2289cfb7a6674 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-05-18Merge pull request #1061 from en-sc/en-sc/dm-resetEvgeniy Naydanov1-41/+81
target/riscv: only `dmactive` can be written if `dmactive` is low
2024-05-17Merge pull request #1029 from MrAlexei/add_decode_wp_rvcEvgeniy Naydanov1-30/+467
Add functions to decode RVC load and store instructions for watchpoints
2024-05-15target/riscv: only `dmactive` can be written if `dmactive` is lowEvgeniy Naydanov1-41/+81
There was an error introduced by 8319eee9e1ffc601b94b4223958180b49f8b8188. According to RISC-V Debug Spec 1.0.0-rc1 [3.14.2. Debug Module Contro]: > 0 (inactive): The module’s state, including authentication mechanism, takes its reset values (the dmactive bit is the only bit which can be written to something other than its reset value). `dmactive` was written together with `hartsel` and `hasel` in 8319eee9e1ffc601b94b4223958180b49f8b8188. Change-Id: I11fba35cb87f8261c0a4a45e28b2813a5a086078 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-05-11target/xtensa: avoid IHI for writes to non-executable memoryIan Thompson1-8/+81
For MPU configs, determine memory access rights by probing protection TLB. Issuing IHI without execute permissions can trigger an exception. No new clang static analyzer warnings. Change-Id: Iea8eab5c2113df3f954285c3b9a79e96d41aa941 Signed-off-by: Ian Thompson <ianst@cadence.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8080 Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-05-11gdb_server: enable keep-alive packets for qCRC packetParshintsev Anatoly1-0/+2
Change-Id: Ia384179bb83ad6b70bf385cc9d575e9ec58f76c7 Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8227 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-05-11cortex_a: drop cortex_a_dap_write_memap_register_u32()Antonio Borneo1-52/+39
Historically, the function cortex_a_dap_write_memap_register_u32() was used to discriminate the register write in APB-AP CPU debug against the complex memory access in AHB-AP memory bus. It has no sense to keep the function and its comment. Plus, by forcing atomic write it impacts the debug performance. Drop it! A further rework to enqueue sequence of atomic writes is needed. Change-Id: I2f5e9015f0e27fa5a6d8337a1ae25e753e2e1d26 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8231 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins
2024-05-11cortex_a: drop the command 'cache auto'Antonio Borneo6-47/+32
The command 'cache auto' was introduced with commit cd440bd32a12 ("add armv7a_cache handlers") in 2015 to allow disabling the cache handling done automatically by OpenOCD. This was probably a way to test the cache handling when there were still the two independent accesses for APB-AP CPU debug and for AHB-AP memory bus. The handling of cache for cortex_a is robust and there is no more reason to disable it. The command 'cache auto' is not used in any upstream script. On target aarch64 this command has never been introduced as the cache is always handled automatically by OpenOCD. Drop the command 'cache auto' and add it in the deprecated list. Drop the flag 'auto_cache_enabled' by considering it as true. Rename the function 'armv7a_cache_auto_flush_all_data()' as 'armv7a_cache_flush_all_data()' and, while there, fix the error propagation in SMP case. Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8230 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2024-05-11cortex_a: drop useless cache invalidate on mem writeAntonio Borneo3-26/+0
The initial OpenOCD code for Cortex-A (ARMv7a) [1] was merged in 2009 but, due to lack of public documentation for ARMv7a, it was almost a simple copy/paste from the existing code for Cortex-M (ARMv7m). On Cortex-M the same AP provides access to both CPU debug and CPU memory. This feature is not present on ARMv7a. To still keep some communality with ARMv7m code, the change [2] splits the CPU debug access from the CPU memory access by using two independent AP; this is copied from the system architecture of TI OMAP3530 which provides to DAP a direct AHB-AP memory bus on AP#0, separated from AP#1 for the APB-AP CPU debug. But the direct memory access through the system bus breaks the coherency between memory and CPU caches, so change [3] added some cache invalidation to avoid issues. The code to allow ARMv7a CPU to really read/write in CPU memory was added by change [4] in 2011. Such still not optimized implementation was very slow, so it did not replace the access through the system bus. A selection through DAP's 'apsel" command was used to select between the two modes. Only in 2015, with change [5], the speed of CPU read/write was improved using the DCC_FAST_MODE. But the direct access to the memory through the system bus remained. Finally, with change [6] in 2018 the system bus access was dropped for good, as the new virtual target "mem_ap" could implement such access in a more clean way. Only memory access through CPU remained for ARMv7a. Nevertheless, a useless cache invalidation remained in the code, decreasing the speed of the write access. Drop the useless cache invalidate on CPU memory write and the associated comment, not anymore valid. Drop the now unused function armv7a_cache_auto_flush_on_write(). This provides a speedup of between 4 and 8, depending on adapter and JTAG/SWD speed. Link: [1] 7a93100c2dfe ("Add minimalist Cortex A8 file") Link: [2] 1d0b276c9f75 ("The rest of the Cortex-A8 support from Magnus: ...") Link: [3] d4e4d65d284f ("Cache invalidation when writing to memory") Link: [4] 05ab8bdb813a ("cortex_a9: implement read/write memory through APB-AP") Link: [5] 0228f8e8274d ("Cortex A: fix extra memory read and non-word sizes") Link: [6] fac9be64d944 ("target/cortex_a: remove buggy memory AP accesses") Change-Id: Ifa3c7ddf2698b2c87037fb48f783844034a7140e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8229 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2024-05-07Merge pull request #1064 from en-sc/en-sc/from_upstreamEvgeniy Naydanov11-13/+476
Merge up to 04154af5d6cd5fe76a2583778379bdacb5aa6fb0 from upstream
2024-05-04ipdbg: fix double free of virtual-ir dataDaniel Anselmi1-7/+6
Fix possible double free and possible memory leak while creating an ipdbg hub. Change-Id: I6254663c27c4f38d46008c4dbff11aa27b84f399 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/8085 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-05-04tcl/target: Add helpers for booting Xilinx ZynqMP from JTAGSean Anderson1-0/+134
Add some helpers for booting ZynqMPs over JTAG. Normally, the CSU ROM will load boot.bin from the boot medium. However, when booting from JTAG we have to do this ourselves. There are generally two parts to this. First, we need to load the PMU firmware. Xilinx's tools do this by attaching to the PMU (a Microblaze CPU) over JTAG. However, the TAP is undocumented and we don't have any microblaze support in-tree. So instead we do it the same way FSBL does it: - We ask the PMU to halt - We load the firmware into the PMU RAM - We ask the PMU to resume The second thing we need to do is start one of the APU cores. When an APU is released from reset, it starts executing at the value of its RVBARADDR. While we could load the APU firmware over the AXI target, it is faster to load it over the APU target. To do this, we put the APU into an infinite loop before halting it. As an aside, I chose to use the "APU" terminology as opposed to "core" to make it clear that these commands operate on the A53 cores and not the R5F cores. Typical usage of these commands could look something like targets uscale.axi boot_pmu /path/to/pmu-firmware.bin boot_apu /path/to/u-boot-spl.bin But of course there is always the option to call lower-level commands individually if your boot process is more unusual. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I816940c2022ccca0fabb489aa75d682edd0f6138 Reviewed-on: https://review.openocd.org/c/openocd/+/8133 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-05-04smp: fix SIGSEGV for "smp off" during target examineAntonio Borneo1-1/+1
The gdb subsystem is initialized after the first target examine, so the field struct target::gdb_service is NULL during examine. A command "smp off" in the examine event handler causes a SIGSEGV during OpenOCD startup. Check for pointer not NULL before dereferencing it. Change-Id: Id115e28be23a957fef1b97ab66d7273f0ea0dce4 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8216 Tested-by: jenkins
2024-05-04target: cortex_a: fix regs invalidation when -defer-examineAntonio Borneo1-1/+1
The code for cortex_a allocates the register cache during the very first examine of the target. To prevent a segmentation fault in assert_reset(), the call to register_cache_invalidate() is guarded by target_was_examined(). But for targets with -defer-examine, the target is set as not examined in handle_target_reset() just before entering in assert_reset(). This causes registers to not be invalidated while reset a target examined but with -defer-examine. Change the condition and invalidate the register cache if it has been already allocated. Change-Id: I81ae782ddce07431d5f2c1bea3e2f19dfcd6d1ce Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8215 Tested-by: jenkins
2024-05-04target: aarch64: fix regs invalidation when -defer-examineAntonio Borneo1-1/+1
The code for aarch64 allocates the register cache during the very first examine of the target. To prevent a segmentation fault in assert_reset(), the call to register_cache_invalidate() is guarded by target_was_examined(). But for targets with -defer-examine, the target is set as not examined in handle_target_reset() just before entering in assert_reset(). This causes registers to not be invalidated while reset a target examined but with -defer-examine. Change the condition and invalidate the register cache if it has been already allocated. Change-Id: Ie13abb0ae2cc28fc3295d678c4ad1691024eb7b8 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8214 Tested-by: jenkins
2024-05-04cortex_m: don't try to halt not-examined targetsAntonio Borneo1-0/+5
Prevent a segmentation fault by preventing to try to halt a target that has not been examined yet. Change-Id: I5d344e7fbdb5422f7c5e2c39bdd48cbc6c2a3e58 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8213 Tested-by: jenkins
2024-05-04target/target: Add 'debug_reason' to current targetMarc Schink2-0/+19
Change-Id: Ie35b13b3e06411b4866ffeada47b3262493dbf2e Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8021 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-05-04target: cortex_m: fix display of DWT registersAntonio Borneo1-0/+1
Commit 16b4b8cf5453 ("Cortex-M3: expose most DWT registers") added the DWT registers to the list of CPU registers. The commit message from 2009 reports the reason behind this odd mixing of CPU and DWT registers. This feature got broken in 2017 with the introduction of the field struct reg::exist and its further use in the code. As result, the command 'reg' on a target Cortex-M reports only the core registers and then the header line ===== Cortex-M DWT registers not anymore followed by the DWT registers. Fix it by tagging each DWT registers as existing. Change-Id: Iab026e7da8d6b8ba052514c3fd3b5cdfe301f330 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: b5964191f0d2 ("register: support non-existent registers") Reviewed-on: https://review.openocd.org/c/openocd/+/8198 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2024-05-04jtag: linuxgpiod: minor alignment to coding styleAntonio Borneo1-9/+9
Avoid double TAB in 'then' block by increasing indentation of the multi-line condition. Change-Id: I7f5a4437fe4f74228f1b0d98e5c5921af4fd36b8 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8200 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2024-05-04doc: style: report indentation of multi-line conditionAntonio Borneo1-0/+15
To help readability and discriminate the 'then' block from the multi-line condition, suggest to increase the indentation of the condition. Change-Id: I02e3834be3001e7ecf24349ad3cefe94b27b79c8 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8199 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2024-05-02Merge pull request #1028 from en-sc/en-sc/busy-reset-batchEvgeniy Naydanov5-29/+45
target/riscv: reset delays during batch scans
2024-04-30Add functions to decode RVC load and store instructionsAleksey Lotosh1-30/+467
For GDB to fully support hardware watchpoints, OpenOCD needs to tell GDB which data address has been hit. OpenOCD relies on a target-specific hit_watchpoint function to do this. If GDB is not given the address, it will not print the hit variable name or its old and new value. There does not seem to be a way for the hardware to tell us which trigger was hit (0.13 introduced the 'hit bit' but this is optional). Alternatively, we can decode the instruction at dpc and find out which memory address it accesses. This commit adds support for RVC (compressed) load and store instructions. Related to: https://github.com/riscv-collab/riscv-openocd/issues/688 https://github.com/riscv-collab/riscv-openocd/pull/291
2024-04-27Merge pull request #1031 from aap-sc/aap-sc/hart_status_info_fixupEvgeniy Naydanov1-8/+31
fix confusing status messages during resume
generated by cgit v1.1 at 2024-11-16 14:48:23 +0000