riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-08-07	When gdb_port is 0, don't increment it.gdb_next_port	Tim Newsome	2	-2/+9
2017-07-27	Merge pull request #86 from riscv/debug	Tim Newsome	2	-4/+55
2017-07-27	Display register numbers in a more usable format.	Tim Newsome	2	-4/+55
2017-07-26	Merge pull request #85 from riscv/print_port	Tim Newsome	1	-0/+6
2017-07-25	Print out which port OpenOCD is listening on.print_port	Tim Newsome	1	-0/+6
2017-07-16	Merge pull request #84 from riscv/reset	Tim Newsome	1	-2/+23
2017-07-16	Use a wall clock timeout to complete reset.	Tim Newsome	1	-5/+9
2017-07-14	Fix infinite loop in reset.	Tim Newsome	1	-1/+18
2017-07-13	Merge pull request #83 from riscv/triggers	Tim Newsome	4	-643/+359
2017-07-12	Share trigger code between 0.11 and 0.13 code.	Tim Newsome	4	-643/+359
2017-07-12	Merge pull request #82 from riscv/comment	Tim Newsome	1	-0/+3
2017-07-12	Forgot to commit this follow up to PR #79	Tim Newsome	1	-0/+3
2017-07-12	Merge pull request #79 from riscv/abstract_regs	Tim Newsome	1	-99/+287
2017-07-12	Keep around cmderr for callers to inspect.	Tim Newsome	1	-26/+39
2017-07-12	Try abstract register writes as well.	Tim Newsome	1	-55/+133
2017-07-12	Try using abstract commands to read registers	Tim Newsome	1	-62/+159
2017-07-11	Merge pull request #80 from riscv/triggers	Tim Newsome	4	-82/+135
2017-07-10	Merge pull request #81 from riscv/llp64	Palmer Dabbelt	1	-27/+27
2017-07-10	Use LL for 64-bit defines, as Windows is LLP64	Palmer Dabbelt	1	-27/+27
2017-07-10	Disable debugger-set triggers on connect	Tim Newsome	4	-82/+135
2017-07-06	Merge pull request #78 from riscv/build32	Tim Newsome	2	-1/+14
2017-07-06	Fix 32-bit build.build32	Tim Newsome	1	-1/+1
2017-07-06	Build 32- and 64-bit binaries with Travis.	Tim Newsome	1	-0/+13
2017-07-06	Merge pull request #74 from riscv/build32	Tim Newsome	3	-7/+10
2017-07-06	Merge pull request #77 from riscv/travis	Tim Newsome	1	-0/+5
2017-07-05	Perform regular build with travis.	Tim Newsome	1	-0/+5
2017-07-03	Merge pull request #73 from riscv/old_triggers	Tim Newsome	1	-44/+130
2017-07-03	Merge pull request #69 from riscv/multi-gdb	Palmer Dabbelt	3	-43/+66
2017-07-03	Merge pull request #72 from dmitryryzhov/examine_restore_temp_reg	Palmer Dabbelt	1	-0/+12
2017-07-03	Fix 32-bit build errors.	Tim Newsome	3	-7/+10
2017-07-03	Fix trigger set/clear bug.	Tim Newsome	1	-2/+2
2017-07-03	Add back support for type 1 triggers.old_triggers	Tim Newsome	1	-42/+120
2017-07-01	Fix comment about saving the temporary register in examine procedure.	Dmitry Ryzhov	1	-2/+6
2017-06-30	Restore value of temporary register (s0) in examine OpenOCD procedure in case...	Dmitry Ryzhov	1	-0/+8
2017-06-27	Check for errors in read_csr().	Tim Newsome	1	-2/+10
2017-06-21	Don't set breakpoints on disabled hartsv20170621	Palmer Dabbelt	1	-0/+6
2017-06-21	No longer hard-code the non-RTOS hart to 0	Palmer Dabbelt	1	-3/+4
2017-06-21	Allow memory writes to proceed on all harts	Palmer Dabbelt	1	-6/+0
2017-06-21	Refactor examine, to avoid some assertions	Palmer Dabbelt	1	-9/+16
2017-06-21	Factor out checking if harts should be used	Palmer Dabbelt	3	-18/+35
2017-06-20	Set current_hartid from coreid	Palmer Dabbelt	3	-7/+5
2017-06-20	Merge pull request #68 from riscv/multicore	Palmer Dabbelt	4	-38/+89
2017-06-20	Set hardware triggers on all harts.multicore	Tim Newsome	1	-33/+69
2017-06-20	Don't immediately segfault with -rtos on v0.11.	Tim Newsome	1	-0/+3
2017-06-20	Comment curious code.	Tim Newsome	1	-0/+4
2017-06-20	Update list of "threads" when harts are discovered.	Tim Newsome	3	-5/+13
2017-06-20	Merge pull request #67 from riscv/cosmetics	Tim Newsome	3	-77/+147
2017-06-19	Put early DEBUG notice of XLEN back.	Tim Newsome	1	-0/+5
2017-06-16	Update debug_defines. Clarify debug output.	Tim Newsome	2	-52/+118
2017-06-16	Fix comment.	Tim Newsome	1	-1/+1