aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2017-07-25Print out which port OpenOCD is listening on.print_portTim Newsome1-0/+6
2017-07-16Merge pull request #84 from riscv/resetTim Newsome1-2/+23
2017-07-16Use a wall clock timeout to complete reset.Tim Newsome1-5/+9
2017-07-14Fix infinite loop in reset.Tim Newsome1-1/+18
2017-07-13Merge pull request #83 from riscv/triggersTim Newsome4-643/+359
2017-07-12Share trigger code between 0.11 and 0.13 code.Tim Newsome4-643/+359
2017-07-12Merge pull request #82 from riscv/commentTim Newsome1-0/+3
2017-07-12Forgot to commit this follow up to PR #79Tim Newsome1-0/+3
2017-07-12Merge pull request #79 from riscv/abstract_regsTim Newsome1-99/+287
2017-07-12Keep around cmderr for callers to inspect.Tim Newsome1-26/+39
2017-07-12Try abstract register writes as well.Tim Newsome1-55/+133
2017-07-12Try using abstract commands to read registersTim Newsome1-62/+159
2017-07-11Merge pull request #80 from riscv/triggersTim Newsome4-82/+135
2017-07-10Merge pull request #81 from riscv/llp64Palmer Dabbelt1-27/+27
2017-07-10Use LL for 64-bit defines, as Windows is LLP64Palmer Dabbelt1-27/+27
2017-07-10Disable debugger-set triggers on connectTim Newsome4-82/+135
2017-07-06Merge pull request #78 from riscv/build32Tim Newsome2-1/+14
2017-07-06Fix 32-bit build.build32Tim Newsome1-1/+1
2017-07-06Build 32- and 64-bit binaries with Travis.Tim Newsome1-0/+13
2017-07-06Merge pull request #74 from riscv/build32Tim Newsome3-7/+10
2017-07-06Merge pull request #77 from riscv/travisTim Newsome1-0/+5
2017-07-05Perform regular build with travis.Tim Newsome1-0/+5
2017-07-03Merge pull request #73 from riscv/old_triggersTim Newsome1-44/+130
2017-07-03Merge pull request #69 from riscv/multi-gdbPalmer Dabbelt3-43/+66
2017-07-03Merge pull request #72 from dmitryryzhov/examine_restore_temp_regPalmer Dabbelt1-0/+12
2017-07-03Fix 32-bit build errors.Tim Newsome3-7/+10
2017-07-03Fix trigger set/clear bug.Tim Newsome1-2/+2
2017-07-03Add back support for type 1 triggers.old_triggersTim Newsome1-42/+120
2017-07-01Fix comment about saving the temporary register in examine procedure.Dmitry Ryzhov1-2/+6
2017-06-30Restore value of temporary register (s0) in examine OpenOCD procedure in case...Dmitry Ryzhov1-0/+8
2017-06-27Check for errors in read_csr().Tim Newsome1-2/+10
2017-06-21Don't set breakpoints on disabled hartsv20170621Palmer Dabbelt1-0/+6
2017-06-21No longer hard-code the non-RTOS hart to 0Palmer Dabbelt1-3/+4
2017-06-21Allow memory writes to proceed on all hartsPalmer Dabbelt1-6/+0
2017-06-21Refactor examine, to avoid some assertionsPalmer Dabbelt1-9/+16
2017-06-21Factor out checking if harts should be usedPalmer Dabbelt3-18/+35
2017-06-20Set current_hartid from coreidPalmer Dabbelt3-7/+5
2017-06-20Merge pull request #68 from riscv/multicorePalmer Dabbelt4-38/+89
2017-06-20Set hardware triggers on all harts.multicoreTim Newsome1-33/+69
2017-06-20Don't immediately segfault with -rtos on v0.11.Tim Newsome1-0/+3
2017-06-20Comment curious code.Tim Newsome1-0/+4
2017-06-20Update list of "threads" when harts are discovered.Tim Newsome3-5/+13
2017-06-20Merge pull request #67 from riscv/cosmeticsTim Newsome3-77/+147
2017-06-19Put early DEBUG notice of XLEN back.Tim Newsome1-0/+5
2017-06-16Update debug_defines. Clarify debug output.Tim Newsome2-52/+118
2017-06-16Fix comment.Tim Newsome1-1/+1
2017-06-16Tell the user about detected harts.Tim Newsome1-8/+10
2017-06-16Tighten up debug output.Tim Newsome1-17/+14
2017-06-16Merge pull request #66 from riscv/whitespaceTim Newsome6-335/+333
2017-06-15Fix indentation to match OpenOCD style.Tim Newsome6-335/+333