diff options
Diffstat (limited to 'tcl/target')
221 files changed, 0 insertions, 12171 deletions
diff --git a/tcl/target/1986ве1т.cfg b/tcl/target/1986ве1т.cfg deleted file mode 100644 index 7b0c35f..0000000 --- a/tcl/target/1986ве1т.cfg +++ /dev/null @@ -1,63 +0,0 @@ -# 1986ВЕ1Т -# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=236&cntnt01returnid=68 - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME 1986ве1т -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x4ba00477 - } { - # SWD IDCODE - set _CPUTAPID 0x2ba01477 - } -} -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -# use AHB-Lite SRAM for work area -$_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# can't handle overlapping memory regions -if { [info exists IMEMORY] && [string equal $IMEMORY true] } { - flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 0 0 $_TARGETNAME 1 1 4 -} else { - flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 0 0 $_TARGETNAME 0 32 4 -} - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -adapter_khz 1000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg deleted file mode 100644 index fca0a7f..0000000 --- a/tcl/target/aduc702x.cfg +++ /dev/null @@ -1,53 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME aduc702x -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # This config file was defaulting to big endian.. - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x3f0f0f0f -} - -adapter_nsrst_delay 200 -jtag_ntrst_delay 200 - -## JTAG scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -## -## Target configuration -## -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - -# allocate the entire SRAM as working area -$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000 - -## flash configuration -# only target number is needed -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME - -## If you use the watchdog, the following code makes sure that the board -## doesn't reboot when halted via JTAG. Yes, on the older generation -## AdUC702x, timer3 continues running even when the CPU is halted. - -proc watchdog_service {} { - global watchdog_hdl - mww 0xffff036c 0 -# echo "watchdog!!" - set watchdog_hdl [after 500 watchdog_service] -} - -$_TARGETNAME configure -event reset-halt-post { watchdog_service } -$_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl } diff --git a/tcl/target/aducm360.cfg b/tcl/target/aducm360.cfg deleted file mode 100755 index 785c18c..0000000 --- a/tcl/target/aducm360.cfg +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file was created using as references the stm32f1x.cfg and aduc702x.cfg -# -source [find target/swj-dp.tcl] - -# Chip name -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME aducm360 -} - -# Endianess -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# Eventually, the whole SRAM of ADuCM360 will be used (8kB) -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x2000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x2ba01477 -} - -swd newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# SWD/JTAG speed -adapter_khz 1000 - -## -## Target configuration -## -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -# allocate the working area -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# flash size will be probed -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME - -adapter_nsrst_delay 100 - -cortex_m reset_config sysresetreq diff --git a/tcl/target/alphascale_asm9260t.cfg b/tcl/target/alphascale_asm9260t.cfg deleted file mode 100644 index 7892ea2..0000000 --- a/tcl/target/alphascale_asm9260t.cfg +++ /dev/null @@ -1,25 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $_CHIPNAME -} else { - set _CHIPNAME asm9260t -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x079264F3 -} - -# And srst_pulls_trst by chip design. -reset_config srst_pulls_trst - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg deleted file mode 100644 index 25fe1f4..0000000 --- a/tcl/target/altera_fpgasoc.cfg +++ /dev/null @@ -1,64 +0,0 @@ -# -# Altera cyclone V SoC family, 5Cxxx -# -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME fpgasoc -} - -# CoreSight Debug Access Port -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x4ba00477 -} - -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ - -expected-id $_DAP_TAPID - -# Subsidiary TAP: fpga -if { [info exists FPGA_TAPID] } { - set _FPGA_TAPID $FPGA_TAPID -} else { - set _FPGA_TAPID 0x02d020dd -} -jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID - - -# -# Cortex-A9 target -# - -# GDB target: Cortex-A9, using DAP, configuring only one core -# Base addresses of cores: -# core 0 - 0x80110000 -# core 1 - 0x80112000 - -# Slow speed to be sure it will work -adapter_khz 1000 - -set _TARGETNAME1 $_CHIPNAME.cpu.0 -set _TARGETNAME2 $_CHIPNAME.cpu.1 - -# A9 core 0 -target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \ - -coreid 0 -dbgbase 0x80110000 - -$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 } -$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1" -$_TARGETNAME1 configure -event gdb-attach { halt } - - -# A9 core 1 -#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \ -# -coreid 1 -dbgbase 0x80112000 - -#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 } -#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2" -#$_TARGETNAME2 configure -event gdb-attach { halt } - -proc cycv_dbginit {target} { - # General Cortex-A8/A9 debug initialisation - cortex_a dbginit -} diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg deleted file mode 100644 index 7409615..0000000 --- a/tcl/target/am335x.cfg +++ /dev/null @@ -1,78 +0,0 @@ -source [find target/icepick.cfg] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME am335x -} - -# set the taps to be enabled by default. this can be overridden -# by setting DEFAULT_TAPS in a separate configuration file -# or directly on the command line. -if { [info exists DEFAULT_TAPS] } { - set _DEFAULT_TAPS "$DEFAULT_TAPS" -} else { - set _DEFAULT_TAPS "$_CHIPNAME.dap" -} - -# -# Main DAP -# -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x4b6b902f -} -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0" - -# -# M3 DAP -# -if { [info exists M3_DAP_TAPID] } { - set _M3_DAP_TAPID $M3_DAP_TAPID -} else { - set _M3_DAP_TAPID 0x4b6b902f -} -jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable -jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0" - -# -# ICEpick-D (JTAG route controller) -# -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0b94402f -} -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version -jtag configure $_CHIPNAME.jrc -event setup { - global _DEFAULT_TAPS - enable_default_taps $_DEFAULT_TAPS -} -# some TCK tycles are required to activate the DEBUG power domain -jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" - -# -# helper function that enables all taps passed as argument -# -proc enable_default_taps { taps } { - foreach tap $taps { - jtag tapenable $tap - } -} - -# -# Cortex-M3 target -# -set _TARGETNAME_2 $_CHIPNAME.m3 -target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap - -# -# Cortex-A8 target -# -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000 - -# SRAM: 64K at 0x4030.0000; use the first 16K -$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000 diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg deleted file mode 100644 index fe0ffff..0000000 --- a/tcl/target/am437x.cfg +++ /dev/null @@ -1,999 +0,0 @@ -source [find target/icepick.cfg] -source [find mem_helper.tcl] - -############################################################################### -## AM437x Registers ## -############################################################################### -set PRCM_BASE_ADDR 0x44df0000 -set REVISION_PRM [expr $PRCM_BASE_ADDR + 0x0000] -set PRM_IRQSTATUS_MPU [expr $PRCM_BASE_ADDR + 0x0004] -set PRM_IRQENABLE_MPU [expr $PRCM_BASE_ADDR + 0x0008] -set PRM_IRQSTATUS_M3 [expr $PRCM_BASE_ADDR + 0x000c] -set PRM_IRQENABLE_M3 [expr $PRCM_BASE_ADDR + 0x0010] -set PM_MPU_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0300] -set PM_MPU_PWRSTST [expr $PRCM_BASE_ADDR + 0x0304] -set RM_MPU_RSTST [expr $PRCM_BASE_ADDR + 0x0314] -set RM_MPU_CONTEXT [expr $PRCM_BASE_ADDR + 0x0324] -set PM_GFX_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0400] -set PM_GFX_PWRSTST [expr $PRCM_BASE_ADDR + 0x0404] -set RM_GFX_RSTCTRL [expr $PRCM_BASE_ADDR + 0x0410] -set RM_GFX_RSTST [expr $PRCM_BASE_ADDR + 0x0414] -set RM_GFX_CONTEXT [expr $PRCM_BASE_ADDR + 0x0424] -set RM_RTC_CONTEXT [expr $PRCM_BASE_ADDR + 0x0524] -set RM_WKUP_RSTCTRL [expr $PRCM_BASE_ADDR + 0x2010] -set RM_WKUP_RSTST [expr $PRCM_BASE_ADDR + 0x2014] -set CM_L3_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2800] -set CM_WKUP_DEBUGSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2820] -set CM_L3S_TSC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2900] -set CM_WKUP_ADC_TSC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2920] -set CM_L4_WKUP_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2a00] -set CM_WKUP_L4WKUP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a20] -set CM_WKUP_WKUP_M3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a28] -set CM_WKUP_SYNCTIMER_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a30] -set CM_WKUP_CLKDIV32K_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a38] -set CM_WKUP_USBPHY0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a40] -set CM_WKUP_USBPHY1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a48] -set CM_WKUP_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2b00] -set CM_WKUP_TIMER0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b20] -set CM_WKUP_TIMER1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b28] -set CM_WKUP_WDT0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b30] -set CM_WKUP_WDT1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b38] -set CM_WKUP_I2C0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b40] -set CM_WKUP_UART0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b48] -set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b50] -set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b58] -set CM_WKUP_CONTROL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b60] -set CM_WKUP_GPIO0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b68] -set CM_CLKMODE_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d20] -set CM_IDLEST_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d24] -set CM_CLKSEL_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d2c] -set CM_DIV_M4_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d38] -set CM_DIV_M5_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d3c] -set CM_DIV_M6_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d40] -set CM_SSC_DELTAMSTEP_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d48] -set CM_SSC_MODFREQDIV_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d4c] -set CM_CLKMODE_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d60] -set CM_IDLEST_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d64] -set CM_CLKSEL_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d6c] -set CM_DIV_M2_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d70] -set CM_SSC_DELTAMSTEP_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d88] -set CM_SSC_MODFREQDIV_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d8c] -set CM_CLKMODE_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da0] -set CM_IDLEST_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da4] -set CM_CLKSEL_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dac] -set CM_DIV_M2_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db0] -set CM_DIV_M4_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db8] -set CM_SSC_DELTAMSTEP_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dc8] -set CM_SSC_MODFREQDIV_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dcc] -set CM_CLKMODE_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de0] -set CM_IDLEST_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de4] -set CM_CLKSEL_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2dec] -set CM_DIV_M2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2df0] -set CM_CLKSEL2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e04] -set CM_SSC_DELTAMSTEP_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e08] -set CM_SSC_MODFREQDIV_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e0c] -set CM_CLKDCOLDO_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e14] -set CM_CLKMODE_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e20] -set CM_IDLEST_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e24] -set CM_CLKSEL_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e2c] -set CM_DIV_M2_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e30] -set CM_SSC_DELTAMSTEP_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e48] -set CM_SSC_MODFREQDIV_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e4c] -set CM_CLKMODE_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e60] -set CM_IDLEST_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e64] -set CM_CLKSEL_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e6c] -set CM_DIV_M2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e70] -set CM_CLKSEL2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e84] -set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e88] -set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e8c] -set CM_SHADOW_FREQ_CONFIG1 [expr $PRCM_BASE_ADDR + 0x2fa0] -set CM_SHADOW_FREQ_CONFIG2 [expr $PRCM_BASE_ADDR + 0x2fa4] -set CM_CLKOUT1_CTRL [expr $PRCM_BASE_ADDR + 0x4100] -set CM_DLL_CTRL [expr $PRCM_BASE_ADDR + 0x4104] -set CM_CLKOUT2_CTRL [expr $PRCM_BASE_ADDR + 0x4108] -set CLKSEL_TIMER1MS_CLK [expr $PRCM_BASE_ADDR + 0x4200] -set CLKSEL_TIMER2_CLK [expr $PRCM_BASE_ADDR + 0x4204] -set CLKSEL_TIMER3_CLK [expr $PRCM_BASE_ADDR + 0x4208] -set CLKSEL_TIMER4_CLK [expr $PRCM_BASE_ADDR + 0x420c] -set CLKSEL_TIMER5_CLK [expr $PRCM_BASE_ADDR + 0x4210] -set CLKSEL_TIMER6_CLK [expr $PRCM_BASE_ADDR + 0x4214] -set CLKSEL_TIMER7_CLK [expr $PRCM_BASE_ADDR + 0x4218] -set CLKSEL_TIMER8_CLK [expr $PRCM_BASE_ADDR + 0x421c] -set CLKSEL_TIMER9_CLK [expr $PRCM_BASE_ADDR + 0x4220] -set CLKSEL_TIMER10_CLK [expr $PRCM_BASE_ADDR + 0x4224] -set CLKSEL_TIMER11_CLK [expr $PRCM_BASE_ADDR + 0x4228] -set CLKSEL_WDT1_CLK [expr $PRCM_BASE_ADDR + 0x422c] -set CLKSEL_SYNCTIMER_CLK [expr $PRCM_BASE_ADDR + 0x4230] -set CLKSEL_MAC_CLK [expr $PRCM_BASE_ADDR + 0x4234] -set CLKSEL_CPTS_RFT_CLK [expr $PRCM_BASE_ADDR + 0x4238] -set CLKSEL_GFX_FCLK [expr $PRCM_BASE_ADDR + 0x423c] -set CLKSEL_GPIO0_DBCLK [expr $PRCM_BASE_ADDR + 0x4240] -set CLKSEL_LCDC_PIXEL_CLK [expr $PRCM_BASE_ADDR + 0x4244] -set CLKSEL_ICSS_OCP_CLK [expr $PRCM_BASE_ADDR + 0x4248] -set CLKSEL_DLL_AGING_CLK [expr $PRCM_BASE_ADDR + 0x4250] -set CLKSEL_USBPHY32KHZ_GCLK [expr $PRCM_BASE_ADDR + 0x4260] -set CM_MPU_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8300] -set CM_MPU_MPU_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8320] -set CM_GFX_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8400] -set CM_GFX_GFX_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8420] -set CM_RTC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8500] -set CM_RTC_RTC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8520] -set CM_PER_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8800] -set CM_PER_L3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8820] -set CM_PER_AES0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8828] -set CM_PER_DES_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8830] -set CM_PER_CRYPTODMA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8838] -set CM_PER_L3_INSTR_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8840] -set CM_PER_MSTR_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8848] -set CM_PER_OCMCRAM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8850] -set CM_PER_SHA0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8858] -set CM_PER_SLV_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8860] -set CM_PER_VPFE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8868] -set CM_PER_VPFE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8870] -set CM_PER_TPCC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8878] -set CM_PER_TPTC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8880] -set CM_PER_TPTC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8888] -set CM_PER_TPTC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8890] -set CM_PER_DLL_AGING_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8898] -set CM_PER_L4HS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a0] -set CM_PER_L4FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a8] -set CM_PER_L3S_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8a00] -set CM_PER_GPMC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a20] -set CM_PER_IEEE5000_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a28] -set CM_PER_MCASP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a38] -set CM_PER_MCASP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a40] -set CM_PER_MMC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a48] -set CM_PER_QSPI_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a58] -set CM_PER_USB_OTG_SS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a60] -set CM_PER_USB_OTG_SS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a68] -set CM_PER_ICSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8b00] -set CM_PER_ICSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8b20] -set CM_PER_L4LS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8c00] -set CM_PER_L4LS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c20] -set CM_PER_DCAN0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c28] -set CM_PER_DCAN1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c30] -set CM_PER_EPWMSS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c38] -set CM_PER_EPWMSS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c40] -set CM_PER_EPWMSS2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c48] -set CM_PER_EPWMSS3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c50] -set CM_PER_EPWMSS4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c58] -set CM_PER_EPWMSS5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c60] -set CM_PER_ELM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c68] -set CM_PER_GPIO1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c78] -set CM_PER_GPIO2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c80] -set CM_PER_GPIO3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c88] -set CM_PER_GPIO4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c90] -set CM_PER_GPIO5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c98] -set CM_PER_HDQ1W_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca0] -set CM_PER_I2C1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca8] -set CM_PER_I2C2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb0] -set CM_PER_MAILBOX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb8] -set CM_PER_MMC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc0] -set CM_PER_MMC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc8] -set CM_PER_PKA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cd0] -set CM_PER_RNG_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce0] -set CM_PER_SPARE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce8] -set CM_PER_SPARE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cf0] -set CM_PER_SPI0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d00] -set CM_PER_SPI1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d08] -set CM_PER_SPI2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d10] -set CM_PER_SPI3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d18] -set CM_PER_SPI4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d20] -set CM_PER_SPINLOCK_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d28] -set CM_PER_TIMER2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d30] -set CM_PER_TIMER3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d38] -set CM_PER_TIMER4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d40] -set CM_PER_TIMER5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d48] -set CM_PER_TIMER6_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d50] -set CM_PER_TIMER7_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d58] -set CM_PER_TIMER8_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d60] -set CM_PER_TIMER9_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d68] -set CM_PER_TIMER10_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d70] -set CM_PER_TIMER11_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d78] -set CM_PER_UART1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d80] -set CM_PER_UART2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d88] -set CM_PER_UART3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d90] -set CM_PER_UART4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d98] -set CM_PER_UART5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8da0] -set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8db8] -set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8dc0] -set CM_PER_EMIF_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8f00] -set CM_PER_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f20] -set CM_PER_DLL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f28] -set CM_PER_EMIF_FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f30] -set CM_PER_OTFA_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f38] -set CM_PER_DSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9200] -set CM_PER_DSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9220] -set CM_PER_CPSW_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9300] -set CM_PER_CPGMAC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9320] -set CM_PER_OCPWP_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9400] -set CM_PER_OCPWP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9420] - -set CONTROL_BASE_ADDR 0x44e10000 -set CONTROL_STATUS [expr $CONTROL_BASE_ADDR + 0x0040] -set DEVICE_ID [expr $CONTROL_BASE_ADDR + 0x0600] -set DEV_FEATURE [expr $CONTROL_BASE_ADDR + 0x0604] -set DEV_ATTRIBUTE [expr $CONTROL_BASE_ADDR + 0x0610] -set MAC_ID0_LO [expr $CONTROL_BASE_ADDR + 0x0630] -set MAC_ID0_HI [expr $CONTROL_BASE_ADDR + 0x0634] -set MAC_ID1_LO [expr $CONTROL_BASE_ADDR + 0x0638] -set MAC_ID1_HI [expr $CONTROL_BASE_ADDR + 0x063c] -set USB_VID_PID [expr $CONTROL_BASE_ADDR + 0x07f4] -set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr $CONTROL_BASE_ADDR + 0x0964] -set CONTROL_CONF_SPI4_CS0 [expr $CONTROL_BASE_ADDR + 0x0a5c] -set CONTROL_CONF_SPI2_SCLK [expr $CONTROL_BASE_ADDR + 0x0a60] -set CONTROL_CONF_SPI2_D0 [expr $CONTROL_BASE_ADDR + 0x0a64] -set CONTROL_CONF_XDMA_EVENT_INTR0 [expr $CONTROL_BASE_ADDR + 0x0a70] -set CONTROL_CONF_XDMA_EVENT_INTR1 [expr $CONTROL_BASE_ADDR + 0x0a74] -set CONTROL_CONF_GPMC_A0 [expr $CONTROL_BASE_ADDR + 0x0840] -set DDR_IO_CTRL [expr $CONTROL_BASE_ADDR + 0x0e04] -set VTP_CTRL_REG [expr $CONTROL_BASE_ADDR + 0x0e0c] -set VREF_CTRL [expr $CONTROL_BASE_ADDR + 0x0e14] -set DDR_CKE_CTRL [expr $CONTROL_BASE_ADDR + 0x131c] -set DDR_ADDRCTRL_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1404] -set DDR_ADDRCTRL_WD0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1408] -set DDR_ADDRCTRL_WD1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x140c] -set DDR_DATA0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1440] -set DDR_DATA1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1444] -set DDR_DATA2_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1448] -set DDR_DATA3_IOCTRL [expr $CONTROL_BASE_ADDR + 0x144c] -set EMIF_SDRAM_CONFIG_EXT [expr $CONTROL_BASE_ADDR + 0x1460] -set EMIF_SDRAM_STATUS_EXT [expr $CONTROL_BASE_ADDR + 0x1464] - -set GPIO0_BASE_ADDR 0x44e07000 -set GPIO0_SYSCONFIG [expr $GPIO0_BASE_ADDR + 0x0010] -set GPIO0_SYSSTATUS [expr $GPIO0_BASE_ADDR + 0x0114] -set GPIO0_CTRL [expr $GPIO0_BASE_ADDR + 0x0130] -set GPIO0_OE [expr $GPIO0_BASE_ADDR + 0x0134] -set GPIO0_CLEARDATAOUT [expr $GPIO0_BASE_ADDR + 0x0190] -set GPIO0_SETDATAOUT [expr $GPIO0_BASE_ADDR + 0x0194] - -set GPIO5_BASE_ADDR 0x48322000 -set GPIO5_SYSCONFIG [expr $GPIO5_BASE_ADDR + 0x0010] -set GPIO5_SYSSTATUS [expr $GPIO5_BASE_ADDR + 0x0114] -set GPIO5_CTRL [expr $GPIO5_BASE_ADDR + 0x0130] -set GPIO5_OE [expr $GPIO5_BASE_ADDR + 0x0134] -set GPIO5_CLEARDATAOUT [expr $GPIO5_BASE_ADDR + 0x0190] -set GPIO5_SETDATAOUT [expr $GPIO5_BASE_ADDR + 0x0194] - -set GPIO1_BASE_ADDR 0x4804c000 -set GPIO1_SYSCONFIG [expr $GPIO1_BASE_ADDR + 0x0010] -set GPIO1_SYSSTATUS [expr $GPIO1_BASE_ADDR + 0x0114] -set GPIO1_CTRL [expr $GPIO1_BASE_ADDR + 0x0130] -set GPIO1_OE [expr $GPIO1_BASE_ADDR + 0x0134] -set GPIO1_CLEARDATAOUT [expr $GPIO1_BASE_ADDR + 0x0190] -set GPIO1_SETDATAOUT [expr $GPIO1_BASE_ADDR + 0x0194] - -set EMIF_BASE_ADDR 0x4c000000 -set EMIF_STATUS [expr $EMIF_BASE_ADDR + 0x0004] -set EMIF_SDRAM_CONFIG [expr $EMIF_BASE_ADDR + 0x0008] -set EMIF_SDRAM_CONFIG_2 [expr $EMIF_BASE_ADDR + 0x000c] -set EMIF_SDRAM_REF_CTRL [expr $EMIF_BASE_ADDR + 0x0010] -set EMIF_SDRAM_REF_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x0014] -set EMIF_SDRAM_TIM_1 [expr $EMIF_BASE_ADDR + 0x0018] -set EMIF_SDRAM_TIM_1_SHDW [expr $EMIF_BASE_ADDR + 0x001c] -set EMIF_SDRAM_TIM_2 [expr $EMIF_BASE_ADDR + 0x0020] -set EMIF_SDRAM_TIM_2_SHDW [expr $EMIF_BASE_ADDR + 0x0024] -set EMIF_SDRAM_TIM_3 [expr $EMIF_BASE_ADDR + 0x0028] -set EMIF_SDRAM_TIM_3_SHDW [expr $EMIF_BASE_ADDR + 0x002c] -set EMIF_LPDDR2_NVM_TIM [expr $EMIF_BASE_ADDR + 0x0030] -set EMIF_LPDDR2_NVM_TIM_SHDW [expr $EMIF_BASE_ADDR + 0x0034] -set EMIF_PWR_MGMT_CTRL [expr $EMIF_BASE_ADDR + 0x0038] -set EMIF_PWR_MGMT_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x003c] -set EMIF_LPDDR2_MODE_REG_DATA [expr $EMIF_BASE_ADDR + 0x0040] -set EMIF_LPDDR2_MODE_REG_CFG [expr $EMIF_BASE_ADDR + 0x0050] -set EMIF_OCP_CONFIG [expr $EMIF_BASE_ADDR + 0x0054] -set EMIF_OCP_CFG_VAL_1 [expr $EMIF_BASE_ADDR + 0x0058] -set EMIF_OCP_CFG_VAL_2 [expr $EMIF_BASE_ADDR + 0x005c] -set EMIF_IODFT_TLGC [expr $EMIF_BASE_ADDR + 0x0060] -set EMIF_IODFT_CTRL_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0064] -set EMIF_IODFT_ADDR_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0068] -set EMIF_IODFT_DATA_MISR_RSLT_1 [expr $EMIF_BASE_ADDR + 0x006c] -set EMIF_IODFT_DATA_MISR_RSLT_2 [expr $EMIF_BASE_ADDR + 0x0070] -set EMIF_IODFT_DATA_MISR_RSLT_3 [expr $EMIF_BASE_ADDR + 0x0074] -set EMIF_PERF_CNT_1 [expr $EMIF_BASE_ADDR + 0x0080] -set EMIF_PERF_CNT_2 [expr $EMIF_BASE_ADDR + 0x0084] -set EMIF_PERF_CNT_CFG [expr $EMIF_BASE_ADDR + 0x0088] -set EMIF_PERF_CNT_SEL [expr $EMIF_BASE_ADDR + 0x008c] -set EMIF_PERF_CNT_TIM [expr $EMIF_BASE_ADDR + 0x0090] -set EMIF_MISC_REG [expr $EMIF_BASE_ADDR + 0x0094] -set EMIF_DLL_CALIB_CTRL [expr $EMIF_BASE_ADDR + 0x0098] -set EMIF_DLL_CALIB_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x009c] -set EMIF_IRQ_EOI [expr $EMIF_BASE_ADDR + 0x00a0] -set EMIF_IRQSTATUS_RAW_SYS [expr $EMIF_BASE_ADDR + 0x00a4] -set EMIF_IRQSTATUS_SYS [expr $EMIF_BASE_ADDR + 0x00ac] -set EMIF_IRQENABLE_SET_SYS [expr $EMIF_BASE_ADDR + 0x00b4] -set EMIF_IRQENABLE_CLR_SYS [expr $EMIF_BASE_ADDR + 0x00bc] -set EMIF_ZQ_CONFIG [expr $EMIF_BASE_ADDR + 0x00c8] -set EMIF_TEMP_ALERT_CONFIG [expr $EMIF_BASE_ADDR + 0x00cc] -set EMIF_OCP_ERR_LOG [expr $EMIF_BASE_ADDR + 0x00d0] -set EMIF_RDWR_LVL_RMP_WIN [expr $EMIF_BASE_ADDR + 0x00d4] -set EMIF_RDWR_LVL_RMP_CTRL [expr $EMIF_BASE_ADDR + 0x00d8] -set EMIF_RDWR_LVL_CTRL [expr $EMIF_BASE_ADDR + 0x00dc] -set EMIF_DDR_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x00e4] -set EMIF_DDR_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x00e8] -set EMIF_DDR_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x00ec] -set EMIF_PRI_COS_MAP [expr $EMIF_BASE_ADDR + 0x0100] -set EMIF_CONNID_COS_1_MAP [expr $EMIF_BASE_ADDR + 0x0104] -set EMIF_CONNID_COS_2_MAP [expr $EMIF_BASE_ADDR + 0x0108] -set ECC_CTRL [expr $EMIF_BASE_ADDR + 0x0110] -set ECC_ADDR_RNG_1 [expr $EMIF_BASE_ADDR + 0x0114] -set ECC_ADDR_RNG_2 [expr $EMIF_BASE_ADDR + 0x0118] -set EMIF_RD_WR_EXEC_THRSH [expr $EMIF_BASE_ADDR + 0x0120] -set COS_CONFIG [expr $EMIF_BASE_ADDR + 0x0124] - -set PHY_STATUS_1 [expr $EMIF_BASE_ADDR + 0x0144] -set PHY_STATUS_2 [expr $EMIF_BASE_ADDR + 0x0148] -set PHY_STATUS_3 [expr $EMIF_BASE_ADDR + 0x014c] -set PHY_STATUS_4 [expr $EMIF_BASE_ADDR + 0x0150] -set PHY_STATUS_5 [expr $EMIF_BASE_ADDR + 0x0154] -set PHY_STATUS_6 [expr $EMIF_BASE_ADDR + 0x0158] -set PHY_STATUS_7 [expr $EMIF_BASE_ADDR + 0x015c] -set PHY_STATUS_8 [expr $EMIF_BASE_ADDR + 0x0160] -set PHY_STATUS_9 [expr $EMIF_BASE_ADDR + 0x0164] -set PHY_STATUS_10 [expr $EMIF_BASE_ADDR + 0x0168] -set PHY_STATUS_11 [expr $EMIF_BASE_ADDR + 0x016c] -set PHY_STATUS_12 [expr $EMIF_BASE_ADDR + 0x0170] -set PHY_STATUS_13 [expr $EMIF_BASE_ADDR + 0x0174] -set PHY_STATUS_14 [expr $EMIF_BASE_ADDR + 0x0178] -set PHY_STATUS_15 [expr $EMIF_BASE_ADDR + 0x017c] -set PHY_STATUS_16 [expr $EMIF_BASE_ADDR + 0x0180] -set PHY_STATUS_17 [expr $EMIF_BASE_ADDR + 0x0184] -set PHY_STATUS_18 [expr $EMIF_BASE_ADDR + 0x0188] -set PHY_STATUS_19 [expr $EMIF_BASE_ADDR + 0x018c] -set PHY_STATUS_20 [expr $EMIF_BASE_ADDR + 0x0190] -set PHY_STATUS_21 [expr $EMIF_BASE_ADDR + 0x0194] -set PHY_STATUS_22 [expr $EMIF_BASE_ADDR + 0x0198] -set PHY_STATUS_23 [expr $EMIF_BASE_ADDR + 0x019c] -set PHY_STATUS_24 [expr $EMIF_BASE_ADDR + 0x01a0] -set PHY_STATUS_25 [expr $EMIF_BASE_ADDR + 0x01a4] -set PHY_STATUS_26 [expr $EMIF_BASE_ADDR + 0x01a8] -set PHY_STATUS_27 [expr $EMIF_BASE_ADDR + 0x01ac] -set PHY_STATUS_28 [expr $EMIF_BASE_ADDR + 0x01b0] - -set EXT_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x0200] -set EXT_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x0204] -set EXT_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x0208] -set EXT_PHY_CTRL_2_SHDW [expr $EMIF_BASE_ADDR + 0x020c] -set EXT_PHY_CTRL_3 [expr $EMIF_BASE_ADDR + 0x0210] -set EXT_PHY_CTRL_3_SHDW [expr $EMIF_BASE_ADDR + 0x0214] -set EXT_PHY_CTRL_4 [expr $EMIF_BASE_ADDR + 0x0218] -set EXT_PHY_CTRL_4_SHDW [expr $EMIF_BASE_ADDR + 0x021c] -set EXT_PHY_CTRL_5 [expr $EMIF_BASE_ADDR + 0x0220] -set EXT_PHY_CTRL_5_SHDW [expr $EMIF_BASE_ADDR + 0x0224] -set EXT_PHY_CTRL_6 [expr $EMIF_BASE_ADDR + 0x0228] -set EXT_PHY_CTRL_6_SHDW [expr $EMIF_BASE_ADDR + 0x022c] -set EXT_PHY_CTRL_7 [expr $EMIF_BASE_ADDR + 0x0230] -set EXT_PHY_CTRL_7_SHDW [expr $EMIF_BASE_ADDR + 0x0234] -set EXT_PHY_CTRL_8 [expr $EMIF_BASE_ADDR + 0x0238] -set EXT_PHY_CTRL_8_SHDW [expr $EMIF_BASE_ADDR + 0x023c] -set EXT_PHY_CTRL_9 [expr $EMIF_BASE_ADDR + 0x0240] -set EXT_PHY_CTRL_9_SHDW [expr $EMIF_BASE_ADDR + 0x0244] -set EXT_PHY_CTRL_10 [expr $EMIF_BASE_ADDR + 0x0248] -set EXT_PHY_CTRL_10_SHDW [expr $EMIF_BASE_ADDR + 0x024c] -set EXT_PHY_CTRL_11 [expr $EMIF_BASE_ADDR + 0x0250] -set EXT_PHY_CTRL_11_SHDW [expr $EMIF_BASE_ADDR + 0x0254] -set EXT_PHY_CTRL_12 [expr $EMIF_BASE_ADDR + 0x0258] -set EXT_PHY_CTRL_12_SHDW [expr $EMIF_BASE_ADDR + 0x025c] -set EXT_PHY_CTRL_13 [expr $EMIF_BASE_ADDR + 0x0260] -set EXT_PHY_CTRL_13_SHDW [expr $EMIF_BASE_ADDR + 0x0264] -set EXT_PHY_CTRL_14 [expr $EMIF_BASE_ADDR + 0x0268] -set EXT_PHY_CTRL_14_SHDW [expr $EMIF_BASE_ADDR + 0x026c] -set EXT_PHY_CTRL_15 [expr $EMIF_BASE_ADDR + 0x0270] -set EXT_PHY_CTRL_15_SHDW [expr $EMIF_BASE_ADDR + 0x0274] -set EXT_PHY_CTRL_16 [expr $EMIF_BASE_ADDR + 0x0278] -set EXT_PHY_CTRL_16_SHDW [expr $EMIF_BASE_ADDR + 0x027c] -set EXT_PHY_CTRL_17 [expr $EMIF_BASE_ADDR + 0x0280] -set EXT_PHY_CTRL_17_SHDW [expr $EMIF_BASE_ADDR + 0x0284] -set EXT_PHY_CTRL_18 [expr $EMIF_BASE_ADDR + 0x0288] -set EXT_PHY_CTRL_18_SHDW [expr $EMIF_BASE_ADDR + 0x028c] -set EXT_PHY_CTRL_19 [expr $EMIF_BASE_ADDR + 0x0290] -set EXT_PHY_CTRL_19_SHDW [expr $EMIF_BASE_ADDR + 0x0294] -set EXT_PHY_CTRL_20 [expr $EMIF_BASE_ADDR + 0x0298] -set EXT_PHY_CTRL_20_SHDW [expr $EMIF_BASE_ADDR + 0x029c] -set EXT_PHY_CTRL_21 [expr $EMIF_BASE_ADDR + 0x02a0] -set EXT_PHY_CTRL_21_SHDW [expr $EMIF_BASE_ADDR + 0x02a4] -set EXT_PHY_CTRL_22 [expr $EMIF_BASE_ADDR + 0x02a8] -set EXT_PHY_CTRL_22_SHDW [expr $EMIF_BASE_ADDR + 0x02ac] -set EXT_PHY_CTRL_23 [expr $EMIF_BASE_ADDR + 0x02b0] -set EXT_PHY_CTRL_23_SHDW [expr $EMIF_BASE_ADDR + 0x02b4] -set EXT_PHY_CTRL_24 [expr $EMIF_BASE_ADDR + 0x02b8] -set EXT_PHY_CTRL_24_SHDW [expr $EMIF_BASE_ADDR + 0x02bc] -set EXT_PHY_CTRL_25 [expr $EMIF_BASE_ADDR + 0x02c0] -set EXT_PHY_CTRL_25_SHDW [expr $EMIF_BASE_ADDR + 0x02c4] -set EXT_PHY_CTRL_26 [expr $EMIF_BASE_ADDR + 0x02c8] -set EXT_PHY_CTRL_26_SHDW [expr $EMIF_BASE_ADDR + 0x02cc] -set EXT_PHY_CTRL_27 [expr $EMIF_BASE_ADDR + 0x02d0] -set EXT_PHY_CTRL_27_SHDW [expr $EMIF_BASE_ADDR + 0x02d4] -set EXT_PHY_CTRL_28 [expr $EMIF_BASE_ADDR + 0x02d8] -set EXT_PHY_CTRL_28_SHDW [expr $EMIF_BASE_ADDR + 0x02dc] -set EXT_PHY_CTRL_29 [expr $EMIF_BASE_ADDR + 0x02e0] -set EXT_PHY_CTRL_29_SHDW [expr $EMIF_BASE_ADDR + 0x02e4] -set EXT_PHY_CTRL_30 [expr $EMIF_BASE_ADDR + 0x02e8] -set EXT_PHY_CTRL_30_SHDW [expr $EMIF_BASE_ADDR + 0x02ec] -set EXT_PHY_CTRL_31 [expr $EMIF_BASE_ADDR + 0x02f0] -set EXT_PHY_CTRL_31_SHDW [expr $EMIF_BASE_ADDR + 0x02f4] -set EXT_PHY_CTRL_32 [expr $EMIF_BASE_ADDR + 0x02f8] -set EXT_PHY_CTRL_32_SHDW [expr $EMIF_BASE_ADDR + 0x02fc] -set EXT_PHY_CTRL_33 [expr $EMIF_BASE_ADDR + 0x0300] -set EXT_PHY_CTRL_33_SHDW [expr $EMIF_BASE_ADDR + 0x0304] -set EXT_PHY_CTRL_34 [expr $EMIF_BASE_ADDR + 0x0308] -set EXT_PHY_CTRL_34_SHDW [expr $EMIF_BASE_ADDR + 0x030c] -set EXT_PHY_CTRL_35 [expr $EMIF_BASE_ADDR + 0x0310] -set EXT_PHY_CTRL_35_SHDW [expr $EMIF_BASE_ADDR + 0x0314] -set EXT_PHY_CTRL_36 [expr $EMIF_BASE_ADDR + 0x0318] -set EXT_PHY_CTRL_36_SHDW [expr $EMIF_BASE_ADDR + 0x031c] - -set WDT1_BASE_ADDR 0x44e35000 -set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034] -set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048] - -set RTC_BASE_ADDR 0x44e3e000 -set RTC_KICK0R [expr $RTC_BASE_ADDR + 0x6c] -set RTC_KICK1R [expr $RTC_BASE_ADDR + 0x70] - - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME am437x -} - -set JRC_MODULE icepick_d -set DEBUGSS_MODULE debugss -set M3_MODULE m3_wakeupss - -set JRC_NAME $_CHIPNAME.$JRC_MODULE -set DEBUGSS_NAME $_CHIPNAME.$DEBUGSS_MODULE -set M3_NAME $_CHIPNAME.$M3_MODULE -set _TARGETNAME $_CHIPNAME.mpuss - -# -# M3 WakeupSS DAP -# -if { [info exists M3_DAP_TAPID] } { - set _M3_DAP_TAPID $M3_DAP_TAPID -} else { - set _M3_DAP_TAPID 0x4b6b902f -} -jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable -jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0" - -# -# DebugSS DAP -# -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x46b6902f -} -jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0" - -# -# ICEpick-D (JTAG route controller) -# -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0b98c02f -} -jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version -jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME" - # some TCK tycles are required to activate the DEBUG power domain -jtag configure $JRC_NAME -event post-reset "runtest 100" - -# -# Cortex-A9 target -# -target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000 - - -# SRAM: 256K at 0x4030.0000 -$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000 - -# Disables watchdog timer after reset otherwise board won't stay in -# halted state. -proc disable_watchdog { } { - global WDT1_WSPR - global WDT1_W_PEND_WSPR - global _TARGETNAME - - set curstate [$_TARGETNAME curstate] - - if { [string compare $curstate halted] == 0 } { - set WDT_DISABLE_SEQ1 0xaaaa - set WDT_DISABLE_SEQ2 0x5555 - - mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1 - - # Empty body to make sure this executes as fast as possible. - # We don't want any delays here otherwise romcode might start - # executing and end up changing state of certain IPs. - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } - - mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } - } -} - -proc ceil { x y } { - return [ expr ($x + $y - 1) / $y ] -} - -proc device_type { } { - global CONTROL_STATUS - - set tmp [ mrw $CONTROL_STATUS ] - set tmp [ expr $tmp & 0x700 ] - set tmp [ expr $tmp >> 8 ] - - return $tmp -} - -proc get_input_clock_frequency { } { - global CONTROL_STATUS - - if { [ device_type ] != 3 } { - error "Unknown device type\n" - return -1 - } - - set freq [ mrw $CONTROL_STATUS ] - set freq [ expr $freq & 0x00c00000 ] - set freq [ expr $freq >> 22 ] - - switch $freq { - 0 { - set CLKIN 19200000 - } - - 1 { - set CLKIN 24000000 - } - - 2 { - set CLKIN 25000000 - } - - 3 { - set CLKIN 26000000 - } - } - - return $CLKIN -} - -proc mpu_pll_config { CLKIN N M M2 } { - global CM_CLKMODE_DPLL_MPU - global CM_CLKSEL_DPLL_MPU - global CM_DIV_M2_DPLL_MPU - global CM_IDLEST_DPLL_MPU - - set clksel [ mrw $CM_CLKSEL_DPLL_MPU ] - set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ] - - mww $CM_CLKMODE_DPLL_MPU 0x4 - while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { } - - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] - mww $CM_CLKSEL_DPLL_MPU $clksel - - set div_m2 [ expr $div_m2 & (~0x1f) ] - set div_m2 [ expr $div_m2 | $M2 ] - mww $CM_DIV_M2_DPLL_MPU $div_m2 - - mww $CM_CLKMODE_DPLL_MPU 0x7 - while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { } - - echo "MPU DPLL locked" -} - -proc core_pll_config { CLKIN N M M4 M5 M6 } { - global CM_CLKMODE_DPLL_CORE - global CM_CLKSEL_DPLL_CORE - global CM_DIV_M4_DPLL_CORE - global CM_DIV_M5_DPLL_CORE - global CM_DIV_M6_DPLL_CORE - global CM_IDLEST_DPLL_CORE - - set clksel [ mrw $CM_CLKSEL_DPLL_CORE ] - - mww $CM_CLKMODE_DPLL_CORE 0x4 - while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { } - - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] - mww $CM_CLKSEL_DPLL_CORE $clksel - mww $CM_DIV_M4_DPLL_CORE $M4 - mww $CM_DIV_M5_DPLL_CORE $M5 - mww $CM_DIV_M6_DPLL_CORE $M6 - - mww $CM_CLKMODE_DPLL_CORE 0x7 - while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { } - - echo "CORE DPLL locked" -} - -proc per_pll_config { CLKIN N M M2 } { - global CM_CLKMODE_DPLL_PER - global CM_CLKSEL_DPLL_PER - global CM_DIV_M2_DPLL_PER - global CM_IDLEST_DPLL_PER - - set x [ expr $M * $CLKIN / 1000000 ] - set y [ expr ($N + 1) * 250 ] - set sd [ ceil $x $y ] - - set clksel [ mrw $CM_CLKSEL_DPLL_PER ] - set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ] - - mww $CM_CLKMODE_DPLL_PER 0x4 - while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { } - - set clksel [ expr $clksel & (~0xff0fffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] - set clksel [ expr $clksel | ($sd << 24) ] - mww $CM_CLKSEL_DPLL_PER $clksel - - set div_m2 [ expr 0xffffff80 | $M2 ] - - mww $CM_CLKMODE_DPLL_PER 0x7 - while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { } - - echo "PER DPLL locked" -} - -proc ddr_pll_config { CLKIN N M M2 M4 } { - global CM_CLKMODE_DPLL_DDR - global CM_CLKSEL_DPLL_DDR - global CM_DIV_M2_DPLL_DDR - global CM_DIV_M4_DPLL_DDR - global CM_IDLEST_DPLL_DDR - - set clksel [ mrw $CM_CLKSEL_DPLL_DDR ] - set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ] - - mww $CM_CLKMODE_DPLL_DDR 0x4 - while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { } - - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 8) | $N ] - mww $CM_CLKSEL_DPLL_DDR $clksel - - set div_m2 [ expr ($div_m2 & 0xffffffe0) | $M2 ] - mww $CM_DIV_M2_DPLL_DDR $div_m2 - mww $CM_DIV_M4_DPLL_DDR $M4 - - mww $CM_CLKMODE_DPLL_DDR 0x7 - while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { } - - echo "DDR DPLL Locked" -} - -proc config_opp100 { } { - set CLKIN [ get_input_clock_frequency ] - - if { $CLKIN == -1 } { - return -1 - } - - switch $CLKIN { - 24000000 { - mpu_pll_config $CLKIN 0 25 1 - core_pll_config $CLKIN 2 125 10 8 4 - per_pll_config $CLKIN 9 400 5 - ddr_pll_config $CLKIN 2 50 1 2 - } - - 25000000 { - mpu_pll_config $CLKIN 0 24 1 - core_pll_config $CLKIN 0 40 10 8 4 - per_pll_config $CLKIN 9 384 5 - ddr_pll_config $CLKIN 0 16 1 2 - } - - 26000000 { - mpu_pll_config $CLKIN 12 300 1 - core_pll_config $CLKIN 12 500 10 8 4 - per_pll_config $CLKIN 12 480 5 - ddr_pll_config $CLKIN 12 200 1 2 - } - - 19200000 { - mpu_pll_config $CLKIN 3 125 1 - core_pll_config $CLKIN 11 625 10 8 4 - per_pll_config $CLKIN 7 400 5 - ddr_pll_config $CLKIN 2 125 1 2 - } - } -} - -proc emif_prcm_clk_enable { } { - global CM_PER_EMIF_FW_CLKCTRL - global CM_PER_EMIF_CLKCTRL - - mww $CM_PER_EMIF_FW_CLKCTRL 0x02 - mww $CM_PER_EMIF_CLKCTRL 0x02 - - while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { } -} - -proc vtp_enable { } { - global VTP_CTRL_REG - - set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x40 ] - mww $VTP_CTRL_REG $vtp - - set vtp [ expr [ mrw $VTP_CTRL_REG ] & ~0x01 ] - mww $VTP_CTRL_REG $vtp - - set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x01 ] - mww $VTP_CTRL_REG $vtp - -} - -proc config_ddr_ioctrl { } { - global DDR_ADDRCTRL_IOCTRL - global DDR_ADDRCTRL_WD0_IOCTRL - global DDR_ADDRCTRL_WD1_IOCTRL - global DDR_CKE_CTRL - global DDR_DATA0_IOCTRL - global DDR_DATA1_IOCTRL - global DDR_DATA2_IOCTRL - global DDR_DATA3_IOCTRL - global DDR_IO_CTRL - - mww $DDR_ADDRCTRL_IOCTRL 0x84 - mww $DDR_ADDRCTRL_WD0_IOCTRL 0x00 - mww $DDR_ADDRCTRL_WD1_IOCTRL 0x00 - mww $DDR_DATA0_IOCTRL 0x84 - mww $DDR_DATA1_IOCTRL 0x84 - mww $DDR_DATA2_IOCTRL 0x84 - mww $DDR_DATA3_IOCTRL 0x84 - - mww $DDR_IO_CTRL 0x00 - mww $DDR_CKE_CTRL 0x03 -} - -proc config_ddr_phy { } { - global EMIF_DDR_PHY_CTRL_1 - global EMIF_DDR_PHY_CTRL_1_SHDW - - global EXT_PHY_CTRL_1 - global EXT_PHY_CTRL_1_SHDW - global EXT_PHY_CTRL_2 - global EXT_PHY_CTRL_2_SHDW - global EXT_PHY_CTRL_3 - global EXT_PHY_CTRL_3_SHDW - global EXT_PHY_CTRL_4 - global EXT_PHY_CTRL_4_SHDW - global EXT_PHY_CTRL_5 - global EXT_PHY_CTRL_5_SHDW - global EXT_PHY_CTRL_6 - global EXT_PHY_CTRL_6_SHDW - global EXT_PHY_CTRL_7 - global EXT_PHY_CTRL_7_SHDW - global EXT_PHY_CTRL_8 - global EXT_PHY_CTRL_8_SHDW - global EXT_PHY_CTRL_9 - global EXT_PHY_CTRL_9_SHDW - global EXT_PHY_CTRL_10 - global EXT_PHY_CTRL_10_SHDW - global EXT_PHY_CTRL_11 - global EXT_PHY_CTRL_11_SHDW - global EXT_PHY_CTRL_12 - global EXT_PHY_CTRL_12_SHDW - global EXT_PHY_CTRL_13 - global EXT_PHY_CTRL_13_SHDW - global EXT_PHY_CTRL_14 - global EXT_PHY_CTRL_14_SHDW - global EXT_PHY_CTRL_15 - global EXT_PHY_CTRL_15_SHDW - global EXT_PHY_CTRL_16 - global EXT_PHY_CTRL_16_SHDW - global EXT_PHY_CTRL_17 - global EXT_PHY_CTRL_17_SHDW - global EXT_PHY_CTRL_18 - global EXT_PHY_CTRL_18_SHDW - global EXT_PHY_CTRL_19 - global EXT_PHY_CTRL_19_SHDW - global EXT_PHY_CTRL_20 - global EXT_PHY_CTRL_20_SHDW - global EXT_PHY_CTRL_21 - global EXT_PHY_CTRL_21_SHDW - global EXT_PHY_CTRL_22 - global EXT_PHY_CTRL_22_SHDW - global EXT_PHY_CTRL_23 - global EXT_PHY_CTRL_23_SHDW - global EXT_PHY_CTRL_24 - global EXT_PHY_CTRL_24_SHDW - global EXT_PHY_CTRL_25 - global EXT_PHY_CTRL_25_SHDW - global EXT_PHY_CTRL_26 - global EXT_PHY_CTRL_26_SHDW - global EXT_PHY_CTRL_27 - global EXT_PHY_CTRL_27_SHDW - global EXT_PHY_CTRL_28 - global EXT_PHY_CTRL_28_SHDW - global EXT_PHY_CTRL_29 - global EXT_PHY_CTRL_29_SHDW - global EXT_PHY_CTRL_30 - global EXT_PHY_CTRL_30_SHDW - global EXT_PHY_CTRL_31 - global EXT_PHY_CTRL_31_SHDW - global EXT_PHY_CTRL_32 - global EXT_PHY_CTRL_32_SHDW - global EXT_PHY_CTRL_33 - global EXT_PHY_CTRL_33_SHDW - global EXT_PHY_CTRL_34 - global EXT_PHY_CTRL_34_SHDW - global EXT_PHY_CTRL_35 - global EXT_PHY_CTRL_35_SHDW - global EXT_PHY_CTRL_36 - global EXT_PHY_CTRL_36_SHDW - - mww $EMIF_DDR_PHY_CTRL_1 0x8009 - mww $EMIF_DDR_PHY_CTRL_1_SHDW 0x8009 - - set slave_ratio 0x80 - set gatelvl_init_ratio 0x20 - set wr_dqs_slave_delay 0x60 - set rd_dqs_slave_delay 0x60 - set dq_offset 0x40 - set gatelvl_init_mode 0x01 - set wr_data_slave_delay 0x80 - set gatelvl_num_dq0 0x0f - set wrlvl_num_dq0 0x0f - - mww $EXT_PHY_CTRL_1 [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ] - mww $EXT_PHY_CTRL_1_SHDW [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ] - mww $EXT_PHY_CTRL_26 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_26_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_27 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_27_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_28 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_28_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_29 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_29_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_30 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_30_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_31 0x00 - mww $EXT_PHY_CTRL_31_SHDW 0x00 - mww $EXT_PHY_CTRL_32 0x00 - mww $EXT_PHY_CTRL_32_SHDW 0x00 - mww $EXT_PHY_CTRL_33 0x00 - mww $EXT_PHY_CTRL_33_SHDW 0x00 - mww $EXT_PHY_CTRL_34 0x00 - mww $EXT_PHY_CTRL_34_SHDW 0x00 - mww $EXT_PHY_CTRL_35 0x00 - mww $EXT_PHY_CTRL_35_SHDW 0x00 - mww $EXT_PHY_CTRL_22 0x00 - mww $EXT_PHY_CTRL_22_SHDW 0x00 - mww $EXT_PHY_CTRL_23 [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ] - mww $EXT_PHY_CTRL_23_SHDW [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ] - mww $EXT_PHY_CTRL_24 [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay ] - mww $EXT_PHY_CTRL_24_SHDW [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0 ] - mww $EXT_PHY_CTRL_25 [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ] - mww $EXT_PHY_CTRL_25_SHDW [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ] - mww $EXT_PHY_CTRL_36 [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ] - mww $EXT_PHY_CTRL_36_SHDW [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ] -} - -proc config_ddr_timing { } { - global EMIF_SDRAM_TIM_1 - global EMIF_SDRAM_TIM_2 - global EMIF_SDRAM_TIM_3 - global EMIF_SDRAM_TIM_1_SHDW - global EMIF_SDRAM_TIM_2_SHDW - global EMIF_SDRAM_TIM_3_SHDW - global EMIF_ZQ_CONFIG - - mww $EMIF_SDRAM_TIM_1 0xeaaad4db - mww $EMIF_SDRAM_TIM_1_SHDW 0xeaaad4db - - mww $EMIF_SDRAM_TIM_2 0x266b7fda - mww $EMIF_SDRAM_TIM_2_SHDW 0x266b7fda - - mww $EMIF_SDRAM_TIM_3 0x107f8678 - mww $EMIF_SDRAM_TIM_3_SHDW 0x107f8678 - - mww $EMIF_ZQ_CONFIG 0x50074be4 -} - -proc config_ddr_pm { } { - global EMIF_PWR_MGMT_CTRL - global EMIF_PWR_MGMT_CTRL_SHDW - global EMIF_DLL_CALIB_CTRL - global EMIF_DLL_CALIB_CTRL_SHDW - global EMIF_TEMP_ALERT_CONFIG - - mww $EMIF_PWR_MGMT_CTRL 0x00 - mww $EMIF_PWR_MGMT_CTRL_SHDW 0x00 - mww $EMIF_DLL_CALIB_CTRL 0x00050000 - mww $EMIF_DLL_CALIB_CTRL_SHDW 0x00050000 - mww $EMIF_TEMP_ALERT_CONFIG 0x00 -} - -proc config_ddr_priority { } { - global EMIF_PRI_COS_MAP - global EMIF_CONNID_COS_1_MAP - global EMIF_CONNID_COS_2_MAP - global EMIF_RD_WR_EXEC_THRSH - global COS_CONFIG - - mww $EMIF_PRI_COS_MAP 0x00 - mww $EMIF_CONNID_COS_1_MAP 0x00 - mww $EMIF_CONNID_COS_2_MAP 0x0 - mww $EMIF_RD_WR_EXEC_THRSH 0x0405 - mww $COS_CONFIG 0x00ffffff -} - -proc config_ddr3 { SDRAM_CONFIG } { - global CM_DLL_CTRL - global EMIF_IODFT_TLGC - global EMIF_RDWR_LVL_CTRL - global EMIF_RDWR_LVL_RMP_CTRL - global EMIF_SDRAM_CONFIG - global EMIF_SDRAM_CONFIG_EXT - global EMIF_SDRAM_REF_CTRL - global EMIF_SDRAM_REF_CTRL_SHDW - global EMIF_STATUS - global EXT_PHY_CTRL_36 - global EXT_PHY_CTRL_36_SHDW - - emif_prcm_clk_enable - vtp_enable - - set dll [ expr [ mrw $CM_DLL_CTRL ] & ~0x01 ] - mww $CM_DLL_CTRL $dll - while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { } - - config_ddr_ioctrl - - mww $EMIF_SDRAM_CONFIG_EXT 0xc163 - mww $EMIF_IODFT_TLGC 0x2011 - mww $EMIF_IODFT_TLGC 0x2411 - mww $EMIF_IODFT_TLGC 0x2011 - mww $EMIF_SDRAM_REF_CTRL 0x80003000 - - config_ddr_phy - - mww $EMIF_IODFT_TLGC 0x2011 - mww $EMIF_IODFT_TLGC 0x2411 - mww $EMIF_IODFT_TLGC 0x2011 - - config_ddr_timing - config_ddr_pm - config_ddr_priority - - mww $EMIF_SDRAM_REF_CTRL 0x3000 - mww $EMIF_SDRAM_CONFIG $SDRAM_CONFIG - - mww $EMIF_SDRAM_REF_CTRL 0x0c30 - mww $EMIF_SDRAM_REF_CTRL_SHDW 0x0c30 - - sleep 10 - - set tmp [ expr [ mrw $EXT_PHY_CTRL_36 ] | 0x0100 ] - mww $EXT_PHY_CTRL_36 $tmp - mww $EXT_PHY_CTRL_36_SHDW $tmp - - mww $EMIF_RDWR_LVL_RMP_CTRL 0x80000000 - mww $EMIF_RDWR_LVL_CTRL 0x80000000 - - while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { } - - if { [ mrw $EMIF_STATUS ] & 0x70 } { - error "DDR3 Hardware Leveling incomplete!!!" - } -} - -proc init_platform { SDRAM_CONFIG } { - config_opp100 - config_ddr3 $SDRAM_CONFIG -} - -$_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 } -$_TARGETNAME configure -event reset-end { disable_watchdog } diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg deleted file mode 100644 index c00dae9..0000000 --- a/tcl/target/amdm37x.cfg +++ /dev/null @@ -1,211 +0,0 @@ -# -# Copyright (C) 2010-2011 by Karl Kurbjun -# Copyright (C) 2009-2011 by Øyvind Harboe -# Copyright (C) 2009 by David Brownell -# Copyright (C) 2009 by Magnus Lundin -# -# TI AM/DM37x Technical Reference Manual (Version R) -# http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf -# -# This script is based on the AM3517 initialization. It should be considered -# preliminary since it needs more complete testing and only the basic -# operations work. -# - -############################################################################### -# User modifiable parameters -############################################################################### - -# This script uses the variable CHIPTYPE to determine whether this is an AM35x -# or DM37x target. If CHIPTYPE is not set it will error out. -if { [info exists CHIPTYPE] } { - - if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME - } else { - set _CHIPNAME $CHIPTYPE - } - - switch $CHIPTYPE { - dm37x { - # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan - set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f" - } - am35x { - # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan - set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f" - } - default { - error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"." - } - } -} else { - error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration." -} - -# Run the adapter at the fastest acceptable speed with the slowest possible -# core clock. -adapter_khz 10 - -############################################################################### -# JTAG setup -# The OpenOCD commands are described in the TAP Declaration section -# http://openocd.org/doc/html/TAP-Declaration.html -############################################################################### - -# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More -# can be read about this module in sprugn4r in chapter 27: "Debug and -# Emulation". The module is used to route the JTAG chain to the various -# subsystems in the chip. -source [find target/icepick.cfg] - -# The TAP order should be described from the TDO connection in OpenOCD to the -# TDI pin. The OpenOCD FAQ describes this in more detail: -# http://openocd.org/doc/html/FAQ.html - -# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO: -# -# Device | TAP number -# ---------|------------ -# DAP | 3 -# Sequencer| 2 Note: The sequencer is an ARM968 -# DSP | 1 -# D2D | 0 -# -# Right now the only secondary tap enabled is the DAP so the rest are left -# undescribed. - -###### -# Start of Chain Description -# The Secondary TAPs all have enable functions defined for use with the ICEPick -# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but -# the TAP numbers for ICEPick do not change. -# -# TODO: A disable function should also be added. -###### - -# Secondary TAP: DAP is closest to the TDO output -# The TAP enable event also needs to be described -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable -jtag configure $_CHIPNAME.dap -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 3" - -# These taps are only present in the DM37x series. -if { $CHIPTYPE == "dm37x" } { - # Secondary TAP: Sequencer (ARM968) it is not in the chain by default - # The ICEPick can be used to enable it in the chain. - jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable - jtag configure $_CHIPNAME.arm2 -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 2" - - # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable) - # The ICEPick can be used to enable it in the chain. - jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable - jtag configure $_CHIPNAME.dsp -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 1" -} - -# Secondary TAP: D2D it is not in the chain by default (-disable) -# The ICEPick can be used to enable it in the chain. -# This IRLEN is probably incorrect - not sure where the documentation is. -jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable -jtag configure $_CHIPNAME.d2d -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 0" - -# Primary TAP: ICEPick - it is closest to TDI so last in the chain -eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID" - -###### -# End of Chain Description -###### - -###### -# Start JTAG TAP events -###### - -# some TCK tycles are required to activate the DEBUG power domain -jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" - -# Enable the DAP TAP -jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" - -###### -# End JTAG TAP events -###### - -############################################################################### -# Target Setup: -# This section is described in the OpenOCD documentation under CPU Configuration -# http://openocd.org/doc/html/CPU-Configuration.html -############################################################################### - -# Create the CPU target to be used with GDB: Cortex-A8, using DAP -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap - -# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first -# 16K to be used as a scratchpad for OpenOCD. - -$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000 - -###### -# Start Target Reset Event Setup: -###### - -# Set the JTAG clock down to 10 kHz to be sure that it will work with the -# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up -# *after* PLL and clock tree setup. - -$_TARGETNAME configure -event "reset-start" { adapter_khz 10 } - -# Describe the reset assert process for openocd - this is asserted with the -# ICEPick -$_TARGETNAME configure -event "reset-assert" { - - global _CHIPNAME - - # assert warm system reset through ICEPick - icepick_c_wreset $_CHIPNAME.jrc -} - -# After the reset is asserted we need to re-initialize debugging and speed up -# the JTAG clock. - -$_TARGETNAME configure -event reset-assert-post { - - global _TARGETNAME - amdm37x_dbginit $_TARGETNAME - adapter_khz 1000 -} - -$_TARGETNAME configure -event gdb-attach { - - global _TARGETNAME - amdm37x_dbginit $_TARGETNAME - - echo "Halting target" - halt -} - -###### -# End Target Reset Event Setup: -###### - -############################################################################### -# Target Functions -# Add any functions needed for the target here -############################################################################### - -# Run this to enable invasive debugging. This is run automatically in the -# reset sequence. -proc amdm37x_dbginit {target} { - # General Cortex-A8 debug initialisation - cortex_a dbginit - - # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but - # access to the signal appears to be implementation specific. TI does not - # describe this register much except a quick line that states DBGEM (sic) is - # at this address and this bit. - $target mww phys 0x5401d030 0x00002000 -} - diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg deleted file mode 100644 index 196b048..0000000 --- a/tcl/target/ar71xx.cfg +++ /dev/null @@ -1,57 +0,0 @@ -# Atheros AR71xx MIPS 24Kc SoC. -# tested on PB44 refererence board - -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -reset_config trst_and_srst - -set CHIPNAME ar71xx - -jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1 - -set _TARGETNAME $CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME - -$_TARGETNAME configure -event reset-halt-post { - #setup PLL to lowest common denominator 300/300/150 setting - mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0 - mww 0xb8050000 0x800f40a3 ;# send to PLL - - #next command will reset for PLL changes to take effect - mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC) -} - -$_TARGETNAME configure -event reset-init { - #complete pll initialization - mww 0xb8050000 0x800f0080 ;# set sw_update bit - mww 0xb8050008 0 ;# clear reset_switch bit - mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass - mww 0xb8050008 1 ;# set clock_switch bit - sleep 1 ;# wait for lock - - # Setup DDR config and flash mapping - mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0) - mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8) - - mww 0xb8000010 8 ;# force precharge all banks - mww 0xb8000010 1 ;# force EMRS update cycle - mww 0xb800000c 0 ;# clr ext. mode register - mww 0xb8000010 2 ;# force auto refresh all banks - mww 0xb8000010 8 ;# force precharge all banks - mww 0xb8000008 0x31 ;# set DDR mode value CAS=3 - mww 0xb8000010 1 ;# force EMRS update cycle - mww 0xb8000014 0x461b ;# DDR refresh value - mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff) - mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7) - mww 0xb8000020 0 - mww 0xb8000024 0 - mww 0xb8000028 0 -} - -# setup working area somewhere in RAM -$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000 - -# serial SPI capable flash -# flash bank <driver> <base> <size> <chip_width> <bus_width> - diff --git a/tcl/target/armada370.cfg b/tcl/target/armada370.cfg deleted file mode 100644 index 40c779b..0000000 --- a/tcl/target/armada370.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# -# armada370 -- support for the Marvell Armada/370 CPU family -# -# gerg@uclinux.org, OCT-2013 -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME armada370 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap - -proc armada370_dbginit {target} { - cortex_a dbginit -} - -$_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME" - -# We need to init now, so we can run the apsel command. -init -dap apsel 1 - diff --git a/tcl/target/at32ap7000.cfg b/tcl/target/at32ap7000.cfg deleted file mode 100644 index 8573aa1..0000000 --- a/tcl/target/at32ap7000.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# Atmel AT32AP7000 -# -# This is the only core in the now-inactive high end AVR32 product line, -# with MMU, Java Acceleration, and "pixel coprocessor". The AP7 line -# is for "Application Processors" (AP) with 7-stage pipelines. -# -# Most current AVR32 parts are in the UC3 flash based microcontroller (UC) -# product line with 3-stage pipelines and without those extras. -# -# All AVR32 parts provide the Nexus Class 3 on-chip debug interfaces -# through their JTAG interfaces. - -jtag newtap ap7 nexus -irlen 5 -expected-id 0x21e8203f - -# REVISIT declare an avr32 target ... needs OpenOCD infrastructure -# for both Nexus (generic) and AVR32 (Atmel-specific). diff --git a/tcl/target/at91r40008.cfg b/tcl/target/at91r40008.cfg deleted file mode 100644 index 912bd0e..0000000 --- a/tcl/target/at91r40008.cfg +++ /dev/null @@ -1,29 +0,0 @@ -# AT91R40008 target configuration file - -# TRST is tied to SRST on the AT91X40 family. -reset_config srst_only srst_pulls_trst - - -if {[info exists CHIPNAME]} { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME at91r40008 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Setup the JTAG scan chain. -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x1f0f0f0f -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0 diff --git a/tcl/target/at91rm9200.cfg b/tcl/target/at91rm9200.cfg deleted file mode 100644 index 2e8c1e0..0000000 --- a/tcl/target/at91rm9200.cfg +++ /dev/null @@ -1,47 +0,0 @@ -# Atmel AT91rm9200 -# http://atmel.com/products/at91/ - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME at91rm9200 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x05b0203f -} - -# Never allow the following! -if { $_CPUTAPID == 0x15b0203f } { - echo "-------------------------------------------------------" - echo "- ERROR: -" - echo "- ERROR: TapID 0x15b0203f is wrong for at91rm9200 -" - echo "- ERROR: The chip/board has a JTAG select pin/jumper -" - echo "- ERROR: -" - echo "- ERROR: In one position (0x05b0203f) it selects the -" - echo "- ERROR: ARM CPU, in the other position (0x1b0203f) -" - echo "- ERROR: it selects boundry-scan not the ARM -" - echo "- ERROR: -" - echo "-------------------------------------------------------" -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# Create the GDB Target. -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME - -# AT91RM9200 has a 16K block of sram @ 0x0020.0000 -$_TARGETNAME configure -work-area-phys 0x00200000 \ - -work-area-size 0x4000 -work-area-backup 1 - -# This chip has a DCC ... use it -arm7_9 dcc_downloads enable diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg deleted file mode 100644 index fca655d..0000000 --- a/tcl/target/at91sam3XXX.cfg +++ /dev/null @@ -1,87 +0,0 @@ -# script for ATMEL sam3, a Cortex-M3 chip -# -# at91sam3u4e -# at91sam3u2e -# at91sam3u1e -# at91sam3u4c -# at91sam3u2c -# at91sam3u1c -# -# at91sam3s4c -# at91sam3s4b -# at91sam3s4a -# at91sam3s2c -# at91sam3s2b -# at91sam3s2a -# at91sam3s1c -# at91sam3s1b -# at91sam3s1a -# -# at91sam3A4C -# at91sam3A8C -# at91sam3X4C -# at91sam3X4E -# at91sam3X8C -# at91sam3X8E -# at91sam3X8H - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME sam3 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 64kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -# 16K is plenty, the smallest chip has this much -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -$_TARGETNAME configure -event gdb-flash-erase-start { - halt -} - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz -# -# Since we may be running of an RC oscilator, we crank down the speed a -# bit more to be on the safe side. Perhaps superstition, but if are -# running off a crystal, we can run closer to the limit. Note -# that there can be a pretty wide band where things are more or less stable. - -adapter_khz 500 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/at91sam3ax_4x.cfg b/tcl/target/at91sam3ax_4x.cfg deleted file mode 100644 index 78ca79f..0000000 --- a/tcl/target/at91sam3ax_4x.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# common stuff -source [find target/at91sam3ax_xx.cfg] - -# size is automatically "calculated" by probing -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME -# This is a 256K chip - it has the 2nd bank -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME at91sam3 0x0000A0000 0 1 1 $_TARGETNAME diff --git a/tcl/target/at91sam3ax_8x.cfg b/tcl/target/at91sam3ax_8x.cfg deleted file mode 100644 index e249383..0000000 --- a/tcl/target/at91sam3ax_8x.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# common stuff -source [find target/at91sam3ax_xx.cfg] - -# size is automatically "calculated" by probing -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME -# This is a 512K chip - it has the 2nd bank -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME - - diff --git a/tcl/target/at91sam3ax_xx.cfg b/tcl/target/at91sam3ax_xx.cfg deleted file mode 100644 index e561771..0000000 --- a/tcl/target/at91sam3ax_xx.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# script for ATMEL sam3, a Cortex-M3 chip -# -# at91sam3A4C -# at91sam3A8C -# at91sam3X4C -# at91sam3X4E -# at91sam3X8C -# at91sam3X8E -# at91sam3X8H -source [find target/at91sam3XXX.cfg] - diff --git a/tcl/target/at91sam3nXX.cfg b/tcl/target/at91sam3nXX.cfg deleted file mode 100644 index 19bd33a..0000000 --- a/tcl/target/at91sam3nXX.cfg +++ /dev/null @@ -1,32 +0,0 @@ - -# -# Configuration for Atmel's SAM3N series -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME at91sam3n -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME - -set _FLASHNAME $_CHIPNAME.flash -flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/at91sam3sXX.cfg b/tcl/target/at91sam3sXX.cfg deleted file mode 100644 index 09146bd..0000000 --- a/tcl/target/at91sam3sXX.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# script for ATMEL sam3, a Cortex-M3 chip -# -# at91sam3s4c -# at91sam3s4b -# at91sam3s4a -# at91sam3s2c -# at91sam3s2b -# at91sam3s2a -# at91sam3s1c -# at91sam3s1b -# at91sam3s1a - -source [find target/at91sam3XXX.cfg] - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam3 0x00400000 0 1 1 $_TARGETNAME diff --git a/tcl/target/at91sam3u1c.cfg b/tcl/target/at91sam3u1c.cfg deleted file mode 100644 index 47c227b..0000000 --- a/tcl/target/at91sam3u1c.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# common stuff -source [find target/at91sam3uxx.cfg] - -# size is automatically "calculated" by probing -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME - - diff --git a/tcl/target/at91sam3u1e.cfg b/tcl/target/at91sam3u1e.cfg deleted file mode 100644 index 47c227b..0000000 --- a/tcl/target/at91sam3u1e.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# common stuff -source [find target/at91sam3uxx.cfg] - -# size is automatically "calculated" by probing -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME - - diff --git a/tcl/target/at91sam3u2c.cfg b/tcl/target/at91sam3u2c.cfg deleted file mode 100644 index 47c227b..0000000 --- a/tcl/target/at91sam3u2c.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# common stuff -source [find target/at91sam3uxx.cfg] - -# size is automatically "calculated" by probing -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME - - diff --git a/tcl/target/at91sam3u2e.cfg b/tcl/target/at91sam3u2e.cfg deleted file mode 100644 index 47c227b..0000000 --- a/tcl/target/at91sam3u2e.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# common stuff -source [find target/at91sam3uxx.cfg] - -# size is automatically "calculated" by probing -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME - - diff --git a/tcl/target/at91sam3u4c.cfg b/tcl/target/at91sam3u4c.cfg deleted file mode 100644 index 5cacbcb..0000000 --- a/tcl/target/at91sam3u4c.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# common stuff -source [find target/at91sam3uxx.cfg] - -# size is automatically "calculated" by probing -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME -# This is a 256K chip, it has the 2nd bank -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME - - diff --git a/tcl/target/at91sam3u4e.cfg b/tcl/target/at91sam3u4e.cfg deleted file mode 100644 index a48f992..0000000 --- a/tcl/target/at91sam3u4e.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# common stuff -source [find target/at91sam3uxx.cfg] - -# size is automatically "calculated" by probing -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME -# This is a 256K chip - it has the 2nd bank -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME - - diff --git a/tcl/target/at91sam3uxx.cfg b/tcl/target/at91sam3uxx.cfg deleted file mode 100644 index b42ae19..0000000 --- a/tcl/target/at91sam3uxx.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# script for ATMEL sam3, a Cortex-M3 chip -# -# at91sam3u4e -# at91sam3u2e -# at91sam3u1e -# at91sam3u4c -# at91sam3u2c -# at91sam3u1c - -source [find target/at91sam3XXX.cfg] - diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg deleted file mode 100644 index ca80143..0000000 --- a/tcl/target/at91sam4XXX.cfg +++ /dev/null @@ -1,63 +0,0 @@ -# -# script for ATMEL sam4, a Cortex-M4 chip -# - -# -# sam4 devices can support both JTAG and SWD transports. -# -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME sam4 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 64kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -# 16K is plenty, the smallest chip has this much -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz -# -# Since we may be running of an RC oscilator, we crank down the speed a -# bit more to be on the safe side. Perhaps superstition, but if are -# running off a crystal, we can run closer to the limit. Note -# that there can be a pretty wide band where things are more or less stable. - -adapter_khz 500 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg deleted file mode 100644 index 4aee7d0..0000000 --- a/tcl/target/at91sam4lXX.cfg +++ /dev/null @@ -1,27 +0,0 @@ -# script for ATMEL sam4l, a Cortex-M4 chip -# - -source [find target/at91sam4XXX.cfg] - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME - -# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N -# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3). -# -# smap_reset_deassert configures whether we want to run or halt out of reset, -# then instruct the SMAP to let us out of reset. -$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert" - -# SRST (wired to RESET_N) resets debug circuitry -# srst_pulls_trst is not configured here to avoid an error raised in reset halt -reset_config srst_gates_jtag - -# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed. -# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio. -# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2 -# but your mileage may vary. -adapter_khz 50 - -# System RC oscillator RCSYS starts in 3 cycles -adapter_nsrst_delay 0 diff --git a/tcl/target/at91sam4sXX.cfg b/tcl/target/at91sam4sXX.cfg deleted file mode 100644 index 8883e23..0000000 --- a/tcl/target/at91sam4sXX.cfg +++ /dev/null @@ -1,7 +0,0 @@ -# script for ATMEL sam4, a Cortex-M4 chip -# - -source [find target/at91sam4XXX.cfg] - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME diff --git a/tcl/target/at91sam4sd32x.cfg b/tcl/target/at91sam4sd32x.cfg deleted file mode 100644 index 077b1f5..0000000 --- a/tcl/target/at91sam4sd32x.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# script for ATMEL sam4sd32, a Cortex-M4 chip -# - -source [find target/at91sam4XXX.cfg] - -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME at91sam4 0x00500000 0 1 1 $_TARGETNAME diff --git a/tcl/target/at91sam7a2.cfg b/tcl/target/at91sam7a2.cfg deleted file mode 100644 index f7a0de2..0000000 --- a/tcl/target/at91sam7a2.cfg +++ /dev/null @@ -1,23 +0,0 @@ - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME at91sam7a2 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x1f0f0f0f -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/tcl/target/at91sam7se512.cfg b/tcl/target/at91sam7se512.cfg deleted file mode 100644 index ab09701..0000000 --- a/tcl/target/at91sam7se512.cfg +++ /dev/null @@ -1,39 +0,0 @@ -# ATMEL sam7se512 -# Example: the "Elektor Internet Radio" - EIR -# http://www.ethernut.de/en/hardware/eir/index.html - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME sam7se512 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # Force an error until we get a good number. - set _CPUTAPID 0xffffffff -} - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only srst_pulls_trst - -#jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# The target -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 - -#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 - diff --git a/tcl/target/at91sam7sx.cfg b/tcl/target/at91sam7sx.cfg deleted file mode 100644 index a563ac0..0000000 --- a/tcl/target/at91sam7sx.cfg +++ /dev/null @@ -1,53 +0,0 @@ -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only srst_pulls_trst - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME at91sam7s -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x3f0f0f0f -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -$_TARGETNAME configure -event reset-init { - soft_reset_halt - # RSTC_CR : Reset peripherals - mww 0xfffffd00 0xa5000004 - # disable watchdog - mww 0xfffffd44 0x00008000 - # enable user reset - mww 0xfffffd08 0xa5000001 - # CKGR_MOR : enable the main oscillator - mww 0xfffffc20 0x00000601 - sleep 10 - # CKGR_PLLR: 96.1097 MHz - mww 0xfffffc2c 0x00481c0e - sleep 10 - # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz - mww 0xfffffc30 0x00000007 - sleep 10 - # MC_FMR: flash mode (FWS=1,FMCN=73) - mww 0xffffff60 0x00490100 - sleep 100 -} - -$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 - -#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 diff --git a/tcl/target/at91sam7x256.cfg b/tcl/target/at91sam7x256.cfg deleted file mode 100644 index e1a2435..0000000 --- a/tcl/target/at91sam7x256.cfg +++ /dev/null @@ -1,50 +0,0 @@ -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only srst_pulls_trst - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME sam7x256 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x3f0f0f0f -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -event reset-init { - # disable watchdog - mww 0xfffffd44 0x00008000 - # enable user reset - mww 0xfffffd08 0xa5000001 - # CKGR_MOR : enable the main oscillator - mww 0xfffffc20 0x00000601 - sleep 10 - # CKGR_PLLR: 96.1097 MHz - mww 0xfffffc2c 0x00481c0e - sleep 10 - # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz - mww 0xfffffc30 0x00000007 - sleep 10 - # MC_FMR: flash mode (FWS=1,FMCN=60) - mww 0xffffff60 0x003c0100 - sleep 100 -} - -$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 - -#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 diff --git a/tcl/target/at91sam7x512.cfg b/tcl/target/at91sam7x512.cfg deleted file mode 100644 index 6910e85..0000000 --- a/tcl/target/at91sam7x512.cfg +++ /dev/null @@ -1,51 +0,0 @@ -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only srst_pulls_trst - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME sam7x512 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x3f0f0f0f -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -event reset-init { - # disable watchdog - mww 0xfffffd44 0x00008000 - # enable user reset - mww 0xfffffd08 0xa5000001 - # CKGR_MOR : enable the main oscillator - mww 0xfffffc20 0x00000601 - sleep 10 - # CKGR_PLLR: 96.1097 MHz - mww 0xfffffc2c 0x00481c0e - sleep 10 - # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz - mww 0xfffffc30 0x00000007 - sleep 10 - # MC_FMR: flash mode (FWS=1,FMCN=60) - mww 0xffffff60 0x003c0100 - sleep 100 -} - -$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 - -#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME.0 at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 -flash bank $_FLASHNAME.1 at91sam7 0 0 0 0 $_TARGETNAME 1 0 0 0 0 0 0 18432 diff --git a/tcl/target/at91sam9.cfg b/tcl/target/at91sam9.cfg deleted file mode 100644 index bf99fb2..0000000 --- a/tcl/target/at91sam9.cfg +++ /dev/null @@ -1,37 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9 -###################################### - -if { [info exists AT91_CHIPNAME] } { - set _CHIPNAME $AT91_CHIPNAME -} else { - error "you must specify a chip name" -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0792603f -} - -reset_config trst_and_srst separate trst_push_pull srst_open_drain - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -adapter_nsrst_delay 300 -jtag_ntrst_delay 200 - -adapter_khz 3 - -###################### -# Target configuration -###################### - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/tcl/target/at91sam9260.cfg b/tcl/target/at91sam9260.cfg deleted file mode 100644 index c5a07fd..0000000 --- a/tcl/target/at91sam9260.cfg +++ /dev/null @@ -1,19 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9260 -###################################### - -if { [info exists CHIPNAME] } { - set AT91_CHIPNAME $CHIPNAME -} else { - set AT91_CHIPNAME at91sam9260 -} - -source [find target/at91sam9.cfg] - - -# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The -# AT91SAM9260 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000. -# Both areas are 4 kB long. - -#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x1000 -work-area-backup 1 -$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1 diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg deleted file mode 100644 index 9ab7409..0000000 --- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg +++ /dev/null @@ -1,89 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9260 -###################################### - -source [find target/at91sam9261.cfg] - -reset_config trst_and_srst - -adapter_khz 4 - -adapter_nsrst_delay 200 -jtag_ntrst_delay 200 - -scan_chain -$_TARGETNAME configure -event reset-start { - # at reset chip runs at 32khz - adapter_khz 8 -} - -$_TARGETNAME configure -event reset-init {at91sam_init} - -# Flash configuration -#flash bank <name> cfi <base> <size> <chip width> <bus width> <target> -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME - -# Faster memory downloads. This is disabled automatically during -# reset init since all reset init sequences are too short for -# fast memory access -arm7_9 dcc_downloads enable -arm7_9 fast_memory_access enable - -proc at91sam_init { } { - mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset - mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog - - mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator - sleep 20 ;# wait 20 ms - mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator - sleep 10 ;# wait 10 ms - mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz - sleep 20 ;# wait 20 ms - mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler - sleep 10 ;# wait 10 ms - mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected - sleep 10 ;# wait 10 ms - - # Now run at anything fast... ie: 10mhz! - adapter_khz 10000 ;# Increase JTAG Speed to 6 MHz - - mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit - mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0 - mww 0xffffec08 0x00160016 ;# SMC_CYCLE0 - mww 0xffffec0c 0x00161003 ;# SMC_MODE0 - - mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31 - mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 - - mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM - - mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks) - #mww 0xffffea08 0x85227254 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks) - - mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command - mww 0x20000000 0 - mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command - mww 0x20000000 0 - mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x4 - mww 0x20000000 0 - mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command - mww 0x20000000 0 - mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode - mww 0x20000000 0 - mww 0xffffea04 0x5d2 ;# SDRAMC_TR : Set refresh timer count to 15us -} diff --git a/tcl/target/at91sam9261.cfg b/tcl/target/at91sam9261.cfg deleted file mode 100644 index 3ad1411..0000000 --- a/tcl/target/at91sam9261.cfg +++ /dev/null @@ -1,14 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9261 -###################################### - -if { [info exists CHIPNAME] } { - set AT91_CHIPNAME $CHIPNAME -} else { - set AT91_CHIPNAME at91sam9261 -} - -source [find target/at91sam9.cfg] - -# Internal sram1 memory -$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x28000 -work-area-backup 1 diff --git a/tcl/target/at91sam9263.cfg b/tcl/target/at91sam9263.cfg deleted file mode 100644 index d2ee113..0000000 --- a/tcl/target/at91sam9263.cfg +++ /dev/null @@ -1,20 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9263 -###################################### - -if { [info exists CHIPNAME] } { - set AT91_CHIPNAME $CHIPNAME -} else { - set AT91_CHIPNAME at91sam9263 -} - -source [find target/at91sam9.cfg] - -# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The -# AT91SAM9263 has two SRAM areas, -# one starting at 0x00300000 of 80KiB -# and the other starting at 0x00500000 of 16KiB. - -# Internal sram1 memory -$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x14000 -work-area-backup 1 -#$_TARGETNAME configure -work-area-phys 0x00500000 -work-area-size 0x4000 -work-area-backup 1 diff --git a/tcl/target/at91sam9g10.cfg b/tcl/target/at91sam9g10.cfg deleted file mode 100644 index b49f3d9..0000000 --- a/tcl/target/at91sam9g10.cfg +++ /dev/null @@ -1,16 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9G10 -###################################### - -if { [info exists CHIPNAME] } { - set AT91_CHIPNAME $CHIPNAME -} else { - set AT91_CHIPNAME at91sam9g10 -} - -source [find target/at91sam9.cfg] - -# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The -# AT91SAM9G10 has one SRAM area at 0x00300000 of 16KiB - -$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1 diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg deleted file mode 100644 index 3f5e3c6..0000000 --- a/tcl/target/at91sam9g20.cfg +++ /dev/null @@ -1,22 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9G20 -###################################### - -if { [info exists CHIPNAME] } { - set AT91_CHIPNAME $CHIPNAME -} else { - set AT91_CHIPNAME at91sam9g20 -} - -source [find target/at91sam9.cfg] - -# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock). - -adapter_khz 5 - -# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The -# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000. -# Both areas are 16 kB long. - -#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1 -$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1 diff --git a/tcl/target/at91sam9g45.cfg b/tcl/target/at91sam9g45.cfg deleted file mode 100644 index 7323679..0000000 --- a/tcl/target/at91sam9g45.cfg +++ /dev/null @@ -1,16 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9G45 -###################################### - -if { [info exists CHIPNAME] } { - set AT91_CHIPNAME $CHIPNAME -} else { - set AT91_CHIPNAME at91sam9g45 -} - -source [find target/at91sam9.cfg] - -# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The -# AT91SAM9G45 has one SRAM area starting at 0x00300000 of 64 KiB. - -$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x200000 -work-area-backup 1 diff --git a/tcl/target/at91sam9rl.cfg b/tcl/target/at91sam9rl.cfg deleted file mode 100644 index db05229..0000000 --- a/tcl/target/at91sam9rl.cfg +++ /dev/null @@ -1,14 +0,0 @@ -###################################### -# Target: Atmel AT91SAM9RL -###################################### - -if { [info exists CHIPNAME] } { - set AT91_CHIPNAME $CHIPNAME -} else { - set AT91_CHIPNAME at91sam9rl -} - -source [find target/at91sam9.cfg] - -# Internal sram1 memory -$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x10000 -work-area-backup 1 diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg deleted file mode 100644 index 47b4f5f..0000000 --- a/tcl/target/at91samdXX.cfg +++ /dev/null @@ -1,87 +0,0 @@ -# -# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip -# - -# -# samdXX devices only support SWD transports. -# -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME at91samd -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 2kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x800 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N -# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2) -# -# dsu_reset_deassert configures whether we want to run or halt out of reset, -# then instruct the DSU to let us out of reset. -$_TARGETNAME configure -event reset-deassert-post { - at91samd dsu_reset_deassert -} - -# SRST (wired to RESET_N) resets debug circuitry -# srst_pulls_trst is not configured here to avoid an error raised in reset halt -reset_config srst_gates_jtag - -# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) cannot -# stop the MCU before it starts executing code if hardware RESETN -# line is configured by command "reset_config srst_only" -# Use "reset_config none" (default) before flash programming. - -# Do not use a reset button with other SWD adapter than Atmel's EDBG. -# DSU usually locks MCU in reset state until you issue a reset command -# in OpenOCD. - -# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset. -# Other members of family usually use SYSCLK = 4 MHz after reset. -# Datasheet does not specify SYSCLK to SWD clock ratio. -# Usually used SYSCLK/6 is slow, testing shows that debugging can -# work @ SYSCLK/2 but your mileage may vary. -# This limit is most probably imposed by incorrectly handled SWD WAIT -# on some SWD adapters. - -adapter_khz 400 - -# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works -# without problem at maximal clock speed. Atmel recommends -# adapter speed less than 10 * CPU clock. -# adapter_khz 5000 - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME diff --git a/tcl/target/at91samg5x.cfg b/tcl/target/at91samg5x.cfg deleted file mode 100644 index 57274c0..0000000 --- a/tcl/target/at91samg5x.cfg +++ /dev/null @@ -1,7 +0,0 @@ -# script for the ATMEL samg5x Cortex-M4F chip family -# - -source [find target/at91sam4XXX.cfg] - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME diff --git a/tcl/target/atheros_ar2313.cfg b/tcl/target/atheros_ar2313.cfg deleted file mode 100644 index 0966c6c..0000000 --- a/tcl/target/atheros_ar2313.cfg +++ /dev/null @@ -1,16 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $_CHIPNAME -} else { - set _CHIPNAME ar2313 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x00000001 -} - -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME diff --git a/tcl/target/atheros_ar2315.cfg b/tcl/target/atheros_ar2315.cfg deleted file mode 100644 index 92ad376..0000000 --- a/tcl/target/atheros_ar2315.cfg +++ /dev/null @@ -1,16 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $_CHIPNAME -} else { - set _CHIPNAME ar2315 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x00000001 -} - -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg deleted file mode 100644 index c5609bb..0000000 --- a/tcl/target/atheros_ar9331.cfg +++ /dev/null @@ -1,16 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $_CHIPNAME -} else { - set _CHIPNAME ar9331 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x00000001 -} - -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME diff --git a/tcl/target/atmega128.cfg b/tcl/target/atmega128.cfg deleted file mode 100644 index b8f7d01..0000000 --- a/tcl/target/atmega128.cfg +++ /dev/null @@ -1,40 +0,0 @@ -# for avr - - set _CHIPNAME avr - set _ENDIAN little - -# jtag speed -adapter_khz 4500 - -reset_config srst_only -adapter_nsrst_delay 100 - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x8970203F -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME - -#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME - -#to use it, script will be like: -#init -#adapter_khz 4500 -#reset init -#verify_ircapture disable -# -#halt -#wait halt -#poll -#avr mass_erase 0 -#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex -#reset run -#shutdown diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg deleted file mode 100644 index b6c4842..0000000 --- a/tcl/target/atsamv.cfg +++ /dev/null @@ -1,51 +0,0 @@ -# ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts -# The chips are very similar; the SAMV series just has -# more peripherals and seems like the "flagship" of the -# family. This script will work for all of them. - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME samv -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 16kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0bd11477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -adapter_khz 1800 - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME - diff --git a/tcl/target/avr32.cfg b/tcl/target/avr32.cfg deleted file mode 100644 index f5ee1a4..0000000 --- a/tcl/target/avr32.cfg +++ /dev/null @@ -1,17 +0,0 @@ -set _CHIPNAME avr32 -set _ENDIAN big - -set _CPUTAPID 0x21e8203f - -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -reset_config trst_and_srst separate - -# jtag scan chain -# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID - -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME - diff --git a/tcl/target/bcm281xx.cfg b/tcl/target/bcm281xx.cfg deleted file mode 100644 index 224af79..0000000 --- a/tcl/target/bcm281xx.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# BCM281xx - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME bcm281xx -} - - -# Main CPU DAP -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x4ba00477 -} - -jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4 - - -# Dual Cortex-A9 -set _TARGETNAME0 $_CHIPNAME.cpu0 -set _TARGETNAME1 $_CHIPNAME.cpu1 - -target create $_TARGETNAME0 cortex_a -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000 -target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000 -target smp $_TARGETNAME0 $_TARGETNAME1 - -$_TARGETNAME0 configure -event gdb-attach { - cortex_a dbginit -} -$_TARGETNAME1 configure -event gdb-attach { - cortex_a dbginit -} diff --git a/tcl/target/bcm4706.cfg b/tcl/target/bcm4706.cfg deleted file mode 100644 index 10b32c7..0000000 --- a/tcl/target/bcm4706.cfg +++ /dev/null @@ -1,7 +0,0 @@ -set _CHIPNAME bcm4706 -set _CPUID 0x1008c17f - -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME diff --git a/tcl/target/bcm4718.cfg b/tcl/target/bcm4718.cfg deleted file mode 100644 index 8193914..0000000 --- a/tcl/target/bcm4718.cfg +++ /dev/null @@ -1,5 +0,0 @@ -set _CHIPNAME bcm4718 -set _LVTAPID 0x1471617f -set _CPUID 0x0008c17f - -source [find target/bcm47xx.cfg] diff --git a/tcl/target/bcm47xx.cfg b/tcl/target/bcm47xx.cfg deleted file mode 100644 index 0132bb8..0000000 --- a/tcl/target/bcm47xx.cfg +++ /dev/null @@ -1,21 +0,0 @@ -echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed" -reset_config none - -jtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID -jtag configure $_CHIPNAME-lv.tap -event setup "jtag tapenable $_CHIPNAME.cpu" -jtag configure $_CHIPNAME-lv.tap -event tap-disable {} - -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable -jtag configure $_CHIPNAME.cpu -event tap-enable "switch_lv_to_ejtag" - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME - -proc switch_lv_to_ejtag {} { - global _CHIPNAME - poll 0 - irscan $_CHIPNAME-lv.tap 0x143ff3a - drscan $_CHIPNAME-lv.tap 32 1 - jtag tapdisable $_CHIPNAME-lv.tap - poll 1 -} diff --git a/tcl/target/bcm5352e.cfg b/tcl/target/bcm5352e.cfg deleted file mode 100644 index 3f0495a..0000000 --- a/tcl/target/bcm5352e.cfg +++ /dev/null @@ -1,7 +0,0 @@ -set _CHIPNAME bcm5352e -set _CPUID 0x0535217f - -jtag newtap $_CHIPNAME cpu -irlen 8 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME diff --git a/tcl/target/bcm6348.cfg b/tcl/target/bcm6348.cfg deleted file mode 100644 index 2540b51..0000000 --- a/tcl/target/bcm6348.cfg +++ /dev/null @@ -1,9 +0,0 @@ -set _CHIPNAME bcm6348 -set _CPUID 0x0634817f - -adapter_khz 1000 - -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg deleted file mode 100644 index 1eaa8fe..0000000 --- a/tcl/target/c100.cfg +++ /dev/null @@ -1,42 +0,0 @@ -# c100 config. -# This is ARM1136 dual core -# this script only configures one core (that is used to run Linux) - -# assume no PLL lock, start slowly -adapter_khz 100 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME c100 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x27b3645b -} - -if { [info exists DSPTAPID] } { - set _DSPTAPID $DSPTAPID -} else { - set _DSPTAPID 0x27b3645b -} - -jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID - - -# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME - -# C100's ARAM 64k SRAM -$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0 diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl deleted file mode 100644 index 52efa83..0000000 --- a/tcl/target/c100config.tcl +++ /dev/null @@ -1,412 +0,0 @@ - -# board(-config) specfic parameters file. - -# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ] -proc config {label} { - return [dict get [configC100] $label ] -} - -# show the value for the param. with label -proc showconfig {label} { - echo [format "0x%x" [dict get [configC100] $label ]] -} - -# Telo board config -# when there are more then one board config -# use soft links to c100board-config.tcl -# so that only the right board-config gets -# included (just like include/configs/board-configs.h -# in u-boot. -proc configC100 {} { - # xtal freq. 24MHz - dict set configC100 CFG_REFCLKFREQ 24000000 - - # Amba Clk 165MHz - dict set configC100 CONFIG_SYS_HZ_CLOCK 165000000 - dict set configC100 w_amba 1 - dict set configC100 x_amba 1 - # y = amba_clk * (w+1)*(x+1)*2/xtal_clk - dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] - - # Arm Clk 450MHz, must be a multiple of 25 MHz - dict set configC100 CFG_ARM_CLOCK 450000000 - dict set configC100 w_arm 0 - dict set configC100 x_arm 1 - # y = arm_clk * (w+1)*(x+1)*2/xtal_clk - dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] - - -} - -# This should be called for reset init event handler -proc setupTelo {} { - - # setup GPIO used as control signals for C100 - setupGPIO - # This will allow acces to lower 8MB or NOR - lowGPIO5 - # setup NOR size,timing,etc. - setupNOR - # setup internals + PLL + DDR2 - initC100 -} - - -proc setupNOR {} { - echo "Setting up NOR: 16MB, 16-bit wide bus, CS0" - # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init() - set EX_CSEN_REG [regs EX_CSEN_REG ] - set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] - set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] - set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] - set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] - set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] - set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] - set EX_MFSM_REG [regs EX_MFSM_REG ] - set EX_CSFSM_REG [regs EX_CSFSM_REG ] - set EX_WRFSM_REG [regs EX_WRFSM_REG ] - set EX_RDFSM_REG [regs EX_RDFSM_REG ] - - # enable Expansion Bus Clock + CS0 (NOR) - mww $EX_CSEN_REG 0x3 - # set the address space for CS0=16MB - mww $EX_CS0_SEG_REG 0x7ff - # set the CS0 bus width to 16-bit - mww $EX_CS0_CFG_REG 0x202 - # set timings to NOR - mww $EX_CS0_TMG1_REG 0x03034006 - mww $EX_CS0_TMG2_REG 0x04040002 - #mww $EX_CS0_TMG3_REG - # set EBUS clock 165/5=33MHz - mww $EX_CLOCK_DIV_REG 0x5 - # everthing else is OK with default -} - -proc bootNOR {} { - set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] - set BLOCK_RESET_REG [regs BLOCK_RESET_REG] - set DDR_RST [regs DDR_RST] - - # put DDR controller in reset (so that it comes reset in u-boot) - mmw $BLOCK_RESET_REG 0x0 $DDR_RST - # setup CS0 controller for NOR - setupNOR - # make sure we are accessing the lower part of NOR - lowGPIO5 - # set PC to start of NOR (at boot 0x20000000 = 0x0) - reg pc $EXP_CS0_BASEADDR - # run - resume -} -proc setupGPIO {} { - echo "Setting up GPIO block for Telo" - # This is current setup for Telo (see sch. for details): - #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup - #GPIO1 irq line for FXS-FXO - #GPIO5 addr22 for NOR flash (access to upper 8MB) - #GPIO17 reset for DECT module. - #GPIO29 CS_n for NAND - - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] - set GPIO_OE_REG [regs GPIO_OE_REG] - - # set GPIO29=GPIO17=1, GPIO5=0 - mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17] - # enable [as output] GPIO29,GPIO17,GPIO5 - mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5] -} - -proc highGPIO5 {} { - echo "GPIO5 high" - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] - # set GPIO5=1 - mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0 -} - -proc lowGPIO5 {} { - echo "GPIO5 low" - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] - # set GPIO5=0 - mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5] -} - -proc boardID {id} { - # so far built: - # 4'b1111 - dict set boardID 15 name "EVT1" - dict set boardID 15 ddr2size 128M - # dict set boardID 15 nandsize 1G - # dict set boardID 15 norsize 16M - # 4'b0000 - dict set boardID 0 name "EVT2" - dict set boardID 0 ddr2size 128M - # 4'b0001 - dict set boardID 1 name "EVT3" - dict set boardID 1 ddr2size 256M - # 4'b1110 - dict set boardID 14 name "EVT3_old" - dict set boardID 14 ddr2size 128M - # 4'b0010 - dict set boardID 2 name "EVT4" - dict set boardID 2 ddr2size 256M - - return $boardID -} - - -# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect() -# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors -proc ooma_board_detect {} { - set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] - - # read the current value of the BOOTSRAP pins - set tmp [mrw $GPIO_BOOTSTRAP_REG] - echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] - # extract the GPBP bits - set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3] - - # display board ID - echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt] - # show it on serial console - putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt] - # return the ddr2 size, used to configure DDR2 on a given board. - return [dict get [boardID $gpbt] $gpbt ddr2size] -} - -proc configureDDR2regs_256M {} { - - set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] - set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] - set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] - set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA] - set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA] - set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA] - set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA] - set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA] - set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA] - set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA] - set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA] - set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA] - set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA] - set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA] - set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA] - set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA] - set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA] - set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA] - set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA] - set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA] - set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] - - set DENALI_CTL_02_VAL 0x0100000000010100 - set DENALI_CTL_11_VAL 0x433a32164a560a00 - - mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 - # 01_DATA mod [40]=1, enable BA2 - mw64bit $DENALI_CTL_01_DATA 0x0100010100000001 - mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL - mw64bit $DENALI_CTL_03_DATA 0x0102020202020201 - mw64bit $DENALI_CTL_04_DATA 0x0000010100000001 - mw64bit $DENALI_CTL_05_DATA 0x0203010300010101 - mw64bit $DENALI_CTL_06_DATA 0x060a020200020202 - mw64bit $DENALI_CTL_07_DATA 0x0000000300000206 - mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209 - mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a - mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18 - # 11_DATA mod [39-32]=16,more refresh - mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL - mw64bit $DENALI_CTL_12_DATA 0x0000000000000800 - mw64bit $DENALI_CTL_13_DATA 0x0010002000100040 - mw64bit $DENALI_CTL_14_DATA 0x0010004000100040 - mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000 - mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000 - mw64bit $DENALI_CTL_17_DATA 0x0000000000000000 - mw64bit $DENALI_CTL_18_DATA 0x0302000000000000 - mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600 - mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8 - - set wr_dqs_shift 0x40 - # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] - # wait int_status[2] (DRAM init complete) - echo -n "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { - sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - } - echo "done." - - # do ddr2 training sequence - # TBD (for now, if you need it, run trainDDR command) -} - -# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99() -# The values are computed based on Mindspeed and Nanya datasheets -proc configureDDR2regs_128M {} { - - set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] - set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] - set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] - set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA] - set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA] - set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA] - set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA] - set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA] - set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA] - set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA] - set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA] - set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA] - set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA] - set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA] - set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA] - set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA] - set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA] - set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA] - set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA] - set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA] - set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] - - - set DENALI_CTL_02_VAL 0x0100010000010100 - set DENALI_CTL_11_VAL 0x433A42124A650A37 - # set some default values - mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 - mw64bit $DENALI_CTL_01_DATA 0x0100000100000101 - mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL - mw64bit $DENALI_CTL_03_DATA 0x0102020202020201 - mw64bit $DENALI_CTL_04_DATA 0x0201010100000201 - mw64bit $DENALI_CTL_05_DATA 0x0203010300010101 - mw64bit $DENALI_CTL_06_DATA 0x050A020200020202 - mw64bit $DENALI_CTL_07_DATA 0x000000030E0B0205 - mw64bit $DENALI_CTL_08_DATA 0x6427003F3F0A0209 - mw64bit $DENALI_CTL_09_DATA 0x1A00002F00001A00 - mw64bit $DENALI_CTL_10_DATA 0x01202020201A1A1A - mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL - mw64bit $DENALI_CTL_12_DATA 0x0000080000000800 - mw64bit $DENALI_CTL_13_DATA 0x0010002000100040 - mw64bit $DENALI_CTL_14_DATA 0x0010004000100040 - mw64bit $DENALI_CTL_15_DATA 0x0508000000000000 - mw64bit $DENALI_CTL_16_DATA 0x000020472D200000 - mw64bit $DENALI_CTL_17_DATA 0x0000000008000000 - mw64bit $DENALI_CTL_18_DATA 0x0302000000000000 - mw64bit $DENALI_CTL_19_DATA 0x00001400C8030604 - mw64bit $DENALI_CTL_20_DATA 0x00000000823600C8 - - set wr_dqs_shift 0x40 - # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] - # wait int_status[2] (DRAM init complete) - echo -n "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { - sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - } - # This is not necessary - #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ] - echo "done." - - # do ddr2 training sequence - # TBD (for now, if you need it, run trainDDR command) -} - - - -proc setupUART0 {} { - # configure UART0 to 115200, 8N1 - set GPIO_LOCK_REG [regs GPIO_LOCK_REG] - set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] - set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] - set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0] - set UART0_LCR [regs UART0_LCR] - set LCR_DLAB [regs LCR_DLAB] - set UART0_DLL [regs UART0_DLL] - set UART0_DLH [regs UART0_DLH] - set UART0_IIR [regs UART0_IIR] - set UART0_IER [regs UART0_IER] - set LCR_ONE_STOP [regs LCR_ONE_STOP] - set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8] - set FCR_XMITRES [regs FCR_XMITRES] - set FCR_RCVRRES [regs FCR_RCVRRES] - set FCR_FIFOEN [regs FCR_FIFOEN] - set IER_UUE [regs IER_UUE] - - # unlock writing to IOCTRL register - mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL - # enable UART0 - mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0 - # baudrate 115200 - # This should really be amba_clk/(16*115200) but amba_clk=165MHz - set tmp 89 - # Enable Divisor Latch access - mmw $UART0_LCR $LCR_DLAB 0x0 - # set the divisor to $tmp - mww $UART0_DLL [expr $tmp & 0xff] - mww $UART0_DLH [expr $tmp >> 8] - # Disable Divisor Latch access - mmw $UART0_LCR 0x0 $LCR_DLAB - # set the UART to 8N1 - mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0 - # reset FIFO - mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0 - # enable FFUART - mww $UART0_IER $IER_UUE -} - -proc putcUART0 {char} { - - set UART0_LSR [regs UART0_LSR] - set UART0_THR [regs UART0_THR] - set LSR_TEMT [regs LSR_TEMT] - - # convert the 'char' to digit - set tmp [ scan $char %c ] - # /* wait for room in the tx FIFO on FFUART */ - while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 } - mww $UART0_THR $tmp - if { $char == "\n" } { putcUART0 \r } -} - -proc putsUART0 {str} { - set index 0 - set len [string length $str] - while { $index < $len } { - putcUART0 [string index $str $index] - set index [expr $index + 1] - } -} - - -proc trainDDR2 {} { - set ARAM_BASEADDR [regs ARAM_BASEADDR] - - # you must have run 'reset init' or u-boot - # load the training code to ARAM - load_image ./images/ddr2train.bin $ARAM_BASEADDR bin - # set PC to start of NOR (at boot 0x20000000 = 0x0) - reg pc $ARAM_BASEADDR - # run - resume -} - -proc flashUBOOT {file} { - # this will update uboot on NOR partition - set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] - - # setup CS0 controller for NOR - setupNOR - # make sure we are accessing the lower part of NOR - lowGPIO5 - flash probe 0 - echo "Erasing sectors 0-3 for uboot" - putsUART0 "Erasing sectors 0-3 for uboot\n" - flash erase_sector 0 0 3 - echo "Programming u-boot" - putsUART0 "Programming u-boot..." - arm11 memwrite burst enable - flash write_image $file $EXP_CS0_BASEADDR - arm11 memwrite burst disable - putsUART0 "done.\n" - putsUART0 "Rebooting, please wait!\n" - reboot -}
\ No newline at end of file diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl deleted file mode 100644 index c9124cb..0000000 --- a/tcl/target/c100helper.tcl +++ /dev/null @@ -1,506 +0,0 @@ - -proc helpC100 {} { - echo "List of useful functions for C100 processor:" - echo "1) reset init: will set up your Telo board" - echo "2) setupNOR: will setup NOR access" - echo "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR" - echo "4) setupGPIO: will setup GPIOs for Telo board" - echo "5) showGPIO: will show current GPIO config registers" - echo "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB" - echo "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB" - echo "8) showAmbaClk: will show current config registers for Amba Bus Clock" - echo "9) setupAmbaClk: will setup Amba Bus Clock=165MHz" - echo "10) showArmClk: will show current config registers for Arm Bus Clock" - echo "11) setupArmClk: will setup Amba Bus Clock=450MHz" - echo "12) ooma_board_detect: will show which version of Telo you have" - echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg" - echo "14) showDDR2: will show DDR2 config registers" - echo "15) showWatchdog: will show current regster config for watchdog" - echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)" - echo "17) bootNOR: will boot Telo from NOR" - echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured" - echo "19) putcUART0: will print a character on UART0" - echo "20) putsUART0: will print a string on UART0" - echo "21) trainDDR2: will run DDR2 training program" - echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin" -} - -source [find mem_helper.tcl] - -# read a 64-bit register (memory mapped) -proc mr64bit {reg} { - set value "" - mem2array value 32 $reg 2 - return $value -} - - -# write a 64-bit register (memory mapped) -proc mw64bit {reg value} { - set high [expr $value >> 32] - set low [expr $value & 0xffffffff] - #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low] - mww $reg $low - mww [expr $reg+4] $high -} - - -proc showNOR {} { - echo "This is the current NOR setup" - set EX_CSEN_REG [regs EX_CSEN_REG ] - set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] - set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] - set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] - set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] - set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] - set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] - set EX_MFSM_REG [regs EX_MFSM_REG ] - set EX_CSFSM_REG [regs EX_CSFSM_REG ] - set EX_WRFSM_REG [regs EX_WRFSM_REG ] - set EX_RDFSM_REG [regs EX_RDFSM_REG ] - - echo [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]] - echo [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]] - echo [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]] - echo [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]] - echo [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]] - echo [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]] - echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]] - echo [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]] - echo [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]] - echo [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]] - echo [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]] -} - - - -proc showGPIO {} { - echo "This is the current GPIO register setup" - # GPIO outputs register - set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] - # GPIO Output Enable register - set GPIO_OE_REG [regs GPIO_OE_REG] - set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG] - set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG] - # GPIO input register - set GPIO_INPUT_REG [regs GPIO_INPUT_REG] - set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG] - set MUX_CONF_REG [regs MUX_CONF_REG] - set SYSCONF_REG [regs SYSCONF_REG] - set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG] - set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] - set GPIO_LOCK_REG [regs GPIO_LOCK_REG] - set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] - set GPIO_DEVID_REG [regs GPIO_DEVID_REG] - - echo [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]] - echo [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]] - echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]] - echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]] - echo [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]] - echo [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]] - echo [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]] - echo [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]] - echo [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]] - echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]] - echo [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]] - echo [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]] - echo [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]] -} - - - -# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk()) -proc showAmbaClk {} { - set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] - set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL] - set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] - - echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]] - mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1 - # see if the PLL is in bypass mode - set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] - echo [format "PLL bypass bit: %d" $bypass] - if {$bypass == 1} { - echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]] - } else { - # nope, extract x,y,w and compute the PLL output freq. - set x [expr ($value(0) & 0x0001F0000) >> 16] - echo [format "x: %d" $x] - set y [expr ($value(0) & 0x00000007F)] - echo [format "y: %d" $y] - set w [expr ($value(0) & 0x000000300) >> 8] - echo [format "w: %d" $w] - echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]] - } -} - - -# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk()) -# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc) -proc setupAmbaClk {} { - set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS] - set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL] - set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL] - set ARM_AHB_BYP [regs ARM_AHB_BYP] - set PLL_DISABLE [regs PLL_DISABLE] - set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] - set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL] - set DIV_BYPASS [regs DIV_BYPASS] - set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK] - set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] - set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK] - set w [config w_amba] - set x [config x_amba] - set y [config y_amba] - - echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]] - #echo [format "setupAmbaClk: w= %d" $w] - #echo [format "setupAmbaClk: x= %d" $x] - #echo [format "setupAmbaClk: y= %d" $y] - # set PLL into BYPASS mode using MUX - mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0 - # do an internal PLL bypass - mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0 - # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us) - # openocd smallest resolution is 1ms so, wait 1ms - sleep 1 - # disable the PLL - mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0 - # wait 1ms - sleep 1 - # enable the PLL - mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE - sleep 1 - # set X, W and X - mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF - mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0 - # wait for PLL to lock - echo "Wating for Amba PLL to lock" - while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 } - # remove the internal PLL bypass - mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL - # remove PLL from BYPASS mode using MUX - mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS -} - - -# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk()) -proc showArmClk {} { - set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] - set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL] - set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] - - echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]] - mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1 - # see if the PLL is in bypass mode - set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] - echo [format "PLL bypass bit: %d" $bypass] - if {$bypass == 1} { - echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]] - } else { - # nope, extract x,y,w and compute the PLL output freq. - set x [expr ($value(0) & 0x0001F0000) >> 16] - echo [format "x: %d" $x] - set y [expr ($value(0) & 0x00000007F)] - echo [format "y: %d" $y] - set w [expr ($value(0) & 0x000000300) >> 8] - echo [format "w: %d" $w] - echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]] - } -} - -# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk()) -# Arm Clock is used by two ARM1136 cores -proc setupArmClk {} { - set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS] - set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL] - set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL] - set ARM_AHB_BYP [regs ARM_AHB_BYP] - set PLL_DISABLE [regs PLL_DISABLE] - set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] - set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL] - set DIV_BYPASS [regs DIV_BYPASS] - set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK] - set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] - set CFG_ARM_CLOCK [config CFG_ARM_CLOCK] - set w [config w_arm] - set x [config x_arm] - set y [config y_arm] - - echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]] - #echo [format "setupArmClk: w= %d" $w] - #echo [format "setupArmaClk: x= %d" $x] - #echo [format "setupArmaClk: y= %d" $y] - # set PLL into BYPASS mode using MUX - mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0 - # do an internal PLL bypass - mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0 - # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us) - # openocd smallest resolution is 1ms so, wait 1ms - sleep 1 - # disable the PLL - mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0 - # wait 1ms - sleep 1 - # enable the PLL - mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE - sleep 1 - # set X, W and X - mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF - mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0 - # wait for PLL to lock - echo "Wating for Amba PLL to lock" - while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 } - # remove the internal PLL bypass - mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL - # remove PLL from BYPASS mode using MUX - mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS -} - - - -proc setupPLL {} { - echo "PLLs setup" - setupAmbaClk - setupArmClk -} - -# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init() -proc setupDDR2 {} { - echo "Configuring DDR2" - - set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR] - set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR] - set MEMORY_CR [regs MEMORY_CR] - set BLOCK_RESET_REG [regs BLOCK_RESET_REG] - set DDR_RST [regs DDR_RST] - - # put DDR controller in reset (so that it is reset and correctly configured) - # this is only necessary if DDR was previously confiured - # and not reset. - mmw $BLOCK_RESET_REG 0x0 $DDR_RST - - set M [expr 1024 * 1024] - set DDR_SZ_1024M [expr 1024 * $M] - set DDR_SZ_256M [expr 256 * $M] - set DDR_SZ_128M [expr 128 * $M] - set DDR_SZ_64M [expr 64 * $M] - # ooma_board_detect returns DDR2 memory size - set tmp [ooma_board_detect] - if {$tmp == "128M"} { - echo "DDR2 size 128MB" - set ddr_size $DDR_SZ_128M - } elseif {$tmp == "256M"} { - echo "DDR2 size 256MB" - set ddr_size $DDR_SZ_256M - } else { - echo "Don't know how to handle this DDR2 size?" - } - - # Memory setup register - mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR] - # disbale ROM remap - mww $MEMORY_CR 0x0 - # Take DDR controller out of reset - mmw $BLOCK_RESET_REG $DDR_RST 0x0 - # min. 20 ops delay - sleep 1 - - # This will setup Denali DDR2 controller - if {$tmp == "128M"} { - configureDDR2regs_128M - } elseif {$tmp == "256M"} { - configureDDR2regs_256M - } else { - echo "Don't know how to configure DDR2 setup?" - } -} - - - -proc showDDR2 {} { - - set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] - set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] - set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] - set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA] - set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA] - set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA] - set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA] - set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA] - set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA] - set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA] - set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA] - set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA] - set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA] - set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA] - set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA] - set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA] - set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA] - set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA] - set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA] - set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA] - set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] - - set tmp [mr64bit $DENALI_CTL_00_DATA] - echo [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_01_DATA] - echo [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_02_DATA] - echo [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_03_DATA] - echo [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_04_DATA] - echo [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_05_DATA] - echo [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_06_DATA] - echo [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_07_DATA] - echo [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_08_DATA] - echo [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_09_DATA] - echo [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_10_DATA] - echo [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_11_DATA] - echo [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_12_DATA] - echo [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_13_DATA] - echo [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_14_DATA] - echo [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_15_DATA] - echo [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_16_DATA] - echo [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_17_DATA] - echo [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_18_DATA] - echo [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_19_DATA] - echo [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)] - set tmp [mr64bit $DENALI_CTL_20_DATA] - echo [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)] - -} - -proc initC100 {} { - # this follows u-boot/cpu/arm1136/start.S - set GPIO_LOCK_REG [regs GPIO_LOCK_REG] - set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] - set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] - set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG] - set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR] - set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG] - set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR] - set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG] - set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN] - set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN] - set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN] - set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN] - set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN] - set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN] - set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG] - - - # unlock writing to IOCTRL register - mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL - # enable address lines A15-A21 - mmw $GPIO_IOCTRL_REG 0xf 0x0 - # set ARM into supervisor mode (SVC32) - # disable IRQ, FIQ - # Do I need this in JTAG mode? - # it really should be done as 'and ~0x1f | 0xd3 but - # openocd does not support this yet - reg cpsr 0xd3 - # /* - # * flush v4 I/D caches - # */ - # mov r0, #0 - # mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - arm mcr 15 0 7 7 0 0x0 - # mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - arm mcr 15 0 8 7 0 0x0 - - # /* - # * disable MMU stuff and caches - # */ - # mrc p15, 0, r0, c1, c0, 0 - arm mrc 15 0 1 0 0 - # bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - # bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - # orr r0, r0, #0x00000002 @ set bit 2 (A) Align - # orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - # orr r0, r0, #0x00400000 @ set bit 22 (U) - # mcr p15, 0, r0, c1, c0, 0 - arm mcr 15 0 1 0 0 0x401002 - # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c - # APB init - # // Setting APB Bus Wait states to 1, set post write - # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40; - mww [expr $APB_ACCESS_WS_REG] 0x40 - # AHB init - # // enable all 6 masters for ARAM - mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 - # // enable all 6 masters for EBUS - mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 - - # ARAM init - # // disable pipeline mode in ARAM - # I don't think this is documented anywhere? - mww $INTC_ARM1_CONTROL_REG 0x1 - # configure clocks - setupPLL - # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART. - setupUART0 - # enable cache - # ? (u-boot does nothing here) - # DDR2 memory init - setupDDR2 - putsUART0 "C100 initialization complete.\n" - echo "C100 initialization complete." -} - -# show current state of watchdog timer -proc showWatchdog {} { - set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND] - set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL] - set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT] - - echo [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]] - echo [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]] - echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]] -} - -# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored) -# this will trigger watchdog reset -# the sw. reset does not work on C100 -# watchdog reset effectively works as hw. reset -proc reboot {} { - set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND] - set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL] - set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT] - - # allow the counter to count to high value before triggering - # this is because regsiter writes are slow over JTAG and - # I don't want to miss the high_bound==curr_count condition - mww $TIMER_WDT_HIGH_BOUND 0xffffff - mww $TIMER_WDT_CURRENT_COUNT 0x0 - echo "JTAG speed lowered to 100kHz" - adapter_khz 100 - mww $TIMER_WDT_CONTROL 0x1 - # wait until the reset - echo -n "Wating for watchdog to trigger..." - #while {[mrw $TIMER_WDT_CONTROL] == 1} { - # echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]] - # sleep 1 - # - #} - while {[c100.cpu curstate] != "running"} { sleep 1} - echo "done." - echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]] -} diff --git a/tcl/target/c100regs.tcl b/tcl/target/c100regs.tcl deleted file mode 100644 index a2c7a60..0000000 --- a/tcl/target/c100regs.tcl +++ /dev/null @@ -1,493 +0,0 @@ -# Note that I basically converted -# u-boot/include/asm-arm/arch/comcerto_100.h -# defines - -# this is a work-around for 'global' not working under Linux -# access registers by calling this routine. -# For example: -# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG] -proc regs {reg} { - return [dict get [regsC100] $reg ] -} - -proc showreg {reg} { - echo [format "0x%x" [dict get [regsC100] $reg ]] -} - -proc regsC100 {} { -#/* memcore */ -#/* device memory base addresses */ -#// device memory sizes -#/* ARAM SIZE=64K */ -dict set regsC100 ARAM_SIZE 0x00010000 -dict set regsC100 ARAM_BASEADDR 0x0A000000 - -#/* Hardware Interface Units */ -dict set regsC100 APB_BASEADDR 0x10000000 -#/* APB_SIZE=16M address range */ -dict set regsC100 APB_SIZE 0x01000000 - -dict set regsC100 EXP_CS0_BASEADDR 0x20000000 -dict set regsC100 EXP_CS1_BASEADDR 0x24000000 -dict set regsC100 EXP_CS2_BASEADDR 0x28000000 -dict set regsC100 EXP_CS3_BASEADDR 0x2C000000 -dict set regsC100 EXP_CS4_BASEADDR 0x30000000 - -dict set regsC100 DDR_BASEADDR 0x80000000 - -dict set regsC100 TDM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000] -dict set regsC100 PHI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000] -dict set regsC100 TDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000] -dict set regsC100 ASA_DDR_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000] -dict set regsC100 ASA_ARAM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000] -dict set regsC100 TIMER_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000] -dict set regsC100 ASD_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000] -dict set regsC100 GPIO_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000] -dict set regsC100 UART0_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000] -dict set regsC100 UART1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000] -dict set regsC100 SPI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000] -dict set regsC100 I2C_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000] -dict set regsC100 INTC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000] -dict set regsC100 CLKCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000] -dict set regsC100 PUI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000] -dict set regsC100 GEMAC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000] -dict set regsC100 IDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000] -dict set regsC100 MEMCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000] -dict set regsC100 ASA_EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000] -dict set regsC100 ASA_AAB_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000] -dict set regsC100 GEMAC1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000] -dict set regsC100 EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000] -dict set regsC100 MDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000] - - -#//////////////////////////////////////////////////////////// -#// AHB block // -#//////////////////////////////////////////////////////////// -dict set regsC100 ASA_ARAM_PRI_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00] -dict set regsC100 ASA_ARAM_TC_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04] -dict set regsC100 ASA_ARAM_TC_CR_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08] -dict set regsC100 ASA_ARAM_STAT_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C] - -dict set regsC100 ASA_EBUS_PRI_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00] -dict set regsC100 ASA_EBUS_TC_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04] -dict set regsC100 ASA_EBUS_TC_CR_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08] -dict set regsC100 ASA_EBUS_STAT_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C] - -dict set regsC100 IDMA_MASTER 0 -dict set regsC100 TDMA_MASTER 1 -dict set regsC100 USBIPSEC_MASTER 2 -dict set regsC100 ARM0_MASTER 3 -dict set regsC100 ARM1_MASTER 4 -dict set regsC100 MDMA_MASTER 5 - -#define IDMA_PRIORITY(level) (level) -#define TDM_PRIORITY(level) (level << 4) -#define USBIPSEC_PRIORITY(level) (level << 8) -#define ARM0_PRIORITY(level) (level << 12) -#define ARM1_PRIORITY(level) (level << 16) -#define MDMA_PRIORITY(level) (level << 20) - -dict set regsC100 ASA_TC_REQIDMAEN [expr 1<<18] -dict set regsC100 ASA_TC_REQTDMEN [expr 1<<19] -dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20] -dict set regsC100 ASA_TC_REQARM0EN [expr 1<<21] -dict set regsC100 ASA_TC_REQARM1EN [expr 1<<22] -dict set regsC100 ASA_TC_REQMDMAEN [expr 1<<23] - -dict set regsC100 MEMORY_BASE_ADDR 0x80000000 -dict set regsC100 MEMORY_MAX_ADDR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10] -dict set regsC100 MEMORY_CR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14] -dict set regsC100 ROM_REMAP_EN 0x1 - -#define HAL_asb_priority(level) \ -#*(volatile unsigned *)ASA_PRI_REG = level - -#define HAL_aram_priority(level) \ -#*(volatile unsigned *)ASA_ARAM_PRI_REG = level - -#define HAL_aram_arbitration(arbitration_mask) \ -#*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask - -#define HAL_aram_defmaster(mask) \ -#*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24) - -#//////////////////////////////////////////////////////////// -#// INTC block // -#//////////////////////////////////////////////////////////// - -dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18] - -#//////////////////////////////////////////////////////////// -#// TIMER block // -#//////////////////////////////////////////////////////////// - -dict set regsC100 TIMER0_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00] -dict set regsC100 TIMER0_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04] -dict set regsC100 TIMER1_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08] -dict set regsC100 TIMER1_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C] - -dict set regsC100 TIMER2_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18] -dict set regsC100 TIMER2_LBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10] -dict set regsC100 TIMER2_HBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14] -dict set regsC100 TIMER2_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C] - -dict set regsC100 TIMER3_LOBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20] -dict set regsC100 TIMER3_HIBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24] -dict set regsC100 TIMER3_CTRL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28] -dict set regsC100 TIMER3_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C] - -dict set regsC100 TIMER_MASK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40] -dict set regsC100 TIMER_STATUS [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50] -dict set regsC100 TIMER_ACK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50] -dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0] -dict set regsC100 TIMER_WDT_CONTROL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4] -dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8] - - - -#//////////////////////////////////////////////////////////// -#// EBUS block -#//////////////////////////////////////////////////////////// - -dict set regsC100 EX_SWRST_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00] -dict set regsC100 EX_CSEN_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04] -dict set regsC100 EX_CS0_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08] -dict set regsC100 EX_CS1_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C] -dict set regsC100 EX_CS2_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10] -dict set regsC100 EX_CS3_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14] -dict set regsC100 EX_CS4_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18] -dict set regsC100 EX_CS0_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C] -dict set regsC100 EX_CS1_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20] -dict set regsC100 EX_CS2_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24] -dict set regsC100 EX_CS3_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28] -dict set regsC100 EX_CS4_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C] -dict set regsC100 EX_CS0_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30] -dict set regsC100 EX_CS1_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34] -dict set regsC100 EX_CS2_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38] -dict set regsC100 EX_CS3_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C] -dict set regsC100 EX_CS4_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40] -dict set regsC100 EX_CS0_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44] -dict set regsC100 EX_CS1_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48] -dict set regsC100 EX_CS2_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C] -dict set regsC100 EX_CS3_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50] -dict set regsC100 EX_CS4_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54] -dict set regsC100 EX_CS0_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58] -dict set regsC100 EX_CS1_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C] -dict set regsC100 EX_CS2_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60] -dict set regsC100 EX_CS3_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64] -dict set regsC100 EX_CS4_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68] -dict set regsC100 EX_CLOCK_DIV_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C] - -dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100] -dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100] -dict set regsC100 EX_CSFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104] -dict set regsC100 EX_WRFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108] -dict set regsC100 EX_RDFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C] - - -dict set regsC100 EX_CLK_EN 0x00000001 -dict set regsC100 EX_CSBOOT_EN 0x00000002 -dict set regsC100 EX_CS0_EN 0x00000002 -dict set regsC100 EX_CS1_EN 0x00000004 -dict set regsC100 EX_CS2_EN 0x00000008 -dict set regsC100 EX_CS3_EN 0x00000010 -dict set regsC100 EX_CS4_EN 0x00000020 - -dict set regsC100 EX_MEM_BUS_8 0x00000000 -dict set regsC100 EX_MEM_BUS_16 0x00000002 -dict set regsC100 EX_MEM_BUS_32 0x00000004 -dict set regsC100 EX_CS_HIGH 0x00000008 -dict set regsC100 EX_WE_HIGH 0x00000010 -dict set regsC100 EX_RE_HIGH 0x00000020 -dict set regsC100 EX_ALE_MODE 0x00000040 -dict set regsC100 EX_STRB_MODE 0x00000080 -dict set regsC100 EX_DM_MODE 0x00000100 -dict set regsC100 EX_NAND_MODE 0x00000200 -dict set regsC100 EX_RDY_EN 0x00000400 -dict set regsC100 EX_RDY_EDGE 0x00000800 - -#//////////////////////////////////////////////////////////// -#// GPIO block -#//////////////////////////////////////////////////////////// - -# GPIO outputs register -dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00] -# GPIO Output Enable register -dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04] -dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08] -dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C] -# GPIO input register -dict set regsC100 GPIO_INPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10] -dict set regsC100 APB_ACCESS_WS_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14] -dict set regsC100 MUX_CONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18] -dict set regsC100 SYSCONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C] -dict set regsC100 GPIO_ARM_ID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30] -dict set regsC100 GPIO_BOOTSTRAP_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40] -dict set regsC100 GPIO_LOCK_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38] -dict set regsC100 GPIO_IOCTRL_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44] -dict set regsC100 GPIO_DEVID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50] - -dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001 -dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002 -dict set regsC100 GPIO_IOCTRL_A19A21 0x00000004 -dict set regsC100 GPIO_IOCTRL_TMREVT0 0x00000008 -dict set regsC100 GPIO_IOCTRL_TMREVT1 0x00000010 -dict set regsC100 GPIO_IOCTRL_GPBT3 0x00000020 -dict set regsC100 GPIO_IOCTRL_I2C 0x00000040 -dict set regsC100 GPIO_IOCTRL_UART0 0x00000080 -dict set regsC100 GPIO_IOCTRL_UART1 0x00000100 -dict set regsC100 GPIO_IOCTRL_SPI 0x00000200 -dict set regsC100 GPIO_IOCTRL_HBMODE 0x00000400 - -dict set regsC100 GPIO_IOCTRL_VAL 0x55555555 - -dict set regsC100 GPIO_0 0x01 -dict set regsC100 GPIO_1 0x02 -dict set regsC100 GPIO_2 0x04 -dict set regsC100 GPIO_3 0x08 -dict set regsC100 GPIO_4 0x10 -dict set regsC100 GPIO_5 0x20 -dict set regsC100 GPIO_6 0x40 -dict set regsC100 GPIO_7 0x80 - -dict set regsC100 GPIO_RISING_EDGE 1 -dict set regsC100 GPIO_FALLING_EDGE 2 -dict set regsC100 GPIO_BOTH_EDGES 3 - -#//////////////////////////////////////////////////////////// -#// UART -#//////////////////////////////////////////////////////////// - -dict set regsC100 UART0_RBR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_THR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_DLL [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_IER [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04] -dict set regsC100 UART0_DLH [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04] -dict set regsC100 UART0_IIR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08] -dict set regsC100 UART0_FCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08] -dict set regsC100 UART0_LCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C] -dict set regsC100 UART0_MCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10] -dict set regsC100 UART0_LSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14] -dict set regsC100 UART0_MSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18] -dict set regsC100 UART0_SCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C] - -dict set regsC100 UART1_RBR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_THR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_DLL [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_IER [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04] -dict set regsC100 UART1_DLH [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04] -dict set regsC100 UART1_IIR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08] -dict set regsC100 UART1_FCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08] -dict set regsC100 UART1_LCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C] -dict set regsC100 UART1_MCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10] -dict set regsC100 UART1_LSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14] -dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18] -dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C] - -# /* default */ -dict set regsC100 LCR_CHAR_LEN_5 0x00 -dict set regsC100 LCR_CHAR_LEN_6 0x01 -dict set regsC100 LCR_CHAR_LEN_7 0x02 -dict set regsC100 LCR_CHAR_LEN_8 0x03 -#/* One stop bit! - default */ -dict set regsC100 LCR_ONE_STOP 0x00 -#/* Two stop bit! */ -dict set regsC100 LCR_TWO_STOP 0x04 -#/* Parity Enable */ -dict set regsC100 LCR_PEN 0x08 -dict set regsC100 LCR_PARITY_NONE 0x00 -#/* Even Parity Select */ -dict set regsC100 LCR_EPS 0x10 -#/* Enable Parity Stuff */ -dict set regsC100 LCR_PS 0x20 -#/* Start Break */ -dict set regsC100 LCR_SBRK 0x40 -#/* Parity Stuff Bit */ -dict set regsC100 LCR_PSB 0x80 -#/* UART 16550 Divisor Latch Assess */ -dict set regsC100 LCR_DLAB 0x80 - -#/* FIFO Error Status */ -dict set regsC100 LSR_FIFOE [expr 1 << 7] -#/* Transmitter Empty */ -dict set regsC100 LSR_TEMT [expr 1 << 6] -#/* Transmit Data Request */ -dict set regsC100 LSR_TDRQ [expr 1 << 5] -#/* Break Interrupt */ -dict set regsC100 LSR_BI [expr 1 << 4] -#/* Framing Error */ -dict set regsC100 LSR_FE [expr 1 << 3] -#/* Parity Error */ -dict set regsC100 LSR_PE [expr 1 << 2] -#/* Overrun Error */ -dict set regsC100 LSR_OE [expr 1 << 1] -#/* Data Ready */ -dict set regsC100 LSR_DR [expr 1 << 0] - -#/* DMA Requests Enable */ -dict set regsC100 IER_DMAE [expr 1 << 7] -#/* UART Unit Enable */ -dict set regsC100 IER_UUE [expr 1 << 6] -#/* NRZ coding Enable */ -dict set regsC100 IER_NRZE [expr 1 << 5] -#/* Receiver Time Out Interrupt Enable */ -dict set regsC100 IER_RTIOE [expr 1 << 4] -#/* Modem Interrupt Enable */ -dict set regsC100 IER_MIE [expr 1 << 3] -#/* Receiver Line Status Interrupt Enable */ -dict set regsC100 IER_RLSE [expr 1 << 2] -#/* Transmit Data request Interrupt Enable */ -dict set regsC100 IER_TIE [expr 1 << 1] -#/* Receiver Data Available Interrupt Enable */ -dict set regsC100 IER_RAVIE [expr 1 << 0] - -#/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES1 [expr 1 << 7] -#/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES0 [expr 1 << 6] -#/* Time Out Detected */ -dict set regsC100 IIR_TOD [expr 1 << 3] -#/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID2 [expr 1 << 2] -#/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID1 [expr 1 << 1] -#/* Interrupt Pending (active low) */ -dict set regsC100 IIR_IP [expr 1 << 0] - -#/* UART 16550 FIFO Control Register */ -dict set regsC100 FCR_FIFOEN 0x01 -dict set regsC100 FCR_RCVRRES 0x02 -dict set regsC100 FCR_XMITRES 0x04 - -#/* Interrupt Enable Register */ -#// UART 16550 -#// Enable Received Data Available Interrupt -dict set regsC100 IER_RXTH 0x01 -#// Enable Transmitter Empty Interrupt -dict set regsC100 IER_TXTH 0x02 - - - -#//////////////////////////////////////////////////////////// -#// CLK + RESET block -#//////////////////////////////////////////////////////////// - -dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00] -dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04] -dict set regsC100 CLKCORE_PLL_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08] -dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C] -dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10] -dict set regsC100 CLKCORE_FSYNC_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14] -dict set regsC100 CLKCORE_CLK_PWR_DWN [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18] -dict set regsC100 CLKCORE_RNG_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C] -dict set regsC100 CLKCORE_RNG_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20] -dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24] -dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40] - -dict set regsC100 ARM_PLL_BY_CTRL 0x80000000 -dict set regsC100 ARM_AHB_BYP 0x04000000 -dict set regsC100 PLL_DISABLE 0x02000000 -dict set regsC100 PLL_CLK_BYPASS 0x01000000 - -dict set regsC100 AHB_PLL_BY_CTRL 0x80000000 -dict set regsC100 DIV_BYPASS 0x40000000 -dict set regsC100 SYNC_MODE 0x20000000 - -dict set regsC100 EPHY_CLKDIV_BYPASS 0x00200000 -dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT 16 -dict set regsC100 PUI_CLKDIV_BYPASS 0x00004000 -dict set regsC100 PUI_CLKDIV_SRCCLK 0x00002000 -dict set regsC100 PUI_CLKDIV_RATIO_SHIFT 8 -dict set regsC100 PCI_CLKDIV_BYPASS 0x00000020 -dict set regsC100 PCI_CLKDIV_RATIO_SHIFT 0 - -dict set regsC100 ARM0_CLK_PD 0x00200000 -dict set regsC100 ARM1_CLK_PD 0x00100000 -dict set regsC100 EPHY_CLK_PD 0x00080000 -dict set regsC100 TDM_CLK_PD 0x00040000 -dict set regsC100 PUI_CLK_PD 0x00020000 -dict set regsC100 PCI_CLK_PD 0x00010000 -dict set regsC100 MDMA_AHBCLK_PD 0x00000400 -dict set regsC100 I2CSPI_AHBCLK_PD 0x00000200 -dict set regsC100 UART_AHBCLK_PD 0x00000100 -dict set regsC100 IPSEC_AHBCLK_PD 0x00000080 -dict set regsC100 TDM_AHBCLK_PD 0x00000040 -dict set regsC100 USB1_AHBCLK_PD 0x00000020 -dict set regsC100 USB0_AHBCLK_PD 0x00000010 -dict set regsC100 GEMAC1_AHBCLK_PD 0x00000008 -dict set regsC100 GEMAC0_AHBCLK_PD 0x00000004 -dict set regsC100 PUI_AHBCLK_PD 0x00000002 -dict set regsC100 HIF_AHBCLK_PD 0x00000001 - -dict set regsC100 ARM1_DIV_BP 0x00001000 -dict set regsC100 ARM1_DIV_VAL_SHIFT 8 -dict set regsC100 ARM0_DIV_BP 0x00000010 -dict set regsC100 ARM0_DIV_VAL_SHIFT 0 - -dict set regsC100 AHBCLK_PLL_LOCK 0x00000002 -dict set regsC100 FCLK_PLL_LOCK 0x00000001 - - -#// reset block -dict set regsC100 BLOCK_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x100] -dict set regsC100 CSP_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x104] - -dict set regsC100 RNG_RST 0x1000 -dict set regsC100 IPSEC_RST 0x0800 -dict set regsC100 DDR_RST 0x0400 -dict set regsC100 USB1_PHY_RST 0x0200 -dict set regsC100 USB0_PHY_RST 0x0100 -dict set regsC100 USB1_RST 0x0080 -dict set regsC100 USB0_RST 0x0040 -dict set regsC100 GEMAC1_RST 0x0020 -dict set regsC100 GEMAC0_RST 0x0010 -dict set regsC100 TDM_RST 0x0008 -dict set regsC100 PUI_RST 0x0004 -dict set regsC100 HIF_RST 0x0002 -dict set regsC100 PCI_RST 0x0001 - -#//////////////////////////////////////////////////////////////// -#// DDR CONTROLLER block -#//////////////////////////////////////////////////////////////// - -dict set regsC100 DDR_CONFIG_BASEADDR 0x0D000000 -dict set regsC100 DENALI_CTL_00_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00] -dict set regsC100 DENALI_CTL_01_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08] -dict set regsC100 DENALI_CTL_02_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10] -dict set regsC100 DENALI_CTL_03_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18] -dict set regsC100 DENALI_CTL_04_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20] -dict set regsC100 DENALI_CTL_05_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28] -dict set regsC100 DENALI_CTL_06_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30] -dict set regsC100 DENALI_CTL_07_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38] -dict set regsC100 DENALI_CTL_08_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40] -dict set regsC100 DENALI_CTL_09_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48] -dict set regsC100 DENALI_CTL_10_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50] -dict set regsC100 DENALI_CTL_11_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58] -dict set regsC100 DENALI_CTL_12_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60] -dict set regsC100 DENALI_CTL_13_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68] -dict set regsC100 DENALI_CTL_14_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70] -dict set regsC100 DENALI_CTL_15_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78] -dict set regsC100 DENALI_CTL_16_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80] -dict set regsC100 DENALI_CTL_17_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88] -dict set regsC100 DENALI_CTL_18_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90] -dict set regsC100 DENALI_CTL_19_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98] -dict set regsC100 DENALI_CTL_20_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0] - -# 32-bit value -dict set regsC100 DENALI_READY_CHECK [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44] -# 8-bit -dict set regsC100 DENALI_WR_DQS [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D] -# 8-bit -dict set regsC100 DENALI_DQS_OUT [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A] -# 8-bit -dict set regsC100 DENALI_DQS_DELAY0 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F] -# 8-bit -dict set regsC100 DENALI_DQS_DELAY1 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50] -# 8-bit -dict set regsC100 DENALI_DQS_DELAY2 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51] -# 8-bit -dict set regsC100 DENALI_DQS_DELAY3 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52] - - -# end of proc regsC100 -} diff --git a/tcl/target/cc2538.cfg b/tcl/target/cc2538.cfg deleted file mode 100755 index 81593c1..0000000 --- a/tcl/target/cc2538.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# Config for Texas Instruments low power RF SoC CC2538 -# http://www.ti.com/lit/pdf/swru319 - -if { [info exists CHIPNAME] } { - set CHIPNAME $CHIPNAME -} else { - set CHIPNAME cc2538 -} - -if { [info exists JRC_TAPID] } { - set JRC_TAPID $JRC_TAPID -} else { - set JRC_TAPID 0x8B96402F -} - -source [find target/cc26xx.cfg] diff --git a/tcl/target/cc26xx.cfg b/tcl/target/cc26xx.cfg deleted file mode 100755 index 1492e6a..0000000 --- a/tcl/target/cc26xx.cfg +++ /dev/null @@ -1,43 +0,0 @@ -# Config for Texas Instruments low power SoC CC26xx family - -adapter_khz 100 - -source [find target/icepick.cfg] -source [find target/ti-cjtag.cfg] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME cc26xx -} - -# -# Main DAP -# -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x4BA00477 -} -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" - -# -# ICEpick-C (JTAG route controller) -# -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x1B99A02F -} -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version -# A start sequence is needed to change from cJTAG (Compact JTAG) to -# 4-pin JTAG before talking via JTAG commands -jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" -jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc" - -# -# Cortex-M3 target -# -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap diff --git a/tcl/target/cc32xx.cfg b/tcl/target/cc32xx.cfg deleted file mode 100755 index 154bf91..0000000 --- a/tcl/target/cc32xx.cfg +++ /dev/null @@ -1,53 +0,0 @@ -# Config for Texas Instruments SoC CC32xx family - -source [find target/swj-dp.tcl] - -adapter_khz 100 - -source [find target/icepick.cfg] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME cc32xx -} - -# -# Main DAP -# -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - if {[using_jtag]} { - set _DAP_TAPID 0x4BA00477 - } else { - set _DAP_TAPID 0x2BA01477 - } -} - -if {[using_jtag]} { - jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable - jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" -} else { - swj_newdap $_CHIPNAME dap -expected-id $_DAP_TAPID -} - -# -# ICEpick-C (JTAG route controller) -# -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0B97C02F -} - -if {[using_jtag]} { - jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version - jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" -} - -# -# Cortex-M3 target -# -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap diff --git a/tcl/target/cs351x.cfg b/tcl/target/cs351x.cfg deleted file mode 100644 index cb05da2..0000000 --- a/tcl/target/cs351x.cfg +++ /dev/null @@ -1,31 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME cs351x -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x00526fa1 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# Create the GDB Target. -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME - -# There is 16K of SRAM on this chip -# FIXME: flash programming is not working by using this work area. So comment this out for now. -#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1 - -# This chip has a DCC ... use it -arm7_9 dcc_downloads enable - diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg deleted file mode 100644 index 859a925..0000000 --- a/tcl/target/davinci.cfg +++ /dev/null @@ -1,377 +0,0 @@ -# -# Utility code for DaVinci-family chips -# - -# davinci_pinmux: assigns PINMUX$reg <== $value -proc davinci_pinmux {soc reg value} { - mww [expr [dict get $soc sysbase] + 4 * $reg] $value -} - -source [find mem_helper.tcl] - -# -# pll_setup: initialize PLL -# - pll_addr ... physical addr of controller -# - mult ... pll multiplier -# - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers -# -# For PLLs that don't have a given register (e.g. plldiv8), or where a -# given divider is non-programmable, caller provides *NO* config mapping. -# - -# PLL version 0x02: tested on dm355 -# REVISIT: On dm6446/dm357 the PLLRST polarity is different. -proc pll_v02_setup {pll_addr mult config} { - set pll_ctrl_addr [expr $pll_addr + 0x100] - set pll_ctrl [mrw $pll_ctrl_addr] - - # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator - # NOTE: this assumes we should clear that bit - set pll_ctrl [expr $pll_ctrl & ~0x0100] - mww $pll_ctrl_addr $pll_ctrl - - # 2 - clear PLLENSRC (bit 5) - set pll_ctrl [expr $pll_ctrl & ~0x0020] - mww $pll_ctrl_addr $pll_ctrl - - # 3 - clear PLLEN (bit 0) ... enter bypass mode - set pll_ctrl [expr $pll_ctrl & ~0x0001] - mww $pll_ctrl_addr $pll_ctrl - - # 4 - wait at least 4 refclk cycles - sleep 1 - - # 5 - set PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl | 0x0008] - mww $pll_ctrl_addr $pll_ctrl - - # 6 - set PLLDIS (bit 4) - set pll_ctrl [expr $pll_ctrl | 0x0010] - mww $pll_ctrl_addr $pll_ctrl - - # 7 - clear PLLPWRDN (bit 1) - set pll_ctrl [expr $pll_ctrl & ~0x0002] - mww $pll_ctrl_addr $pll_ctrl - - # 8 - clear PLLDIS (bit 4) - set pll_ctrl [expr $pll_ctrl & ~0x0010] - mww $pll_ctrl_addr $pll_ctrl - - # 9 - optional: write prediv, postdiv, and pllm - # NOTE: for dm355 PLL1, postdiv is controlled via MISC register - mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff] - if { [dict exists $config prediv] } { - set div [dict get $config prediv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0114] $div - } - if { [dict exists $config postdiv] } { - set div [dict get $config postdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0128] $div - } - - # 10 - optional: set plldiv1, plldiv2, ... - # NOTE: this assumes some registers have their just-reset values: - # - PLLSTAT.GOSTAT is clear when we enter - # - ALNCTL has everything set - set go 0 - if { [dict exists $config div1] } { - set div [dict get $config div1] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0118] $div - set go 1 - } - if { [dict exists $config div2] } { - set div [dict get $config div2] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div - set go 1 - } - if { [dict exists $config div3] } { - set div [dict get $config div3] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0120] $div - set go 1 - } - if { [dict exists $config div4] } { - set div [dict get $config div4] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0160] $div - set go 1 - } - if { [dict exists $config div5] } { - set div [dict get $config div5] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0164] $div - set go 1 - } - if {$go != 0} { - # write pllcmd.GO; poll pllstat.GO - mww [expr $pll_addr + 0x0138] 0x01 - set pllstat [expr $pll_addr + 0x013c] - while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } - } - mww [expr $pll_addr + 0x0138] 0x00 - - # 11 - wait at least 5 usec for reset to finish - # (assume covered by overheads including JTAG messaging) - - # 12 - clear PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl & ~0x0008] - mww $pll_ctrl_addr $pll_ctrl - - # 13 - wait at least 8000 refclk cycles for PLL to lock - # if we assume 24 MHz (slowest osc), that's 1/3 msec - sleep 3 - - # 14 - set PLLEN (bit 0) ... leave bypass mode - set pll_ctrl [expr $pll_ctrl | 0x0001] - mww $pll_ctrl_addr $pll_ctrl -} - -# PLL version 0x03: tested on dm365 -proc pll_v03_setup {pll_addr mult config} { - set pll_ctrl_addr [expr $pll_addr + 0x100] - set pll_secctrl_addr [expr $pll_addr + 0x108] - set pll_ctrl [mrw $pll_ctrl_addr] - - # 1 - power up the PLL - set pll_ctrl [expr $pll_ctrl & ~0x0002] - mww $pll_ctrl_addr $pll_ctrl - - # 2 - clear PLLENSRC (bit 5) - set pll_ctrl [expr $pll_ctrl & ~0x0020] - mww $pll_ctrl_addr $pll_ctrl - - # 2 - clear PLLEN (bit 0) ... enter bypass mode - set pll_ctrl [expr $pll_ctrl & ~0x0001] - mww $pll_ctrl_addr $pll_ctrl - - # 3 - wait at least 4 refclk cycles - sleep 1 - - # 4 - set PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl | 0x0008] - mww $pll_ctrl_addr $pll_ctrl - - # 5 - wait at least 5 usec - sleep 1 - - # 6 - clear PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl & ~0x0008] - mww $pll_ctrl_addr $pll_ctrl - - # 9 - optional: write prediv, postdiv, and pllm - mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] - if { [dict exists $config prediv] } { - set div [dict get $config prediv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0114] $div - } - if { [dict exists $config postdiv] } { - set div [dict get $config postdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0128] $div - } - - # 10 - write start sequence to PLLSECCTL - mww $pll_secctrl_addr 0x00470000 - mww $pll_secctrl_addr 0x00460000 - mww $pll_secctrl_addr 0x00400000 - mww $pll_secctrl_addr 0x00410000 - - # 11 - optional: set plldiv1, plldiv2, ... - # NOTE: this assumes some registers have their just-reset values: - # - PLLSTAT.GOSTAT is clear when we enter - set aln 0 - if { [dict exists $config div1] } { - set div [dict get $config div1] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0118] $div - set aln [expr $aln | 0x1] - } else { - mww [expr $pll_addr + 0x0118] 0 - } - if { [dict exists $config div2] } { - set div [dict get $config div2] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div - set aln [expr $aln | 0x2] - } else { - mww [expr $pll_addr + 0x011c] 0 - } - if { [dict exists $config div3] } { - set div [dict get $config div3] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0120] $div - set aln [expr $aln | 0x4] - } else { - mww [expr $pll_addr + 0x0120] 0 - } - if { [dict exists $config oscdiv] } { - set div [dict get $config oscdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0124] $div - } else { - mww [expr $pll_addr + 0x0124] 0 - } - if { [dict exists $config div4] } { - set div [dict get $config div4] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0160] $div - set aln [expr $aln | 0x8] - } else { - mww [expr $pll_addr + 0x0160] 0 - } - if { [dict exists $config div5] } { - set div [dict get $config div5] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0164] $div - set aln [expr $aln | 0x10] - } else { - mww [expr $pll_addr + 0x0164] 0 - } - if { [dict exists $config div6] } { - set div [dict get $config div6] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0168] $div - set aln [expr $aln | 0x20] - } else { - mww [expr $pll_addr + 0x0168] 0 - } - if { [dict exists $config div7] } { - set div [dict get $config div7] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x016c] $div - set aln [expr $aln | 0x40] - } else { - mww [expr $pll_addr + 0x016c] 0 - } - if { [dict exists $config div8] } { - set div [dict get $config div8] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0170] $div - set aln [expr $aln | 0x80] - } else { - mww [expr $pll_addr + 0x0170] 0 - } - if { [dict exists $config div9] } { - set div [dict get $config div9] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0174] $div - set aln [expr $aln | 0x100] - } else { - mww [expr $pll_addr + 0x0174] 0 - } - if {$aln != 0} { - # clear pllcmd.GO - mww [expr $pll_addr + 0x0138] 0x00 - # write alingment flags - mww [expr $pll_addr + 0x0140] $aln - # write pllcmd.GO; poll pllstat.GO - mww [expr $pll_addr + 0x0138] 0x01 - set pllstat [expr $pll_addr + 0x013c] - while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } - } - mww [expr $pll_addr + 0x0138] 0x00 - set addr [dict get $config ctladdr] - while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 } - - # 12 - set PLLEN (bit 0) ... leave bypass mode - set pll_ctrl [expr $pll_ctrl | 0x0001] - mww $pll_ctrl_addr $pll_ctrl -} - -# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain -# modules can be enabled. - -# prepare a non-DSP module to be enabled; finish with psc_go -proc psc_enable {module} { - set psc_addr 0x01c41000 - # write MDCTL - mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f -} - -# prepare a non-DSP module to be reset; finish with psc_go -proc psc_reset {module} { - set psc_addr 0x01c41000 - # write MDCTL - mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f -} - -# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc -proc psc_go {} { - set psc_addr 0x01c41000 - set ptstat_addr [expr $psc_addr + 0x0128] - - # just in case PTSTAT.go isn't clear - while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } - - # write PTCMD.go ... ignoring any DSP power domain - mww [expr $psc_addr + 0x0120] 1 - - # wait for PTSTAT.go to clear (again ignoring DSP power domain) - while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } -} - -# -# A reset using only SRST is a "Warm Reset", resetting everything in the -# chip except ARM emulation (and everything _outside_ the chip that hooks -# up to SRST). But many boards don't expose SRST via their JTAG connectors -# (it's not present on TI-14 headers). -# -# From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except -# without any board-wide side effects, since it's triggered using JTAG using -# either (a) ARM watchdog timer, or (b) ICEpick. -# -proc davinci_wdog_reset {} { - set timer2_phys 0x01c21c00 - - # NOTE -- on entry - # - JTAG communication with the ARM *must* be working OK; this - # may imply using adaptive clocking or disabling WFI-in-idle - # - current target must be the DaVinci ARM - # - that ARM core must be halted - # - timer2 clock is still enabled (PSC 29 on most chips) - - # - # Part I -- run regardless of being halted via JTAG - # - # NOTE: for now, we assume there's no DSP that could control the - # watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog - # suspend signal is controlled via ARM emulation suspend. - # - - # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt - mww phys [expr $timer2_phys + 0x28] 0x00004000 - - # - # Part II -- in case watchdog hasn't been set up - # - - # TCR: disable, force internal clock source - mww phys [expr $timer2_phys + 0x20] 0 - - # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state) - mww phys [expr $timer2_phys + 0x24] 0 - mww phys [expr $timer2_phys + 0x24] 0x110b - - # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers - # so watchdog triggers ASAP - mww phys [expr $timer2_phys + 0x10] 0 - mww phys [expr $timer2_phys + 0x14] 0 - mww phys [expr $timer2_phys + 0x18] 0 - mww phys [expr $timer2_phys + 0x1c] 0 - - # WDTCR: put into pre-active state, then active - mww phys [expr $timer2_phys + 0x28] 0xa5c64000 - mww phys [expr $timer2_phys + 0x28] 0xda7e4000 - - # - # Part III -- it's ready to rumble - # - - # WDTCR: write invalid WDKEY to trigger reset - mww phys [expr $timer2_phys + 0x28] 0x00004000 -} diff --git a/tcl/target/dragonite.cfg b/tcl/target/dragonite.cfg deleted file mode 100644 index 750fd64..0000000 --- a/tcl/target/dragonite.cfg +++ /dev/null @@ -1,31 +0,0 @@ -###################################### -# Target: Marvell Dragonite CPU core -###################################### - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dragonite -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x121003d3 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME - -reset_config trst_and_srst -adapter_nsrst_delay 200 -jtag_ntrst_delay 200 - diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg deleted file mode 100644 index 6f32223..0000000 --- a/tcl/target/dsp56321.cfg +++ /dev/null @@ -1,37 +0,0 @@ -# Script for freescale DSP56321 -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dsp56321 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a big endian - set _ENDIAN big -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x1181501d -} - -#jtag speed -adapter_khz 4500 - -#has only srst -reset_config srst_only - -#jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID - -#target configuration -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME - -#working area at base of ram -$_TARGETNAME configure -work-area-virt 0 diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg deleted file mode 100644 index 0c491fa..0000000 --- a/tcl/target/dsp568013.cfg +++ /dev/null @@ -1,76 +0,0 @@ -# Script for freescale DSP568013 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dsp568013 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a big endian - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x01f2401d -} - -#jtag speed -adapter_khz 800 - -reset_config srst_only - -#MASTER tap -jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID - -#CORE tap -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004 - -#target configuration - There is only 1 tap at a time, hence only 1 target is defined. -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME - -# Setup the interesting tap -# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this) -jtag configure $_CHIPNAME.chp -event setup " - jtag tapenable $_TARGETNAME - poll off -" - -#select CORE tap by modifying the TLM register. -#to be used when MASTER tap is selected. -jtag configure $_TARGETNAME -event tap-enable " - irscan $_CHIPNAME.chp 0x05; - drscan $_CHIPNAME.chp 4 0x02; - jtag tapdisable $_CHIPNAME.chp; -" - -#select MASTER tap by modifying the TLM register. -#to be used when CORE tap is selected. -jtag configure $_CHIPNAME.chp -event tap-enable " - irscan $_TARGETNAME 0x08; - drscan $_TARGETNAME 4 0x1; - jtag tapdisable $_TARGETNAME; -" - -#disables the master tap -jtag configure $_TARGETNAME -event tap-disable " -" -#TODO FIND SMARTER WAY. - -jtag configure $_CHIPNAME.chp -event tap-disable " -" -#TODO FIND SMARTER WAY. - - -#working area at base of ram -$_TARGETNAME configure -work-area-virt 0 - -#setup flash -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME - diff --git a/tcl/target/dsp568037.cfg b/tcl/target/dsp568037.cfg deleted file mode 100644 index 01194d0..0000000 --- a/tcl/target/dsp568037.cfg +++ /dev/null @@ -1,72 +0,0 @@ -# Script for freescale DSP568037 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dsp568037 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a big endian - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x01f2801d -} - -#jtag speed -adapter_khz 800 - -reset_config srst_only - -#MASTER tap -jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID - -#CORE tap -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004 - -#target configuration - There is only 1 tap at a time, hence only 1 target is defined. -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME - -# Setup the interesting tap -jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME" - -#select CORE tap by modifying the TLM register. -#to be used when MASTER tap is selected. -jtag configure $_TARGETNAME -event tap-enable " - irscan $_CHIPNAME.chp 0x05; - drscan $_CHIPNAME.chp 4 0x02; - jtag tapdisable $_CHIPNAME.chp; -" - -#select MASTER tap by modifying the TLM register. -#to be used when CORE tap is selected. -jtag configure $_CHIPNAME.chp -event tap-enable " - irscan $_TARGETNAME 0x08; - drscan $_TARGETNAME 4 0x1; - jtag tapdisable $_TARGETNAME; -" - -#disables the master tap -jtag configure $_TARGETNAME -event tap-disable " -" -#TODO FIND SMARTER WAY. - -jtag configure $_CHIPNAME.chp -event tap-disable " -" -#TODO FIND SMARTER WAY. - - -#working area at base of ram -$_TARGETNAME configure -work-area-virt 0 - -#setup flash -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME - diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg deleted file mode 100644 index 33610d5..0000000 --- a/tcl/target/efm32.cfg +++ /dev/null @@ -1,43 +0,0 @@ -# -# efm32 target -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME efm32 -} - -# Work-area is a space in RAM used for flash programming -# By default use 2kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x800 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x2ba01477 -} - -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID - -adapter_khz 1000 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/efm32_stlink.cfg b/tcl/target/efm32_stlink.cfg deleted file mode 100644 index 230155e..0000000 --- a/tcl/target/efm32_stlink.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/efm32_stlink.cfg is deprecated, please switch to target/efm32.cfg" -source [find target/efm32.cfg] diff --git a/tcl/target/em357.cfg b/tcl/target/em357.cfg deleted file mode 100644 index 24ffb04..0000000 --- a/tcl/target/em357.cfg +++ /dev/null @@ -1,76 +0,0 @@ -# -# Target configuration for the Silicon Labs EM357 chips -# - -# -# em357 family supports JTAG and SWD transports -# -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME em357 -} - -# Work-area is a space in RAM used for flash programming -# By default use 4kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x1000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x3ba00477 - } else { - set _CPUTAPID 0x1ba00477 - } -} - -if { [info exists BSTAPID] } { - set _BSTAPID $BSTAPID -} else { - set _BSTAPID 0x069a962b -} - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME em358 -} - -if { [info exists FLASHSIZE] } { - set _FLASHSIZE $FLASHSIZE -} else { - set _FLASHSIZE 0x30000 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID -if { [using_jtag] } { - swj_newdap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME em357 0x08000000 $_FLASHSIZE 0 0 $_TARGETNAME - -if { ![using_hla]} { -# according to errata, we need to use vectreset rather than sysresetreq to avoid lockup -# There is a bug in the chip, which means that when using external debuggers the chip -# may lock up in certain CPU clock modes. Affected modes are operating the CPU at -# 24MHz derived from the 24MHz crystal, or 12MHz derived from the high frequency RC -# oscillator. If an external debugger tool asserts SYSRESETREQ, the chip will lock up and -# require a pin reset or power cycle. -# -# for details, refer to: -# http://www.silabs.com/Support%20Documents/TechnicalDocs/EM35x-Errata.pdf - cortex_m reset_config vectreset -} diff --git a/tcl/target/em358.cfg b/tcl/target/em358.cfg deleted file mode 100644 index 92e65a4..0000000 --- a/tcl/target/em358.cfg +++ /dev/null @@ -1,17 +0,0 @@ -# Target configuration for the Silicon Labs EM358 chips - -# -# em357 family supports JTAG and SWD transports -# - -if { ![info exists CHIPNAME] } { - set CHIPNAME em358 -} - -if { ![info exists BSTAPID] } { - set BSTAPID 0x069aa62b -} - -# 512K of flash in the em358 chips -set FLASHSIZE 0x80000 -source [find target/em357.cfg] diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg deleted file mode 100644 index f186d37..0000000 --- a/tcl/target/epc9301.cfg +++ /dev/null @@ -1,32 +0,0 @@ -# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board. - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME ep9301 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # Force an error until we get a good number. - set _CPUTAPID 0xffffffff -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1 - -#flash configuration -#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME diff --git a/tcl/target/exynos5250.cfg b/tcl/target/exynos5250.cfg deleted file mode 100644 index 3678341..0000000 --- a/tcl/target/exynos5250.cfg +++ /dev/null @@ -1,23 +0,0 @@ -# -# Samsung Exynos 5250 - dual-core ARM Cortex-A15 -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME exynos5250 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create ${_TARGETNAME}0 cortex_a -chain-position $_TARGETNAME -target create ${_TARGETNAME}1 cortex_a -chain-position $_TARGETNAME - -target smp ${_TARGETNAME}0 ${_TARGETNAME}1 diff --git a/tcl/target/faux.cfg b/tcl/target/faux.cfg deleted file mode 100644 index d3891cd..0000000 --- a/tcl/target/faux.cfg +++ /dev/null @@ -1,30 +0,0 @@ -#Script for faux target - used for testing - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME at91eb40a -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x00000000 -} - - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -#target configuration -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - -#dummy flash driver -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 $_TARGETNAME diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg deleted file mode 100644 index 389576e..0000000 --- a/tcl/target/feroceon.cfg +++ /dev/null @@ -1,31 +0,0 @@ -###################################### -# Target: Marvell Feroceon CPU core -###################################### - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME feroceon -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x20a023d3 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME - -reset_config trst_and_srst -adapter_nsrst_delay 200 -jtag_ntrst_delay 200 - diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg deleted file mode 100644 index 78bbc94..0000000 --- a/tcl/target/fm3.cfg +++ /dev/null @@ -1,53 +0,0 @@ -# MB9BF506 -# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME mb9bfxx6 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -# delays on reset lines -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -# Fujitsu Cortex-M3 reset configuration -reset_config trst_only - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -# MB9BF506 has 64kB of SRAM on its main system bus -$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0 - -# MB9BF506 has 512kB internal FLASH - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME - -# 4MHz / 6 = 666kHz, so use 500 -adapter_khz 500 - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/fm4.cfg b/tcl/target/fm4.cfg deleted file mode 100644 index e5d0f8d..0000000 --- a/tcl/target/fm4.cfg +++ /dev/null @@ -1,30 +0,0 @@ -# -# Spansion FM4 (ARM Cortex-M4) -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME fm4 -} - -source [find target/swj-dp.tcl] - -if { [info exists CPUTAPID] } { - set _CPU_TAPID $CPUTAPID -} elseif { [using_jtag] } { - set _CPU_TAPID 0x4ba00477 -} else { - set _CPU_TAPID 0x2ba01477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME - -adapter_khz 500 - -if {![using_hla]} { - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/fm4_mb9bf.cfg b/tcl/target/fm4_mb9bf.cfg deleted file mode 100644 index e53fdc8..0000000 --- a/tcl/target/fm4_mb9bf.cfg +++ /dev/null @@ -1,18 +0,0 @@ -# -# Spansion FM4 MB9BFxxx (ARM Cortex-M4) -# - -source [find target/fm4.cfg] - -# MB9BF566 M/N/R have 32 KB SRAM0 -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x8000 -} - -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \ - -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES diff --git a/tcl/target/fm4_s6e2cc.cfg b/tcl/target/fm4_s6e2cc.cfg deleted file mode 100644 index 60b73b9..0000000 --- a/tcl/target/fm4_s6e2cc.cfg +++ /dev/null @@ -1,19 +0,0 @@ -# -# Spansion FM4 S6E2CC (ARM Cortex-M4) -# - -source [find target/fm4.cfg] - -# S6E2CC8 H/J/L have 96 KB SRAM0 -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x18000 -} - -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \ - -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES -flash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 $_TARGETNAME $CHIPSERIES diff --git a/tcl/target/gp326xxxa.cfg b/tcl/target/gp326xxxa.cfg deleted file mode 100644 index feb7554..0000000 --- a/tcl/target/gp326xxxa.cfg +++ /dev/null @@ -1,94 +0,0 @@ -# -# Support for General Plus GP326XXXA chips -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME gp326xxxa -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4f1f0f0f -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - -# Use internal SRAM as a work area -$_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0 - -# The chip has both lines connected together -reset_config trst_and_srst srst_pulls_trst -# This delay is needed otherwise communication with the target would -# be unreliable -adapter_nsrst_delay 100 - -# Set the adapter speed ridiculously low just in case we are -# running off of a 32kHz clock -adapter_khz 2 - -proc gp32xxxa_halt_and_reset_control_registers {} { - # System control registers - set P_SYSTEM_CTRL_NEW 0xD0000008 - set P_SYSTEM_CTRL 0xD000000C - set P_SYSTEM_CLK_EN0 0xD0000010 - set P_SYSTEM_CLK_EN1 0xD0000014 - set P_SYSTEM_RESET_FLAG 0xD0000018 - set P_SYSTEM_CLK_CTRL 0xD000001C - set P_SYSTEM_LVR_CTRL 0xD0000020 - set P_SYSTEM_WATCHDOG_CTRL 0xD0000024 - set P_SYSTEM_PLLEN 0xD000005C - - # Since we can't use SRST without pulling TRST - # we can't assume the state of the clock configuration - # or watchdog settings. So reset them before porceeding - - # Set the adapter speed ridiculously low just in case we are - # running off of a 32kHz clock - adapter_khz 2 - - # Disable any advanced features at this stage - arm7_9 dcc_downloads disable - arm7_9 fast_memory_access disable - - # Do a "soft reset" - soft_reset_halt - # Reset all system control registers to their default "after-reset" values - mwh $P_SYSTEM_WATCHDOG_CTRL 0x0000 - mwh $P_SYSTEM_LVR_CTRL 0x0000 - - mwh $P_SYSTEM_CTRL_NEW 0x0001 - mwh $P_SYSTEM_CTRL 0x0001 - # Clear all reset flags by writing 1's - mwh $P_SYSTEM_RESET_FLAG 0x001C - - mwh $P_SYSTEM_CLK_CTRL 0x8000 - mwh $P_SYSTEM_CLK_EN0 0xFFFF - mwh $P_SYSTEM_CLK_EN1 0xFFFF - mwh $P_SYSTEM_PLLEN 0x0010 - - # Unfortunately there's no register that would allow us to - # know if PLL is locked. So just wait for 100ms in hopes that - # it would be enough. - sleep 100 - - # Now that we know that we are running at 48Mhz - # Increase JTAG speed and enable speed optimization features - adapter_khz 5000 - arm7_9 dcc_downloads enable - arm7_9 fast_memory_access enable -} - -$_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers } diff --git a/tcl/target/hilscher_netx10.cfg b/tcl/target/hilscher_netx10.cfg deleted file mode 100644 index 3f96607..0000000 --- a/tcl/target/hilscher_netx10.cfg +++ /dev/null @@ -1,31 +0,0 @@ -################################################################################ -# Author: Michael Trensch (MTrensch@googlemail.com) -################################################################################ - -#Hilscher netX 10 CPU - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME netx10 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x25966021 -} - -# jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# that TAP is associated with a target -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME - diff --git a/tcl/target/hilscher_netx50.cfg b/tcl/target/hilscher_netx50.cfg deleted file mode 100644 index c6510c6..0000000 --- a/tcl/target/hilscher_netx50.cfg +++ /dev/null @@ -1,50 +0,0 @@ -################################################################################ -# Author: Michael Trensch (MTrensch@googlemail.com) -################################################################################ - -#Hilscher netX 50 CPU - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME netx50 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x25966021 -} - -# jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# that TAP is associated with a target -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME - -# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from -# DMA controller at init. This function will setup a dummy DMA to free this ares -# and must be called before using SDRAM -proc sdram_fix { } { - - mww 0x1c005830 0x00000001 - - mww 0x1c005104 0xBFFFFFFC - mww 0x1c00510c 0x00480001 - mww 0x1c005110 0x00000001 - - sleep 100 - - mww 0x1c00510c 0 - mww 0x1c005110 0 - mww 0x1c005830 0x00000000 - - puts "SDRAM Fix executed!" -} diff --git a/tcl/target/hilscher_netx500.cfg b/tcl/target/hilscher_netx500.cfg deleted file mode 100644 index 93375fd..0000000 --- a/tcl/target/hilscher_netx500.cfg +++ /dev/null @@ -1,47 +0,0 @@ -#Hilscher netX 500 CPU - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME netx500 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926021 -} - -# jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# that TAP is associated with a target -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -proc mread32 {addr} { - set value(0) 0 - mem2array value 32 $addr 1 - return $value(0) -} - -# This function must be called on netX100/500 right after halt -# If it is called later the needed register cannot be written anymore -proc sdram_fix { } { - - set accesskey [mread32 0x00100070] - mww 0x00100070 [expr $accesskey] - mww 0x0010002c 0x00000001 - - if {[expr [mread32 0x0010002c] & 0x07] == 0x07} { - puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!" - } else { - puts "SDRAM Fix succeeded!" - } -} diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg deleted file mode 100644 index abd7b6a..0000000 --- a/tcl/target/icepick.cfg +++ /dev/null @@ -1,142 +0,0 @@ -# -# Copyright (C) 2011 by Karl Kurbjun -# Copyright (C) 2009 by David Brownell -# - -# Utilities for TI ICEpick-C/D used in most TI SoCs -# Details about the ICEPick are available in the the TRM for each SoC -# and http://processors.wiki.ti.com/index.php/ICEPICK - -# create "constants" -proc CONST { key } { - - array set constant { - # define ICEPick instructions - IR_BYPASS 0x00 - IR_ROUTER 0x02 - IR_CONNECT 0x07 - IF_BYPASS 0x3F - } - return $constant($key) -} - -# Instruction to connect to the icepick module -proc icepick_c_connect {jrc} { - - # Send CONNECT instruction in IR state - irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE - - # Send write and connect key - drscan $jrc 8 0x89 -endstate DRPAUSE -} - -# Instruction to disconnect to the icepick module -proc icepick_c_disconnect {jrc} { - - # Send CONNECT instruction in IR state - irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE - - # Send write and connect key - drscan $jrc 8 0x86 -endstate DRPAUSE -} - -# -# icepick_c_router: -# this function is for sending router commands -# arguments are: -# jrc: TAP name for the ICEpick -# rw: read/write (0 for read, 1 for write) -# block: icepick or DAP -# register: which register to read/write -# payload: value to read/write -# this function is for sending router commands -# -proc icepick_c_router {jrc rw block register payload} { - - set new_dr_value \ - [expr ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \ - ( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) ] - -# echo "\tNew router value:\t0x[format %x $new_dr_value]" - - # select router - irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE - - # ROUTER instructions are 32 bits wide - set old_dr_value [drscan $jrc 32 $new_dr_value -endstate DRPAUSE] -} - -# Configure the icepick control register -proc icepick_c_setup {jrc} { - - # send a router write, block is 0, register is 1, value is 0x2100 - icepick_c_router $jrc 1 0x0 0x1 0x001000 -} - -# jrc == TAP name for the ICEpick -# port == a port number, 0..15 -proc icepick_c_tapenable {jrc port} { - - # First CONNECT to the ICEPick -# echo "Connecting to ICEPick" - icepick_c_connect $jrc - -# echo "Configuring the ICEpick" - icepick_c_setup $jrc - - # NOTE: it's important not to enter RUN/IDLE state until - # done sending these instructions and data to the ICEpick. - # And never to enter RESET, which will disable the TAPs. - - # first enable power and clock for TAP - icepick_c_router $jrc 1 0x2 $port 0x100048 - - # TRM states that the register should be read back here, skipped for now - - # enable debug "default" mode - icepick_c_router $jrc 1 0x2 $port 0x102048 - - # TRM states that debug enable and debug mode should be read back and - # confirmed - skipped for now - - # Finally select the tap - icepick_c_router $jrc 1 0x2 $port 0x102148 - - # Enter the bypass state - irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE - runtest 10 -} - -# jrc == TAP name for the ICEpick -# coreid== core id number 0..15 (not same as port number!) -proc icepick_d_set_coreid {jrc coreid } { - icepick_c_router $jrc 1 0x6 $coreid 0x2008 -} - -# jrc == TAP name for the ICEpick -# port == a port number, 0..15 -# Follow the sequence described in -# http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf -proc icepick_d_tapenable {jrc port coreid} { - # First CONNECT to the ICEPick - icepick_c_connect $jrc - icepick_c_setup $jrc - - # Select the port - icepick_c_router $jrc 1 0x2 $port 0x2108 - - # Set 4 bit core ID to the Cortex-A - icepick_d_set_coreid $jrc $coreid - - # Enter the bypass state - irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE - runtest 10 -} - -# This function uses the ICEPick to send a warm system reset -proc icepick_c_wreset {jrc} { - - # send a router write, block is 0, register is 1, value is 0x2100 - icepick_c_router $jrc 1 0x0 0x1 0x002101 -} - diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg deleted file mode 100644 index 9eea53e..0000000 --- a/tcl/target/imx.cfg +++ /dev/null @@ -1,30 +0,0 @@ -# utility fn's for Freescale i.MX series - -global TARGETNAME -set TARGETNAME $_TARGETNAME - -# rewrite commands of the form below to arm11 mcr... -# Data.Set c15:0x042f %long 0x40000015 -proc setc15 {regs value} { - global TARGETNAME - - echo [format "set p15 0x%04x, 0x%08x" $regs $value] - - arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value -} - - -proc imx3x_reset {} { - # this reset script comes from the Freescale PDK - # - # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK - - echo "Target Setup: initialize DRAM controller and peripherals" - -# Data.Set c15:0x01 %long 0x00050078 - setc15 0x01 0x00050078 - - echo "configuring CP15 for enabling the peripheral bus" -# Data.Set c15:0x042f %long 0x40000015 - setc15 0x042f 0x40000015 -} diff --git a/tcl/target/imx21.cfg b/tcl/target/imx21.cfg deleted file mode 100644 index 2d9ce39..0000000 --- a/tcl/target/imx21.cfg +++ /dev/null @@ -1,34 +0,0 @@ -#use combined on interfaces or targets that can't set TRST/SRST separately -# -# Hmmm.... should srst_pulls_trst be used here like i.MX27??? -reset_config trst_and_srst - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx21 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - - -# Note above there is 1 tap - -# The CPU tap -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0792611f -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - - -# Create the GDB Target. -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -arm7_9 dcc_downloads enable diff --git a/tcl/target/imx25.cfg b/tcl/target/imx25.cfg deleted file mode 100644 index bc91278..0000000 --- a/tcl/target/imx25.cfg +++ /dev/null @@ -1,46 +0,0 @@ -# -# imx25 config -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx25 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists ETBTAPID] } { - set _ETBTAPID $ETBTAPID -} else { - set _ETBTAPID 0x1b900f0f -} -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0x0f -expected-id $_ETBTAPID - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926041 -} -jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id 0x0 - -if { [info exists SDMATAPID] } { - set _SDMATAPID $SDMATAPID -} else { - set _SDMATAPID 0x0882301d -} -jtag newtap $_CHIPNAME sdma -irlen 5 -expected-id $_SDMATAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN \ - -chain-position $_TARGETNAME - -# trace setup -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/imx27.cfg b/tcl/target/imx27.cfg deleted file mode 100644 index e5a5035..0000000 --- a/tcl/target/imx27.cfg +++ /dev/null @@ -1,53 +0,0 @@ -# page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3" -# SRST pulls TRST -# -# Without setting these options correctly you'll see all sorts -# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset -# failing, etc. -reset_config trst_and_srst srst_pulls_trst - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx27 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - - -# Note above there are 2 taps - -# trace buffer -if { [info exists ETBTAPID] } { - set _ETBTAPID $ETBTAPID -} else { - set _ETBTAPID 0x1b900f0f -} -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID - -# The CPU tap -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926121 -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# Create the GDB Target. -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -# REVISIT what operating environment sets up this virtual address mapping? -$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \ - -work-area-size 0x8000 -work-area-backup 1 -# Internal to the chip, there is 45K of SRAM -# - -arm7_9 dcc_downloads enable - -# trace setup -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/imx28.cfg b/tcl/target/imx28.cfg deleted file mode 100644 index 4cc3950..0000000 --- a/tcl/target/imx28.cfg +++ /dev/null @@ -1,38 +0,0 @@ -# i.MX28 config file. -# based off of the imx21.cfg file. - -reset_config trst_and_srst - -#jtag nTRST and nSRST delay -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx28 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - - -# Note above there is 1 tap - -# The CPU tap -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x079264f3 -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - - -# Create the GDB Target. -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -arm7_9 dcc_downloads enable diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg deleted file mode 100644 index ca63951..0000000 --- a/tcl/target/imx31.cfg +++ /dev/null @@ -1,68 +0,0 @@ -# imx31 config -# - -reset_config trst_and_srst srst_gates_jtag - -adapter_nsrst_delay 5 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx31 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07b3601d -} - -if { [info exists SDMATAPID] } { - set _SDMATAPID $SDMATAPID -} else { - set _SDMATAPID 0x2190101d -} - -if { [info exists ETBTAPID] } { - set _ETBTAPID $ETBTAPID -} else { - set _ETBTAPID 0x2b900f0f -} - -#======================================== - -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID - -# The "SDMA" - <S>mart <DMA> controller debug tap -# Based on some IO pins - this can be disabled & removed -# See diagram: 6-14 -# SIGNAL NAME: -# SJC_MOD - controls multiplexer - disables ARM1136 -# SDMA_BYPASS - disables SDMA - -# -# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID - -# No IDCODE for this TAP -jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0 - -# Per section 40.17.1, table 40-85 the IR register is 4 bits -# But this conflicts with Diagram 6-13, "3bits ir and drs" -jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME - - -proc power_restore {} { echo "Sensed power restore. No action." } -proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." } - -# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg deleted file mode 100644 index 21495c2..0000000 --- a/tcl/target/imx35.cfg +++ /dev/null @@ -1,55 +0,0 @@ -# imx35 config -# - -reset_config trst_and_srst srst_gates_jtag -jtag_ntrst_delay 100 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx35 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07b3601d -} - -if { [info exists SDMATAPID] } { - set _SDMATAPID $SDMATAPID -} else { - set _SDMATAPID 0x0882601d -} - -if { [info exists ETBTAPID] } { - set _ETBTAPID $ETBTAPID -} else { - set _ETBTAPID 0x2b900f0f -} - -#======================================== - -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID - -# No IDCODE for this TAP -jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0 - -jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME - -proc power_restore {} { echo "Sensed power restore. No action." } -proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." } - -# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg deleted file mode 100644 index b143aad..0000000 --- a/tcl/target/imx51.cfg +++ /dev/null @@ -1,47 +0,0 @@ -# Freescale i.MX51 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx51 -} - -# CoreSight Debug Access Port -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x1ba00477 -} - -jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_DAP_TAPID - -# SDMA / no IDCODE -jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf - -# SJC -if { [info exists SJC_TAPID] } { - set _SJC_TAPID SJC_TAPID -} else { - set _SJC_TAPID 0x0190c01d -} - -jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \ - -expected-id $_SJC_TAPID -ignore-version - -# GDB target: Cortex-A8, using DAP -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP - -# some TCK tycles are required to activate the DEBUG power domain -jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100" - -# have the DAP "always" be active -jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP" - -proc imx51_dbginit {target} { - # General Cortex-A8 debug initialisation - cortex_a dbginit -} - -$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME" diff --git a/tcl/target/imx53.cfg b/tcl/target/imx53.cfg deleted file mode 100644 index 87a3008..0000000 --- a/tcl/target/imx53.cfg +++ /dev/null @@ -1,47 +0,0 @@ -# Freescale i.MX53 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx53 -} - -# CoreSight Debug Access Port -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x1ba00477 -} - -jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_DAP_TAPID - -# SDMA / no IDCODE -jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf - -# SJC -if { [info exists SJC_TAPID] } { - set _SJC_TAPID SJC_TAPID -} else { - set _SJC_TAPID 0x0190d01d -} - -jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \ - -expected-id $_SJC_TAPID -ignore-version - -# GDB target: Cortex-A8, using DAP -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP - -# some TCK tycles are required to activate the DEBUG power domain -jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100" - -# have the DAP "always" be active -jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP" - -proc imx53_dbginit {target} { - # General Cortex-A8 debug initialisation - cortex_a dbginit -} - -$_TARGETNAME configure -event reset-assert-post "imx53_dbginit $_TARGETNAME" diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg deleted file mode 100644 index 4f7e98a..0000000 --- a/tcl/target/imx6.cfg +++ /dev/null @@ -1,59 +0,0 @@ -# Freescale i.MX6 series single/dual/quad core processor - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx6 -} - -# CoreSight Debug Access Port -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x4ba00477 -} - -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ - -expected-id $_DAP_TAPID - -# SDMA / no IDCODE -jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f - -# System JTAG Controller -if { [info exists SJC_TAPID] } { - set _SJC_TAPID $SJC_TAPID -} else { - set _SJC_TAPID 0x0191c01d -} -set _SJC_TAPID2 0x2191c01d -set _SJC_TAPID3 0x2191e01d -set _SJC_TAPID4 0x1191c01d - -jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ - -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \ - -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4 - -# GDB target: Cortex-A9, using DAP, configuring only one core -# Base addresses of cores: -# core 0 - 0x82150000 -# core 1 - 0x82152000 -# core 2 - 0x82154000 -# core 3 - 0x82156000 -set _TARGETNAME $_CHIPNAME.cpu.0 -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ - -coreid 0 -dbgbase 0x82150000 - -# some TCK cycles are required to activate the DEBUG power domain -jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" - -proc imx6_dbginit {target} { - # General Cortex-A8/A9 debug initialisation - cortex_a dbginit -} - -# Slow speed to be sure it will work -adapter_khz 1000 -$_TARGETNAME configure -event reset-start { adapter_khz 1000 } - -$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME" -$_TARGETNAME configure -event gdb-attach { halt } diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg deleted file mode 100644 index 31f1aa1..0000000 --- a/tcl/target/is5114.cfg +++ /dev/null @@ -1,46 +0,0 @@ -# script for Insilica IS-5114 -# AKA: Atmel AT76C114 - an ARM946 chip -# ATMEL sold his product line to Insilica... - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME is5114 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a little endian - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # Force an error until we get a good number. - set _CPUTAPID 0xffffffff -} - -# jtag speed. We need to stick to 16kHz until we've finished reset. -adapter_khz 16 - -reset_config trst_and_srst - -# Do not specify a tap id here... -jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1 -# This is the "arm946" chip. -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf -jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1 - - -#arm946e-s and -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -event reset-start { adapter_khz 16 } -$_TARGETNAME configure -event reset-init { - # We can increase speed now that we know the target is halted. - adapter_khz 3000 -} -$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1 diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg deleted file mode 100644 index d7b5bf4..0000000 --- a/tcl/target/ixp42x.cfg +++ /dev/null @@ -1,107 +0,0 @@ -#xscale ixp42x CPU - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME ixp42x -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a bigendian - set _ENDIAN big -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x19274013 -} -set _CPUTAPID2 0x19275013 -set _CPUTAPID3 0x19277013 -set _CPUTAPID4 0x29274013 -set _CPUTAPID5 0x29275013 -set _CPUTAPID6 0x29277013 - -jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME - - -# register constants for IXP42x SDRAM controller -global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD -global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD -set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 0x0000 -set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 0x0001 - -global IXP42x_SDRAM_CL3 -global IXP42x_SDRAM_CL2 -set IXP42x_SDRAM_CL3 0x0008 -set IXP42x_SDRAM_CL2 0x0000 - -global IXP42x_SDRAM_8MB_2Mx32_1BANK -global IXP42x_SDRAM_16MB_2Mx32_2BANK -global IXP42x_SDRAM_16MB_4Mx16_1BANK -global IXP42x_SDRAM_32MB_4Mx16_2BANK -global IXP42x_SDRAM_32MB_8Mx16_1BANK -global IXP42x_SDRAM_64MB_8Mx16_2BANK -global IXP42x_SDRAM_64MB_16Mx16_1BANK -global IXP42x_SDRAM_128MB_16Mx16_2BANK -global IXP42x_SDRAM_128MB_32Mx16_1BANK -global IXP42x_SDRAM_256MB_32Mx16_2BANK - -set IXP42x_SDRAM_8MB_2Mx32_1BANK 0x0030 -set IXP42x_SDRAM_16MB_2Mx32_2BANK 0x0031 -set IXP42x_SDRAM_16MB_4Mx16_1BANK 0x0032 -set IXP42x_SDRAM_32MB_4Mx16_2BANK 0x0033 -set IXP42x_SDRAM_32MB_8Mx16_1BANK 0x0010 -set IXP42x_SDRAM_64MB_8Mx16_2BANK 0x0011 -set IXP42x_SDRAM_64MB_16Mx16_1BANK 0x0012 -set IXP42x_SDRAM_128MB_16Mx16_2BANK 0x0013 -set IXP42x_SDRAM_128MB_32Mx16_1BANK 0x0014 -set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015 - - -# helper function to init SDRAM on IXP42x. -# SDRAM_CFG: one of IXP42X_SDRAM_xxx -# REFRESH: refresh counter reload value (integer) -# CASLAT: 2 or 3 -proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } { - - switch $CASLAT { - 2 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ] - set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD - } - 3 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ] - set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD - } - default { error [format "unsupported cas latency \"%s\" " $CASLAT] } - } - echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH] - - mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3 - mww 0xCC000004 0 ;# disable refresh - mww 0xCC000008 3 ;# NOP - sleep 100 - mww 0xCC000004 $REFRESH ;# set refresh counter - mww 0xCC000008 2 ;# Precharge All Banks - sleep 100 - mww 0xCC000008 4 ;# Auto Refresh - mww 0xCC000008 4 ;# Auto Refresh - mww 0xCC000008 4 ;# Auto Refresh - mww 0xCC000008 4 ;# Auto Refresh - mww 0xCC000008 4 ;# Auto Refresh - mww 0xCC000008 4 ;# Auto Refresh - mww 0xCC000008 4 ;# Auto Refresh - mww 0xCC000008 4 ;# Auto Refresh - mww 0xCC000008 $CASCMD ;# Mode Select CL2/CL3 -} - -proc ixp42x_set_bigendian { } { - reg XSCALE_CTRL 0xF8 -} - diff --git a/tcl/target/k1921vk01t.cfg b/tcl/target/k1921vk01t.cfg deleted file mode 100755 index 61b193e..0000000 --- a/tcl/target/k1921vk01t.cfg +++ /dev/null @@ -1,55 +0,0 @@ -# K1921VK01T -# http://niiet.ru/chips/nis?id=354 - -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME k1921vk01t -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x10000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x4ba00477 - } { - # SWD IDCODE - set _CPUTAPID 0x2ba01477 - } -} -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME - -adapter_khz 2000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg deleted file mode 100644 index 9811611..0000000 --- a/tcl/target/k40.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# -# Freescale Kinetis K40 devices -# - -set CHIPNAME k40 -source [find target/kx.cfg] diff --git a/tcl/target/k60.cfg b/tcl/target/k60.cfg deleted file mode 100644 index b9c5e3a..0000000 --- a/tcl/target/k60.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# -# Freescale Kinetis K60 devices -# - -set CHIPNAME k60 -source [find target/kx.cfg] diff --git a/tcl/target/ke02.cfg b/tcl/target/ke02.cfg deleted file mode 100644 index 8311920..0000000 --- a/tcl/target/ke02.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# -# Freescale Kinetis KE02 devices -# - -set CHIPNAME ke02 -source [find target/kex.cfg] diff --git a/tcl/target/ke04.cfg b/tcl/target/ke04.cfg deleted file mode 100644 index f63d77c..0000000 --- a/tcl/target/ke04.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# -# Freescale Kinetis KE04 devices -# - -set CHIPNAME ke04 -source [find target/kex.cfg] diff --git a/tcl/target/ke06.cfg b/tcl/target/ke06.cfg deleted file mode 100644 index 3465b8b..0000000 --- a/tcl/target/ke06.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# -# Freescale Kinetis KE06 devices -# - -set CHIPNAME ke06 -source [find target/kex.cfg] diff --git a/tcl/target/kex.cfg b/tcl/target/kex.cfg deleted file mode 100644 index dca8a35..0000000 --- a/tcl/target/kex.cfg +++ /dev/null @@ -1,58 +0,0 @@ -# -# Freescale Kinetis KE series devices -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME ke -} - -# Work-area is a space in RAM used for flash programming -# By default use 1kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x400 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x4ba00477 - } { - set _CPUTAPID 0x2ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME - -adapter_khz 1000 - -reset_config srst_nogate - -if {![using_hla]} { - - # It is important that "kinetis_ke mdm check_security" is called for - # 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start' - # causes "kinetis_ke mdm check_security" to fail the first time openocd - # calls it when it tries to connect after the CPU has been power-cycled. - $_CHIPNAME.cpu configure -event examine-end { - kinetis_ke mdm check_security - } - - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/kl25.cfg b/tcl/target/kl25.cfg deleted file mode 100644 index 0e716e3..0000000 --- a/tcl/target/kl25.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# -# Freescale Kinetis KL25 devices -# - -set CHIPNAME kl25 -source [find target/klx.cfg] diff --git a/tcl/target/kl25z_hla.cfg b/tcl/target/kl25z_hla.cfg deleted file mode 100644 index e4deac6..0000000 --- a/tcl/target/kl25z_hla.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/kl25z_hla.cfg is deprecated, please switch to target/kl25.cfg" -source [find target/kl25.cfg] diff --git a/tcl/target/kl46.cfg b/tcl/target/kl46.cfg deleted file mode 100644 index 70ea273..0000000 --- a/tcl/target/kl46.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# -# Freescale Kinetis KL46 devices -# - -set CHIPNAME kl46 -source [find target/klx.cfg] diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg deleted file mode 100644 index 0df6612..0000000 --- a/tcl/target/klx.cfg +++ /dev/null @@ -1,60 +0,0 @@ -# -# Freescale Kinetis KL series devices -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME klx -} - -# Work-area is a space in RAM used for flash programming -# By default use 4kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x1000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0bc11477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME - -# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual -# specifies up to 1MHz for VLPR mode. -adapter_khz 1000 - -reset_config srst_nogate - -if {![using_hla]} { - # Detect secured MCU or boot lock-up in RESET/WDOG loop - $_CHIPNAME.cpu configure -event examine-start { - kinetis mdm check_security - } - - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual -# specifies up to 24MHz for run mode; Table 17 of Sub-Family Data -# Sheet rev4 lists 25MHz as the maximum frequency. -# Uncoment only if VLPR mode is not used -#$_TARGETNAME configure -event reset-init { -# adapter_khz 24000 -#} diff --git a/tcl/target/ks869x.cfg b/tcl/target/ks869x.cfg deleted file mode 100644 index 0f6829c..0000000 --- a/tcl/target/ks869x.cfg +++ /dev/null @@ -1,34 +0,0 @@ -# ARM920T CPU - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME ks869x -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x00922f0f -} - -adapter_khz 6000 - -# jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0 - -# speed up memory downloads -arm7_9 fast_memory_access enable -arm7_9 dcc_downloads enable diff --git a/tcl/target/kx.cfg b/tcl/target/kx.cfg deleted file mode 100644 index b39ee3d..0000000 --- a/tcl/target/kx.cfg +++ /dev/null @@ -1,54 +0,0 @@ -# -# Freescale Kinetis Kx series devices -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME kx -} - -# Work-area is a space in RAM used for flash programming -# By default use 4kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x1000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x4ba00477 - } { - set _CPUTAPID 0x2ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME - -adapter_khz 1000 - -reset_config srst_nogate - -if {![using_hla]} { - # Detect secured MCU or boot lock-up in RESET/WDOG loop - $_CHIPNAME.cpu configure -event examine-start { - kinetis mdm check_security - } - - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/lpc11xx.cfg b/tcl/target/lpc11xx.cfg deleted file mode 100644 index 7a65c1f..0000000 --- a/tcl/target/lpc11xx.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# NXP LPC11xx Cortex-M0 with at least 1kB SRAM -set CHIPNAME lpc11xx -set CHIPSERIES lpc1100 -if { ![info exists WORKAREASIZE] } { - set WORKAREASIZE 0x400 -} - -source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc12xx.cfg b/tcl/target/lpc12xx.cfg deleted file mode 100644 index a37c6fe..0000000 --- a/tcl/target/lpc12xx.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# NXP LPC12xx Cortex-M0 with at least 4kB SRAM -set CHIPNAME lpc12xx -set CHIPSERIES lpc1200 -if { ![info exists WORKAREASIZE] } { - set WORKAREASIZE 0x1000 -} - -source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc13xx.cfg b/tcl/target/lpc13xx.cfg deleted file mode 100644 index 3d128c9..0000000 --- a/tcl/target/lpc13xx.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# NXP LPC13xx Cortex-M3 with at least 4kB SRAM -set CHIPNAME lpc13xx -set CHIPSERIES lpc1300 -if { ![info exists WORKAREASIZE] } { - set WORKAREASIZE 0x1000 -} - -source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg deleted file mode 100644 index dccf880..0000000 --- a/tcl/target/lpc17xx.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# NXP LPC17xx Cortex-M3 with at least 8kB SRAM -set CHIPNAME lpc17xx -set CHIPSERIES lpc1700 -if { ![info exists WORKAREASIZE] } { - set WORKAREASIZE 0x2000 -} - -source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg deleted file mode 100644 index a781403..0000000 --- a/tcl/target/lpc1850.cfg +++ /dev/null @@ -1,34 +0,0 @@ -source [find target/swj-dp.tcl] - -adapter_khz 500 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc1850 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} -# -# M3 JTAG mode TAP -# -if { [info exists M3_JTAG_TAPID] } { - set _M3_JTAG_TAPID $M3_JTAG_TAPID -} else { - set _M3_JTAG_TAPID 0x4ba00477 -} - -swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID - -set _TARGETNAME $_CHIPNAME.m3 -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg deleted file mode 100644 index 9c10e9f..0000000 --- a/tcl/target/lpc1xxx.cfg +++ /dev/null @@ -1,159 +0,0 @@ -# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts -# -# !!!!!! -# -# This file should not be included directly, rather by the lpc11xx.cfg, -# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the -# appropriate values. -# -# !!!!!! - -# LPC8xx chips support only SWD transport. -# LPC11xx chips support only SWD transport. -# LPC12xx chips support only SWD transport. -# LPC11Uxx chips support only SWD transports. -# LPC13xx chips support only SWD transports. -# LPC17xx chips support both JTAG and SWD transports. -# LPC40xx chips support both JTAG and SWD transports. -# Adapt based on what transport is active. -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)." -} - -if { [info exists CHIPSERIES] } { - # Validate chip series is supported - if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } { - error "Unsupported LPC1xxx chip series specified." - } - set _CHIPSERIES $CHIPSERIES -} else { - error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)." -} - -# After reset, the chip is clocked by an internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# CCLK is the core clock frequency in KHz -if { [info exists CCLK] } { - # Allow user override - set _CCLK $CCLK -} else { - # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x) - if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } { - set _CCLK 12000 - } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { - set _CCLK 4000 - } -} - -if { [info exists CPUTAPID] } { - # Allow user override - set _CPUTAPID $CPUTAPID -} else { - # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core. - if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } { - set _CPUTAPID 0x0bb11477 - } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { - if { [using_jtag] } { - set _CPUTAPID 0x4ba00477 - } { - set _CPUTAPID 0x2ba01477 - } - } -} - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE." -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) -# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) -# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) -# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) -# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) -# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000) -$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE - -# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000) -# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000) -# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000) -# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000) -# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000) -# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000) -# -# All are compatible with the "lpc1700" variant of the LPC2000 flash driver -# (same cmd51 destination boundary alignment, and all three support 256 byte -# transfers). -# -# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \ - auto $_CCLK calc_checksum - -if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } { - # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select - # "User Flash Mode" where interrupt vectors are _not_ remapped, - # and reside in flash instead). - # - # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description - # Bit Symbol Value Description - # 1:0 MAP System memory remap - # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. - # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. - # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. - # 31:2 - - Reserved. - $_TARGETNAME configure -event reset-init { - mww 0x40048000 0x02 - } -} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { - # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select - # "User Flash Mode" where interrupt vectors are _not_ remapped, - # and reside in flash instead). - # - # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description - # Bit Symbol Value Description Reset - # value - # 0 MAP Memory map control. 0 - # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. - # 1 User mode. The on-chip Flash memory is mapped to address 0. - # 31:1 - Reserved. The value read from a reserved bit is not defined. NA - # - # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user - $_TARGETNAME configure -event reset-init { - mww 0x400FC040 0x01 - } -} - -# Run with *real slow* clock by default since the -# boot rom could have been playing with the PLL, so -# we have no idea what clock the target is running at. -adapter_khz 10 - -# delays on reset lines -adapter_nsrst_delay 200 -if {[using_jtag]} { - jtag_ntrst_delay 200 -} - -# LPC8xx (Cortex-M0+ core) support SYSRESETREQ -# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ -# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ -# LPC40xx (Cortex-M4F core) support SYSRESETREQ -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg deleted file mode 100644 index f55777f..0000000 --- a/tcl/target/lpc2103.cfg +++ /dev/null @@ -1,21 +0,0 @@ -# NXP LPC2103 ARM7TDMI-S with 32kB flash and 8kB SRAM, clocked with 12MHz crystal - -source [find target/lpc2xxx.cfg] - -# parameters: -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2103 {core_freq_khz adapter_freq_khz} { - # 32kB flash and 8kB SRAM - # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> - setup_lpc2xxx lpc2103 0x4f1f0f0f 0x8000 lpc2000_v2 0x2000 $core_freq_khz $adapter_freq_khz -} - -proc init_targets {} { - # default to core clocked with 12MHz crystal - echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." - - # setup_lpc2103 <core_freq_khz> <adapter_freq_khz> - setup_lpc2103 12000 1500 -} diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg deleted file mode 100644 index 0251738..0000000 --- a/tcl/target/lpc2124.cfg +++ /dev/null @@ -1,21 +0,0 @@ -# NXP LPC2124 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal - -source [find target/lpc2xxx.cfg] - -# parameters: -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2124 {core_freq_khz adapter_freq_khz} { - # 256kB flash and 16kB SRAM - # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> - setup_lpc2xxx lpc2124 0x4f1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz -} - -proc init_targets {} { - # default to core clocked with 12MHz crystal - echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." - - # setup_lpc2124 <core_freq_khz> <adapter_freq_khz> - setup_lpc2124 12000 1500 -} diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg deleted file mode 100644 index 2c33cde..0000000 --- a/tcl/target/lpc2129.cfg +++ /dev/null @@ -1,21 +0,0 @@ -# NXP LPC2129 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal - -source [find target/lpc2xxx.cfg] - -# parameters: -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2129 {core_freq_khz adapter_freq_khz} { - # 256kB flash and 16kB SRAM - # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> - setup_lpc2xxx lpc2129 0xcf1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz -} - -proc init_targets {} { - # default to core clocked with 12MHz crystal - echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." - - # setup_lpc2129 <core_freq_khz> <adapter_freq_khz> - setup_lpc2129 12000 1500 -} diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg deleted file mode 100644 index f3a2011..0000000 --- a/tcl/target/lpc2148.cfg +++ /dev/null @@ -1,21 +0,0 @@ -# NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal - -source [find target/lpc2xxx.cfg] - -# parameters: -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2148 {core_freq_khz adapter_freq_khz} { - # 500kB flash and 32kB SRAM - # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> - setup_lpc2xxx lpc2148 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz -} - -proc init_targets {} { - # default to core clocked with 12MHz crystal - echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." - - # setup_lpc2148 <core_freq_khz> <adapter_freq_khz> - setup_lpc2148 12000 1500 -} diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg deleted file mode 100644 index 83d595d..0000000 --- a/tcl/target/lpc2294.cfg +++ /dev/null @@ -1,23 +0,0 @@ -# NXP LPC2294 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal - -source [find target/lpc2xxx.cfg] - -# parameters: -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2294 {core_freq_khz adapter_freq_khz} { - # 256kB flash and 16kB SRAM - # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> - - # !! TAPID unknown !! - setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz -} - -proc init_targets {} { - # default to core clocked with 12MHz crystal - echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." - - # setup_lpc2294 <core_freq_khz> <adapter_freq_khz> - setup_lpc2294 12000 1500 -} diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg deleted file mode 100644 index 0b66b82..0000000 --- a/tcl/target/lpc2378.cfg +++ /dev/null @@ -1,21 +0,0 @@ -# NXP LPC2378 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 56kB SRAM (16kB for ETH, 8kB for DMA), clocked with 4MHz internal oscillator - -source [find target/lpc2xxx.cfg] - -# parameters: -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2378 {core_freq_khz adapter_freq_khz} { - # 504kB flash and 32kB SRAM - # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> - setup_lpc2xxx lpc2378 0x4f1f0f0f 0x7e000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz -} - -proc init_targets {} { - # default to core clocked with 4MHz internal oscillator - echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different." - - # setup_lpc2378 <core_freq_khz> <adapter_freq_khz> - setup_lpc2378 4000 500 -} diff --git a/tcl/target/lpc2460.cfg b/tcl/target/lpc2460.cfg deleted file mode 100644 index 69fdc4a..0000000 --- a/tcl/target/lpc2460.cfg +++ /dev/null @@ -1,21 +0,0 @@ -# NXP LPC2460 ARM7TDMI-S with 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator - -source [find target/lpc2xxx.cfg] - -# parameters: -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2460 {core_freq_khz adapter_freq_khz} { - # 64kB SRAM - # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> - setup_lpc2xxx lpc2460 0x4f1f0f0f 0 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz -} - -proc init_targets {} { - # default to core clocked with 4MHz internal oscillator - echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different." - - # setup_lpc2460 <core_freq_khz> <adapter_freq_khz> - setup_lpc2460 4000 500 -} diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg deleted file mode 100644 index 48e5bdf..0000000 --- a/tcl/target/lpc2478.cfg +++ /dev/null @@ -1,21 +0,0 @@ -# NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator - -source [find target/lpc2xxx.cfg] - -# parameters: -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2478 {core_freq_khz adapter_freq_khz} { - # 504kB flash and 64kB SRAM - # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> - setup_lpc2xxx lpc2478 0x4f1f0f0f 0x7e000 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz -} - -proc init_targets {} { - # default to core clocked with 4MHz internal oscillator - echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different." - - # setup_lpc2478 <core_freq_khz> <adapter_freq_khz> - setup_lpc2478 4000 500 -} diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg deleted file mode 100644 index 5367787..0000000 --- a/tcl/target/lpc2900.cfg +++ /dev/null @@ -1,66 +0,0 @@ - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc2900 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0596802B -} - -if { [info exists HAS_ETB] } { -} else { - # Set default (no ETB). - # Show a warning, because this should have been configured explicitely. - set HAS_ETB 0 - # TODO: warning? -} - -if { [info exists ETBTAPID] } { - set _ETBTAPID $ETBTAPID -} else { - set _ETBTAPID 0x1B900F0F -} - -# TRST and SRST both exist, and can be controlled independently -reset_config trst_and_srst separate - -# Define the _TARGETNAME -set _TARGETNAME $_CHIPNAME.cpu - -# Include the ETB tap controller if asked for. -# Has to be done manually for newer devices (not an "old" LPC2917/2919). -if { $HAS_ETB == 1 } { - # Clear the HAS_ETB flag. Must be set again for a new tap in the chain. - set HAS_ETB 0 - - # Add the ETB tap controller and the ARM9 core debug tap - jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID - jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - - # Create the ".cpu" target - target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME - - # Configure ETM and ETB - etm config $_TARGETNAME 8 normal full etb - etb config $_TARGETNAME $_CHIPNAME.etb - -} else { - # Add the ARM9 core debug tap - jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - - # Create the ".cpu" target - target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -} - -arm7_9 dbgrq enable -arm7_9 dcc_downloads enable - -# Flash bank configuration: -# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz> -# Flash base address, total flash size, and number of sectors are all configured automatically. -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK diff --git a/tcl/target/lpc2xxx.cfg b/tcl/target/lpc2xxx.cfg deleted file mode 100644 index 11f1c48..0000000 --- a/tcl/target/lpc2xxx.cfg +++ /dev/null @@ -1,44 +0,0 @@ -# Common setup for the LPC2xxx parts - -# parameters: -# - chip_name - name of the chip, e.g. lpc2103 -# - cputapids - TAP IDs of the core, should be quoted if more than one, e.g. 0x4f1f0f0f or "0x3f0f0f0f 0x4f1f0f0f" -# - flash_size - size of on-chip flash (available for code, not including the bootloader) in bytes, e.g. 0x8000 -# - flash_variant - "type" of LPC2xxx device, lpc2000_v1 (LPC22xx and older LPC21xx) or lpc2000_v2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx) -# - workarea_size - size of work-area in RAM for flashing procedures, must not exceed the size of RAM available at 0x40000000, e.g. 0x2000 -# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 -# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 - -proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size core_freq_khz adapter_freq_khz} { - reset_config trst_and_srst - - # reset delays - adapter_nsrst_delay 100 - jtag_ntrst_delay 100 - - adapter_khz $adapter_freq_khz - - foreach i $cputapids { - append expected_ids "-expected-id " $i " " - } - - eval "jtag newtap $chip_name cpu -irlen 4 -ircapture 0x1 -irmask 0xf $expected_ids" - - global _TARGETNAME - set _TARGETNAME $chip_name.cpu - target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME - - $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size $workarea_size -work-area-backup 0 - - if { $flash_size > 0 } { - # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] - set _FLASHNAME $chip_name.flash - flash bank $_FLASHNAME lpc2000 0x0 $flash_size 0 0 $_TARGETNAME $flash_variant $core_freq_khz calc_checksum - } -} - -proc init_targets {} { - # FIX!!! read out CPUTAPID here and choose right setup. In addition to the - # CPUTAPID some querying of the target would be required. - return -error "This is a generic LPC2xxx configuration file, use a specific target file." -} diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg deleted file mode 100644 index 27c1f67..0000000 --- a/tcl/target/lpc3131.cfg +++ /dev/null @@ -1,76 +0,0 @@ -###################################### -# Target: NXP lpc3131 -###################################### - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc3131 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# ARM926EJS core -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926f0f -} - -# Scan Tap -# Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module -# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through. -if { [info exists SJCTAPID] } { - set _SJCTAPID $SJCTAPID -} else { - set _SJCTAPID 0x1541E02B -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -################################################################## -# various symbol definitions, to avoid hard-wiring addresses -################################################################## - -global lpc313x -set lpc313x [ dict create ] - -# Physical addresses for controllers and memory -dict set lpc313x sram0 0x11028000 -dict set lpc313x sram1 0x11040000 -dict set lpc313x uart 0x15001000 -dict set lpc313x cgu 0x13004000 -dict set lpc313x ioconfig 0x13003000 -dict set lpc313x sysconfig 0x13002800 -dict set lpc313x wdt 0x13002400 - -################################################################## -# Target configuration -################################################################## - -adapter_nsrst_delay 1000 -jtag_ntrst_delay 0 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME invoke-event halted - -$_TARGETNAME configure -work-area-phys [dict get $lpc313x sram0] -work-area-size 0x30000 -work-area-backup 0 - -$_TARGETNAME configure -event reset-init { - echo "\nRunning reset init script for LPC3131\n" - halt - wait_halt - reg cpsr 0xa00000d3 ;#Supervisor mode - reg pc 0x11029000 - poll - sleep 500 -} - -arm7_9 fast_memory_access enable -arm7_9 dcc_downloads enable diff --git a/tcl/target/lpc3250.cfg b/tcl/target/lpc3250.cfg deleted file mode 100644 index 14bb0f6..0000000 --- a/tcl/target/lpc3250.cfg +++ /dev/null @@ -1,43 +0,0 @@ -# lpc3250 config -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc3250 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x17900f0f -} - -if { [info exists CPUTAPID_REV_A0] } { - set _CPUTAPID_REV_A0 $CPUTAPID_REV_A0 -} else { - set _CPUTAPID_REV_A0 0x17926f0f -} - -if { [info exists SJCTAPID] } { - set _SJCTAPID $SJCTAPID -} else { - set _SJCTAPID 0x1b900f0f -} - -jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID \ - -expected-id $_CPUTAPID_REV_A0 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0 - -proc power_restore {} { echo "Sensed power restore. No action." } -proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." } diff --git a/tcl/target/lpc40xx.cfg b/tcl/target/lpc40xx.cfg deleted file mode 100644 index 606cda5..0000000 --- a/tcl/target/lpc40xx.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# NXP LPC40xx Cortex-M4F with at least 16kB SRAM -set CHIPNAME lpc40xx -set CHIPSERIES lpc4000 -if { ![info exists WORKAREASIZE] } { - set WORKAREASIZE 0x4000 -} - -source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg deleted file mode 100644 index 4e23ffb..0000000 --- a/tcl/target/lpc4350.cfg +++ /dev/null @@ -1,70 +0,0 @@ -source [find target/swj-dp.tcl] - -adapter_khz 500 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc4350 -} - -# -# M4 JTAG mode TAP -# -if { [info exists M4_JTAG_TAPID] } { - set _M4_JTAG_TAPID $M4_JTAG_TAPID -} else { - set _M4_JTAG_TAPID 0x4ba00477 -} - -# -# M4 SWD mode TAP -# -if { [info exists M4_SWD_TAPID] } { - set _M4_SWD_TAPID $M4_SWD_TAPID -} else { - set _M4_SWD_TAPID 0x2ba01477 -} - -if { [using_jtag] } { - set _M4_TAPID $_M4_JTAG_TAPID -} { - set _M4_TAPID $_M4_SWD_TAPID -} - -# -# M0 TAP -# -if { [info exists M0_JTAG_TAPID] } { - set _M0_JTAG_TAPID $M0_JTAG_TAPID -} else { - set _M0_JTAG_TAPID 0x0ba01477 -} - -swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M4_TAPID -target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 - -if { [using_jtag] } { - swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M0_JTAG_TAPID - target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0 -} - -# LPC4350 has 96+32 KB SRAM -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x20000 -} -$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \ - -work-area-size $_WORKAREASIZE -work-area-backup 0 - -if {![using_hla]} { - # on this CPU we should use VECTRESET to perform a soft reset and - # manually reset the periphery - # SRST or SYSRESETREQ disable the debug interface for the time of - # the reset and will not fit our requirements for a consistent debug - # session - cortex_m reset_config vectreset -} diff --git a/tcl/target/lpc4357.cfg b/tcl/target/lpc4357.cfg deleted file mode 100644 index 1a15ad6..0000000 --- a/tcl/target/lpc4357.cfg +++ /dev/null @@ -1,12 +0,0 @@ -# -# NXP LPC4357 -# - -if { ![info exists CHIPNAME] } { - set CHIPNAME lpc4357 -} -set WORKAREASIZE 0x8000 -source [find target/lpc4350.cfg] - -flash bank $_CHIPNAME.flasha lpc2000 0x1A000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum -flash bank $_CHIPNAME.flashb lpc2000 0x1B000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg deleted file mode 100644 index 67bff0a..0000000 --- a/tcl/target/lpc4370.cfg +++ /dev/null @@ -1,85 +0,0 @@ -# -# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each -# - -adapter_khz 500 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc4370 -} - -# -# M4 JTAG mode TAP -# -if { [info exists M4_JTAG_TAPID] } { - set _M4_JTAG_TAPID $M4_JTAG_TAPID -} else { - set _M4_JTAG_TAPID 0x4ba00477 -} - -# -# M4 SWD mode TAP -# -if { [info exists M4_SWD_TAPID] } { - set _M4_SWD_TAPID $M4_SWD_TAPID -} else { - set _M4_SWD_TAPID 0x2ba01477 -} - -source [find target/swj-dp.tcl] - -if { [using_jtag] } { - set _M4_TAPID $_M4_JTAG_TAPID -} else { - set _M4_TAPID $_M4_SWD_TAPID -} - -# -# M0 TAP -# -if { [info exists M0_JTAG_TAPID] } { - set _M0_JTAG_TAPID $M0_JTAG_TAPID -} else { - set _M0_JTAG_TAPID 0x0ba01477 -} - -swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M4_TAPID - -target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 - -# LPC4370 has 96+32 KB contiguous SRAM -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x20000 -} -$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \ - -work-area-size $_WORKAREASIZE -work-area-backup 0 - -if { [using_jtag] } { - jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M0_JTAG_TAPID - jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M0_JTAG_TAPID - - target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app - target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub - - # 32+8+32 KB SRAM - $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \ - -work-area-size 0x92000 -work-area-backup 0 - - # 16+2 KB M0 subsystem SRAM - $_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \ - -work-area-size 0x4800 -work-area-backup 0 - - # Default to the Cortex-M4 - targets $_CHIPNAME.m4 -} - -if { ![using_hla] } { - cortex_m reset_config vectreset -} diff --git a/tcl/target/lpc8xx.cfg b/tcl/target/lpc8xx.cfg deleted file mode 100644 index e0e210b..0000000 --- a/tcl/target/lpc8xx.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# NXP LPC8xx Cortex-M0+ with at least 1kB SRAM -if { ![info exists CHIPNAME] } { - set CHIPNAME lpc8xx -} -set CHIPSERIES lpc800 -if { ![info exists WORKAREASIZE] } { - set WORKAREASIZE 0x400 -} - -source [find target/lpc1xxx.cfg] diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg deleted file mode 100644 index 27ac8c3..0000000 --- a/tcl/target/mc13224v.cfg +++ /dev/null @@ -1,54 +0,0 @@ -source [find bitsbytes.tcl] -source [find cpu/arm/arm7tdmi.tcl] -source [find memory.tcl] -source [find mmr_helpers.tcl] - -set CHIP_MAKER freescale -set CHIP_FAMILY mc1322x -set CHIP_NAME mc13224 -set N_RAM 1 -set RAM(0,BASE) 0x00400000 -set RAM(0,LEN) 0x18000 -set RAM(0,HUMAN) "internal SRAM" -set RAM(0,TYPE) "ram" -set RAM(0,RWX) $RWX_RWX -set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY - -# I AM LAZY... I create 1 region for all MMRs. -set N_MMREGS 1 -set MMREGS(0,CHIPSELECT) -1 -set MMREGS(0,BASE) 0x80000000 -set MMREGS(0,LEN) 0x00030000 -set MMREGS(0,HUMAN) "mm-regs" -set MMREGS(0,TYPE) "mmr" -set MMREGS(0,RWX) $RWX_RW -set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY - -set N_XMEM 0 - -set _CHIPNAME mc13224v -set _CPUTAPID 0x1f1f001d - -jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -reset_config srst_only -jtag_ntrst_delay 200 - -# rclk hasn't been working well. This maybe the mc13224v or something else. -#adapter_khz 2000 -adapter_khz 2000 - -###################### -# Target configuration -###################### - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME - -# Internal sram memory -$_TARGETNAME configure -work-area-phys 0x00408000 \ - -work-area-size 0x1000 \ - -work-area-backup 1 - -# flash support is pending (should be straightforward to implement) -#flash bank mc1322x 0 0 0 0 $_TARGETNAME diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg deleted file mode 100644 index 804ac1a..0000000 --- a/tcl/target/mdr32f9q2i.cfg +++ /dev/null @@ -1,62 +0,0 @@ -# MDR32F9Q2I (1986ВЕ92У) -# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68 - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME mdr32f9q2i -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x8000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x4ba00477 - } { - # SWD IDCODE - set _CPUTAPID 0x2ba01477 - } -} -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# can't handle overlapping memory regions -if { [info exists IMEMORY] && [string equal $IMEMORY true] } { - flash bank ${_CHIPNAME}_info.flash mdr 0x08000000 0x01000 0 0 $_TARGETNAME 1 1 4 -} else { - flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4 -} - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -adapter_khz 1000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/nds32v2.cfg b/tcl/target/nds32v2.cfg deleted file mode 100644 index bbf6b3a..0000000 --- a/tcl/target/nds32v2.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# -# Andes Core -# -# http://www.andestech.com -# - -jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME nds32_v2 -endian little -chain-position $_TARGETNAME diff --git a/tcl/target/nds32v3.cfg b/tcl/target/nds32v3.cfg deleted file mode 100644 index 0c267cd..0000000 --- a/tcl/target/nds32v3.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# -# Andes Core -# -# http://www.andestech.com -# - -jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME nds32_v3 -endian little -chain-position $_TARGETNAME diff --git a/tcl/target/nds32v3m.cfg b/tcl/target/nds32v3m.cfg deleted file mode 100644 index 169e3d1..0000000 --- a/tcl/target/nds32v3m.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# -# Andes Core -# -# http://www.andestech.com -# - -jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME nds32_v3m -endian little -chain-position $_TARGETNAME diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg deleted file mode 100644 index 280dd4f..0000000 --- a/tcl/target/nrf51.cfg +++ /dev/null @@ -1,60 +0,0 @@ -# -# script for Nordic nRF51 series, a Cortex-M0 chip -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME nrf51 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 16kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0bb11477 -} - -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -if {![using_hla]} { - # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal - cortex_m reset_config sysresetreq -} - -flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME -flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME - -# -# The chip should start up from internal 16Mhz RC, so setting adapter -# clock to 1Mhz should be OK -# -adapter_khz 1000 - -proc enable_all_ram {} { - # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks - # are reliably enabled after reset on some revisions (contrary to spec.) So after - # resetting we enable all banks via the RAMON register - mww 0x40000524 0xF -} -$_TARGETNAME configure -event reset-end { enable_all_ram } diff --git a/tcl/target/nrf51_stlink.tcl b/tcl/target/nrf51_stlink.tcl deleted file mode 100644 index 7e23c5a..0000000 --- a/tcl/target/nrf51_stlink.tcl +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/nrf51_stlink.cfg is deprecated, please switch to target/nrf51.cfg" -source [find target/nrf51.cfg] diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg deleted file mode 100644 index c1cbf1a..0000000 --- a/tcl/target/nrf52.cfg +++ /dev/null @@ -1,28 +0,0 @@ -# -# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME nrf52 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x2ba01477 -} - -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -adapter_khz 10000 - -if { ![using_hla] } { - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/nuc910.cfg b/tcl/target/nuc910.cfg deleted file mode 100644 index 29cd29f..0000000 --- a/tcl/target/nuc910.cfg +++ /dev/null @@ -1,27 +0,0 @@ -# -# Nuvoton nuc910 (previously W90P910) based soc -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME nuc910 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # set useful default - set _CPUTAPID 0x07926f0f -} - -set _TARGETNAME $_CHIPNAME.cpu -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/tcl/target/numicro.cfg b/tcl/target/numicro.cfg deleted file mode 100644 index 13d9654..0000000 --- a/tcl/target/numicro.cfg +++ /dev/null @@ -1,60 +0,0 @@ -# script for Nuvoton MuMicro Cortex-M0 Series - -# Adapt based on what transport is active. -source [find target/swj-dp.tcl] - -# Set Chipname -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME NuMicro -} - -# SWD DP-ID Nuvoton NuMicro Cortex-M0 has SWD Transport only. -if { [info exists CPUDAPID] } { - set _CPUDAPID $CPUDAPID -} else { - set _CPUDAPID 0x0BB11477 -} - -# Work-area is a space in RAM used for flash programming -# By default use 2kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x800 -} - - -# Debug Adapter Target Settings -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#> -#set _FLASHNAME $_CHIPNAME.flash -#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME -# flash size will be probed -set _FLASHNAME $_CHIPNAME.flash_aprom -flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME -set _FLASHNAME $_CHIPNAME.flash_data -flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME -set _FLASHNAME $_CHIPNAME.flash_ldrom -flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME -set _FLASHNAME $_CHIPNAME.flash_config -flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME - -# set default SWCLK frequency -adapter_khz 1000 - -# set default srst setting "none" -reset_config none - -# HLA doesn't have cortex_m commands -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg deleted file mode 100644 index 7968ad1..0000000 --- a/tcl/target/omap2420.cfg +++ /dev/null @@ -1,61 +0,0 @@ -# Texas Instruments OMAP 2420 -# http://www.ti.com/omap -# as seen in Nokia N8x0 tablets - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME omap2420 -} - -# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK -reset_config srst_nogate - -# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6). -jtag newtap $_CHIPNAME iva -irlen 4 -disable - -# Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2). -jtag newtap $_CHIPNAME dsp -irlen 38 -disable - -# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID] } { - set _ETB_TAPID $ETB_TAPID -} else { - set _ETB_TAPID 0x2b900f0f -} -jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID - -# Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID] } { - set _CPU_TAPID $CPU_TAPID -} else { - set _CPU_TAPID 0x07b3602f -} -jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID - -# Primary TAP: ICEpick-B (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x01ce4801 -} -jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID - -# GDB target: the ARM. -set _TARGETNAME $_CHIPNAME.arm -target create $_TARGETNAME arm11 -chain-position $_TARGETNAME - -# scratch: framebuffer, may be initially unavailable in some chips -$_TARGETNAME configure -work-area-phys 0x40210000 -$_TARGETNAME configure -work-area-size 0x00081000 -$_TARGETNAME configure -work-area-backup 0 - -# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb - -# RM_RSTCTRL_WKUP.RST.GS - Trigger a global software reset, and -# give it a chance to finish before we talk to the chip again. -set RM_RSTCTRL_WKUP 0x48008450 -$_TARGETNAME configure -event reset-assert \ - "halt; $_TARGETNAME mww $RM_RSTCTRL_WKUP 2; sleep 200" diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg deleted file mode 100644 index c2929d1..0000000 --- a/tcl/target/omap3530.cfg +++ /dev/null @@ -1,74 +0,0 @@ -# TI OMAP3530 -# http://focus.ti.com/docs/prod/folders/print/omap3530.html -# Other OMAP3 chips remove DSP and/or the OpenGL support - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME omap3530 -} - -# ICEpick-C ... used to route Cortex, DSP, and more not shown here -source [find target/icepick.cfg] - -# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick -jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable - -# Subsidiary TAP: CoreSight Debug Access Port (DAP) -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x0b6d602f -} -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_DAP_TAPID -disable -jtag configure $_CHIPNAME.dap -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 3" - -# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0b7ae02f -} -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ - -expected-id $_JRC_TAPID - -# GDB target: Cortex-A8, using DAP -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap - -# SRAM: 64K at 0x4020.0000; use the first 16K -$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000 - -################### - -# the reset sequence is event-driven -# and kind of finicky... - -# some TCK tycles are required to activate the DEBUG power domain -jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" - -# have the DAP "always" be active -jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" - -proc omap3_dbginit {target} { - # General Cortex-A8 debug initialisation - cortex_a dbginit - # Enable DBGU signal for OMAP353x - $target mww phys 0x5401d030 0x00002000 -} - -# be absolutely certain the JTAG clock will work with the worst-case -# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in. -# OK to speed up *after* PLL and clock tree setup. -adapter_khz 1000 -$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 } - -# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset -# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick -# would issue. RST_DPLL3 (4) is a cold reset. -set PRM_RSTCTRL 0x48307250 -$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2" - -$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME" diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg deleted file mode 100644 index 6f3525a..0000000 --- a/tcl/target/omap4430.cfg +++ /dev/null @@ -1,127 +0,0 @@ -# OMAP4430 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME omap4430 -} - - -# Although the OMAP4430 supposedly has an ICEpick-D, only the -# ICEpick-C router commands seem to work. -# See http://processors.wiki.ti.com/index.php/ICEPICK -source [find target/icepick.cfg] - - -# -# A9 DAP -# -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x3BA00477 -} - -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_DAP_TAPID -disable -jtag configure $_CHIPNAME.dap -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 9" - - -# -# M3 DAPs, one per core -# -if { [info exists M3_DAP_TAPID] } { - set _M3_DAP_TAPID $M3_DAP_TAPID -} else { - set _M3_DAP_TAPID 0x4BA00477 -} - -jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M3_DAP_TAPID -disable -jtag configure $_CHIPNAME.m31_dap -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 5" - -jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M3_DAP_TAPID -disable -jtag configure $_CHIPNAME.m30_dap -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 4" - - -# -# ICEpick-D JRC (JTAG route controller) -# -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x3b95c02f - set _JRC_TAPID2 0x1b85202f -} - -# PandaBoard REV EA1 (PEAP platforms) -if { [info exists JRC_TAPID2] } { - set _JRC_TAPID2 $JRC_TAPID2 -} else { - set _JRC_TAPID2 0x1b85202f -} - - - -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ - -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2 - -# Required by ICEpick to power-up the debug domain -jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200" - - -# -# GDB target: Cortex-A9, using DAP -# -# The debugger can connect to either core of the A9, but currently -# not both simultaneously. Change -coreid to 1 to connect to the -# second core. -# -set _TARGETNAME $_CHIPNAME.cpu - -# APB DBGBASE reads 0x80040000, but this points to an empty ROM table. -# 0x80000000 is cpu0 coresight region -# -# -# CORTEX_A8_PADDRDBG_CPU_SHIFT 13 -# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) - -set _coreid 0 -set _dbgbase [expr 0x80000000 | ($_coreid << 13)] -echo "Using dbgbase = [format 0x%x $_dbgbase]" - -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ - -coreid 0 -dbgbase $_dbgbase - -# SRAM: 56KiB at 0x4030.0000 -$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 - - -# -# M3 targets, separate TAP/DAP for each core -# -target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap -target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap - - -# Once the JRC is up, enable our TAPs -jtag configure $_CHIPNAME.jrc -event setup " - jtag tapenable $_CHIPNAME.dap - jtag tapenable $_CHIPNAME.m30_dap - jtag tapenable $_CHIPNAME.m31_dap -" - -# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset -# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset. -set PRM_RSTCTRL 0x4A307B00 -$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1" -$_CHIPNAME.m30 configure -event reset-assert { } -$_CHIPNAME.m31 configure -event reset-assert { } - -# Soft breakpoints don't currently work due to broken cache handling -gdb_breakpoint_override hard - diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg deleted file mode 100644 index 9c40e62..0000000 --- a/tcl/target/omap4460.cfg +++ /dev/null @@ -1,126 +0,0 @@ -# OMAP4460 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME omap4460 -} - - -# Although the OMAP4430 supposedly has an ICEpick-D, only the -# ICEpick-C router commands seem to work. -# See http://processors.wiki.ti.com/index.php/ICEPICK -source [find target/icepick.cfg] - - -# -# A9 DAP -# -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - set _DAP_TAPID 0x3BA00477 -} - -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_DAP_TAPID -disable -jtag configure $_CHIPNAME.dap -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 9" - - -# -# M3 DAPs, one per core -# -if { [info exists M3_DAP_TAPID] } { - set _M3_DAP_TAPID $M3_DAP_TAPID -} else { - set _M3_DAP_TAPID 0x4BA00477 -} - -jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M3_DAP_TAPID -disable -jtag configure $_CHIPNAME.m31_dap -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 5" - -jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M3_DAP_TAPID -disable -jtag configure $_CHIPNAME.m30_dap -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 4" - - -# -# ICEpick-D JRC (JTAG route controller) -# -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x2b94e02f - set _JRC_TAPID2 0x1b85202f -} - -# PandaBoard REV EA1 (PEAP platforms) -if { [info exists JRC_TAPID2] } { - set _JRC_TAPID2 $JRC_TAPID2 -} else { - set _JRC_TAPID2 0x1b85202f -} - - - -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ - -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2 - -# Required by ICEpick to power-up the debug domain -jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200" - - -# -# GDB target: Cortex-A9, using DAP -# -# The debugger can connect to either core of the A9, but currently -# not both simultaneously. Change -coreid to 1 to connect to the -# second core. -# -set _TARGETNAME $_CHIPNAME.cpu - -# APB DBGBASE reads 0x80040000, but this points to an empty ROM table. -# 0x80000000 is cpu0 coresight region -# -# -# CORTEX_A8_PADDRDBG_CPU_SHIFT 13 -# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) - -set _coreid 0 -set _dbgbase [expr 0x80000000 | ($_coreid << 13)] -echo "Using dbgbase = [format 0x%x $_dbgbase]" - -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ - -coreid 0 -dbgbase $_dbgbase - -# SRAM: 56KiB at 0x4030.0000 -$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 - - -# -# M3 targets, separate TAP/DAP for each core -# -target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap -target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap - - -# Once the JRC is up, enable our TAPs -jtag configure $_CHIPNAME.jrc -event setup " - jtag tapenable $_CHIPNAME.dap - jtag tapenable $_CHIPNAME.m30_dap - jtag tapenable $_CHIPNAME.m31_dap -" - -# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset -# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset. -set PRM_RSTCTRL 0x4A307B00 -$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1" -$_CHIPNAME.m30 configure -event reset-assert { } -$_CHIPNAME.m31 configure -event reset-assert { } - -# Soft breakpoints don't currently work due to broken cache handling -gdb_breakpoint_override hard diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg deleted file mode 100644 index c4ff40e..0000000 --- a/tcl/target/omap5912.cfg +++ /dev/null @@ -1,52 +0,0 @@ -# TI OMAP5912 dual core processor -# http://focus.ti.com/docs/prod/folders/print/omap5912.html - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME omap5912 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # NOTE: validated with XOMAP5912 part - set _CPUTAPID 0x0692602f -} - -adapter_nsrst_delay 100 - -# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for -# its standalone siblings (like TMS320VC5502) of the same era - -#jtag scan chain -jtag newtap $_CHIPNAME dsp -irlen 38 -expected-id 0x03df1d81 -jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID -jtag newtap $_CHIPNAME unknown -irlen 8 - -set _TARGETNAME $_CHIPNAME.arm -target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME - -proc omap5912_reset {} { - # - # halt target - # - poll - sleep 1 - halt - wait_halt - # - # disable wdt - # - mww 0xfffec808 0x000000f5 - mww 0xfffec808 0x000000a0 - - mww 0xfffeb048 0x0000aaaa - sleep 500 - mww 0xfffeb048 0x00005555 - sleep 500 -} - -# omap5912 lcd frame buffer as working area -$_TARGETNAME configure -work-area-phys 0x20000000 \ - -work-area-size 0x3e800 -work-area-backup 0 diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg deleted file mode 100644 index fd9ff4c..0000000 --- a/tcl/target/omapl138.cfg +++ /dev/null @@ -1,66 +0,0 @@ -# -# Texas Instruments DaVinci family: OMAPL138 -# -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME omapl138 -} - -source [find target/icepick.cfg] - -# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID] } { - set _ETB_TAPID $ETB_TAPID -} else { - set _ETB_TAPID 0x2b900f0f -} -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable -jtag configure $_CHIPNAME.etb -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 3" - -# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID] } { - set _CPU_TAPID $CPU_TAPID -} else { - set _CPU_TAPID 0x07926001 -} -jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable -jtag configure $_CHIPNAME.arm -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 2" - -# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0b7d102f -} -jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version - -jtag configure $_CHIPNAME.jrc -event setup \ - "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" - -################ -# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) -# and the ETB memory (4K) are other options, while trace is unused. -# Little-endian; use the OpenOCD default. -set _TARGETNAME $_CHIPNAME.arm - -target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 - -# be absolutely certain the JTAG clock will work with the worst-case -# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns -# on the PLL and starts using it. OK to speed up after clock setup. -adapter_khz 1500 -$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 } - -arm7_9 fast_memory_access enable -arm7_9 dcc_downloads enable - -# trace setup -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb - -gdb_breakpoint_override hard -arm7_9 dbgrq enable diff --git a/tcl/target/or1k.cfg b/tcl/target/or1k.cfg deleted file mode 100644 index 360a0dd..0000000 --- a/tcl/target/or1k.cfg +++ /dev/null @@ -1,72 +0,0 @@ -set _ENDIAN big - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME or1k -} - -if { [info exists TAP_TYPE] } { - set _TAP_TYPE $TAP_TYPE -} else { - puts "You need to select a tap type" - shutdown -} - -# Configure the target -if { [string compare $_TAP_TYPE "VJTAG"] == 0 } { - if { [info exists FPGATAPID] } { - set _FPGATAPID $FPGATAPID - } else { - puts "You need to set your FPGA JTAG ID" - shutdown - } - - jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID - - set _TARGETNAME $_CHIPNAME.cpu - target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME - - # Select the TAP core we are using - tap_select vjtag - -} elseif { [string compare $_TAP_TYPE "XILINX_BSCAN"] == 0 } { - - if { [info exists FPGATAPID] } { - set _FPGATAPID $FPGATAPID - } else { - puts "You need to set your FPGA JTAG ID" - shutdown - } - - jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_FPGATAPID - - set _TARGETNAME $_CHIPNAME.cpu - target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME - - # Select the TAP core we are using - tap_select xilinx_bscan -} else { - # OpenCores Mohor JTAG TAP ID - set _CPUTAPID 0x14951185 - - jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - - set _TARGETNAME $_CHIPNAME.cpu - target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME - - # Select the TAP core we are using - tap_select mohor -} - -# Select the debug unit core we are using. This debug unit as an option. - -set ADBG_USE_HISPEED 1 -set ENABLE_JSP_SERVER 2 -set ENABLE_JSP_MULTI 4 - -# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped -# on burst reads and writes to improve download speeds. -# This option must match the RTL configured option. - -du_select adv [expr $ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI] diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg deleted file mode 100644 index d53b99a..0000000 --- a/tcl/target/pic32mx.cfg +++ /dev/null @@ -1,90 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME pic32mx -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x30938053 -} - -# default working area is 16384 -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME - -# -# At reset the pic32mx does not allow code execution from RAM -# we have to setup the BMX registers to allow this. -# One limitation is that we loose the first 2k of RAM. -# - -global _PIC32MX_DATASIZE -global _WORKAREASIZE -set _PIC32MX_DATASIZE 0x800 -set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)] - -$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0 -$_TARGETNAME configure -event reset-init { - # - # from reset the pic32 cannot execute code in ram - enable ram execution - # minimum offset from start of ram is 2k - # - global _PIC32MX_DATASIZE - global _WORKAREASIZE - - # BMXCON set 0 wait state option by clearing BMXWSDRM bit, bit 6 - mww 0xbf882000 0x001f0000 - # BMXDKPBA: 2k kernel data @ 0xa0000000 - mww 0xbf882010 $_PIC32MX_DATASIZE - # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA) - mww 0xbf882020 $_WORKAREASIZE - # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA) - mww 0xbf882030 $_WORKAREASIZE - - # - # Set system clock to 8Mhz if the default clock configuration is set - # - - # SYSKEY register, make sure OSCCON is locked - mww 0xbf80f230 0x0 - # SYSKEY register, write unlock sequence - mww 0xbf80f230 0xaa996655 - mww 0xbf80f230 0x556699aa - # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1 - mww 0xbf80f004 0x07000000 - # SYSKEY register, relock OSCCON - mww 0xbf80f230 0x0 -} - -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME -# add virtual banks for kseg0 and kseg1 -flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME -flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME - -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME -# add virtual banks for kseg0 and kseg1 -flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME -flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg deleted file mode 100644 index d443b01..0000000 --- a/tcl/target/psoc4.cfg +++ /dev/null @@ -1,152 +0,0 @@ -# script for Cypress PSoC 41xx/42xx family - -# -# PSoC 4 devices support SWD transports only. -# -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME psoc4 -} - -# Work-area is a space in RAM used for flash programming -# By default use 4kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x1000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0bb11477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME - -adapter_khz 1500 - -# Reset, bloody PSoC 4 reset -# -# 1) XRES (nSRST) resets also SWD DP so SWD line reset and DP reinit is needed. -# High level adapter stops working after SRST and needs OpenOCD restart. -# If your hw does not use SRST for other circuits, use sysresetreq instead -# -# 2) PSoC 4 executes initialization code from system ROM after reset. -# This code subsequently jumps to user flash reset vector address. -# Unfortunately the system ROM code is protected from reading and debugging. -# Protection breaks vector catch VC_CORERESET used for "reset halt" by cortex_m. -# -# Cypress uses TEST_MODE flag to loop CPU in system ROM before executing code -# from user flash. Programming specifications states that TEST_MODE flag must be -# set in time frame 400 usec delayed about 1 msec from reset. -# -# OpenOCD have no standard way how to set TEST_MODE in specified time frame. -# TEST_MODE flag is set before reset instead. It worked for tested chips -# despite it is not guaranteed by specification. -# -# 3) SWD cannot be connected during system initialization after reset. -# This might be a reason for unconnecting ST-Link v2 when deasserting reset. -# As a workaround arp_reset deassert is not called for hla - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -proc ocd_process_reset_inner { MODE } { - if { 0 != [string compare psoc4.cpu [target names]] } { - return -code error "PSoC 4 reset can handle only one psoc4.cpu target"; - } - set t psoc4.cpu - - # If this target must be halted... - set halt -1 - if { 0 == [string compare $MODE halt] } { - set halt 1 - } - if { 0 == [string compare $MODE init] } { - set halt 1; - } - if { 0 == [string compare $MODE run ] } { - set halt 0; - } - if { $halt < 0 } { - return -code error "Invalid mode: $MODE, must be one of: halt, init, or run"; - } - - #$t invoke-event reset-start - $t invoke-event reset-assert-pre - - set TEST_MODE 0x40030014 - if { $halt == 1 } { - mww $TEST_MODE 0x80000000 - } else { - mww $TEST_MODE 0 - } - - $t arp_reset assert 0 - $t invoke-event reset-assert-post - $t invoke-event reset-deassert-pre - if {![using_hla]} { # workaround ST-Link v2 fails and forcing reconnect - $t arp_reset deassert 0 - } - $t invoke-event reset-deassert-post - - # Pass 1 - Now wait for any halt (requested as part of reset - # assert/deassert) to happen. Ideally it takes effect without - # first executing any instructions. - if { $halt } { - # Now PSoC CPU should loop in system ROM - $t arp_waitstate running 200 - $t arp_halt - - # Catch, but ignore any errors. - catch { $t arp_waitstate halted 1000 } - - # Did we succeed? - set s [$t curstate] - - if { 0 != [string compare $s "halted" ] } { - return -code error [format "TARGET: %s - Not halted" $t] - } - - # Check if PSoC CPU is stopped in system ROM - set pc [ocd_reg pc] - regsub {pc[^:]*: } $pc "" pc - if { $pc < 0x10000000 || $pc > 0x1000ffff } { - return -code error [format "TARGET: %s - Not halted in system ROM, use 'reset_config none'" $t] - } - - # Set registers to reset vector values - mem2array value 32 0 2 - reg pc [expr $value(1) & 0xfffffffe ] - reg msp $value(0) - - mww $TEST_MODE 0 - } - - #Pass 2 - if needed "init" - if { 0 == [string compare init $MODE] } { - set err [catch "$t arp_waitstate halted 5000"] - - # Did it halt? - if { $err == 0 } { - $t invoke-event reset-init - } - } - - $t invoke-event reset-end -} diff --git a/tcl/target/psoc5lp.cfg b/tcl/target/psoc5lp.cfg deleted file mode 100644 index 1cdde47..0000000 --- a/tcl/target/psoc5lp.cfg +++ /dev/null @@ -1,32 +0,0 @@ -# -# Cypress PSoC 5LP -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME psoc5lp -} - -if { [info exists CPUTAPID] } { - set _CPU_TAPID $CPUTAPID -} else { - set _CPU_TAPID 0x4BA00477 -} - -if { [using_jtag] } { - set _CPU_DAP_ID $_CPU_TAPID -} else { - set _CPU_DAP_ID 0x2ba01477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -if {![using_hla]} { - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg deleted file mode 100644 index 3862425..0000000 --- a/tcl/target/pxa255.cfg +++ /dev/null @@ -1,59 +0,0 @@ -# PXA255 chip ... originally from Intel, PXA line was sold to Marvell. -# This chip is now at end-of-life. Final orders have been taken. - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME pxa255 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x69264013 -} - -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME xscale -endian $_ENDIAN \ - -chain-position $_CHIPNAME.cpu - -# PXA255 comes out of reset using 3.6864 MHz oscillator. -# Until the PLL kicks in, keep the JTAG clock slow enough -# that we get no errors. -adapter_khz 300 -$_TARGETNAME configure -event "reset-start" { adapter_khz 300 } - -# both TRST and SRST are *required* for debug -# DCSR is often accessed with SRST active -reset_config trst_and_srst separate srst_nogate - -# reset processing that works with PXA -proc init_reset {mode} { - # assert both resets; equivalent to power-on reset - jtag_reset 1 1 - - # drop TRST after at least 32 cycles - sleep 1 - jtag_reset 0 1 - - # minimum 32 TCK cycles to wake up the controller - runtest 50 - - # now the TAP will be responsive; validate scanchain - jtag arp_init - - # ... and take it out of reset - jtag_reset 0 0 -} - -proc jtag_init {} { - init_reset startup -} diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg deleted file mode 100644 index 95f7f16..0000000 --- a/tcl/target/pxa270.cfg +++ /dev/null @@ -1,50 +0,0 @@ -#Marvell/Intel PXA270 Script - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME pxa270 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -#IDs for pxa270. Are there more? -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # set useful default - set _CPUTAPID 0x49265013 -} - -if { [info exists CPUTAPID2] } { - set _CPUTAPID2 $CPUTAPID2 -} else { - # set useful default - set _CPUTAPID2 0x79265013 -} - -if { [info exists CPUTAPID3] } { - set _CPUTAPID2 $CPUTAPID3 -} else { - # set useful default - set _CPUTAPID3 0x89265013 -} - -# set adapter_nsrst_delay to the delay introduced by your reset circuit -# the rest of the needed delays are built into the openocd program -adapter_nsrst_delay 260 -# set the jtag_ntrst_delay to the delay introduced by a reset circuit -# the rest of the needed delays are built into the openocd program -jtag_ntrst_delay 250 - -set _TARGETNAME $_CHIPNAME.cpu -jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 - -target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -# maps to PXA internal RAM. If you are using a PXA255 -# you must initialize SDRAM or leave this option off -$_TARGETNAME configure -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0 diff --git a/tcl/target/pxa3xx.cfg b/tcl/target/pxa3xx.cfg deleted file mode 100644 index c459f6e..0000000 --- a/tcl/target/pxa3xx.cfg +++ /dev/null @@ -1,86 +0,0 @@ -# Marvell PXA3xx - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME pxa3xx -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# IDs for all currently known PXA3xx chips -if { [info exists CPUTAPID_PXA30X_A0] } { - set _CPUTAPID_PXA30X_A0 $CPUTAPID_PXA30X_A0 -} else { - set _CPUTAPID_PXA30X_A0 0x0E648013 -} -if { [info exists CPUTAPID_PXA30X_A1] } { - set _CPUTAPID_PXA30X_A1 $CPUTAPID_PXA30X_A1 -} else { - set _CPUTAPID_PXA30X_A1 0x1E648013 -} -if { [info exists CPUTAPID_PXA31X_A0] } { - set _CPUTAPID_PXA31X_A0 $CPUTAPID_PXA31X_A0 -} else { - set _CPUTAPID_PXA31X_A0 0x0E649013 -} -if { [info exists CPUTAPID_PXA31X_A1] } { - set _CPUTAPID_PXA31X_A1 $CPUTAPID_PXA31X_A1 -} else { - set _CPUTAPID_PXA31X_A1 0x1E649013 -} -if { [info exists CPUTAPID_PXA31X_A2] } { - set _CPUTAPID_PXA31X_A2 $CPUTAPID_PXA31X_A2 -} else { - set _CPUTAPID_PXA31X_A2 0x2E649013 -} -if { [info exists CPUTAPID_PXA31X_B0] } { - set _CPUTAPID_PXA31X_B0 $CPUTAPID_PXA31X_B0 -} else { - set _CPUTAPID_PXA31X_B0 0x3E649013 -} -if { [info exists CPUTAPID_PXA32X_B1] } { - set _CPUTAPID_PXA32X_B1 $CPUTAPID_PXA32X_B1 -} else { - set _CPUTAPID_PXA32X_B1 0x5E642013 -} -if { [info exists CPUTAPID_PXA32X_B2] } { - set _CPUTAPID_PXA32X_B2 $CPUTAPID_PXA32X_B2 -} else { - set _CPUTAPID_PXA32X_B2 0x6E642013 -} -if { [info exists CPUTAPID_PXA32X_C0] } { - set _CPUTAPID_PXA32X_C0 $CPUTAPID_PXA32X_C0 -} else { - set _CPUTAPID_PXA32X_C0 0x7E642013 -} - -# set adapter_nsrst_delay to the delay introduced by your reset circuit -# the rest of the needed delays are built into the openocd program -adapter_nsrst_delay 260 - -# set the jtag_ntrst_delay to the delay introduced by a reset circuit -# the rest of the needed delays are built into the openocd program -jtag_ntrst_delay 250 - -set _TARGETNAME $_CHIPNAME.cpu -jtag newtap $_CHIPNAME cpu -irlen 11 -ircapture 0x1 -irmask 0x7f \ - -expected-id $_CPUTAPID_PXA30X_A0 \ - -expected-id $_CPUTAPID_PXA30X_A1 \ - -expected-id $_CPUTAPID_PXA31X_A0 \ - -expected-id $_CPUTAPID_PXA31X_A1 \ - -expected-id $_CPUTAPID_PXA31X_A2 \ - -expected-id $_CPUTAPID_PXA31X_B0 \ - -expected-id $_CPUTAPID_PXA32X_B1 \ - -expected-id $_CPUTAPID_PXA32X_B2 \ - -expected-id $_CPUTAPID_PXA32X_C0 - -target create $_TARGETNAME xscale -endian $_ENDIAN \ - -chain-position $_TARGETNAME - -# work area in internal RAM. -$_TARGETNAME configure -work-area-phys 0x5c030000 -work-area-size 0x10000 diff --git a/tcl/target/quark_d20xx.cfg b/tcl/target/quark_d20xx.cfg deleted file mode 100644 index 419f9dc..0000000 --- a/tcl/target/quark_d20xx.cfg +++ /dev/null @@ -1,50 +0,0 @@ -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x38289013 -} - -jtag newtap quark_d20xx quark -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable -jtag newtap quark_d20xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e786013 -enable - -proc quark_d20xx_tapenable {} { - echo "enabling quark core tap" - irscan quark_d20xx.cltap 0x11 - drscan quark_d20xx.cltap 12 1 - runtest 10 -} - -proc quark_d20xx_tapdisable {} { - echo "disabling quark core tap" - irscan quark_d20xx.cltap 0x11 - drscan quark_d20xx.cltap 12 0 - runtest 10 -} - -proc quark_d20xx_setup {} { - jtag tapenable quark_d20xx.quark -} - -jtag configure quark_d20xx.quark -event tap-enable \ - "quark_d20xx_tapenable" - -jtag configure quark_d20xx.quark -event tap-disable \ - "quark_d20xx_tapdisable" - -target create quark_d20xx.quark quark_d20xx -endian little -chain-position quark_d20xx.quark - -quark_d20xx.quark configure -event gdb-attach { halt } - -quark_d20xx.quark configure -event reset-start { - # need to halt the target to write to memory - if {[quark_d20xx.quark curstate] ne "halted"} { halt } - # set resetbreak via the core tap - irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x1 - # trigger a warm reset - mww 0xb0800570 0x2 - # clear resetbreak - irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x0 -} - -jtag configure quark_d20xx.quark -event setup \ - "quark_d20xx_setup" diff --git a/tcl/target/quark_x10xx.cfg b/tcl/target/quark_x10xx.cfg deleted file mode 100644 index a5bbfb4..0000000 --- a/tcl/target/quark_x10xx.cfg +++ /dev/null @@ -1,52 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME quark_x10xx -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x18289013 -} - -jtag newtap quark_x10xx cpu -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable -jtag newtap quark_x10xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e681013 -enable - -#openocd puts tap at front of chain not end of chain -proc quark_x10xx_tapenable {} { - echo "enabling core tap" - irscan quark_x10xx.cltap 0x11 - drscan quark_x10xx.cltap 64 1 - runtest 10 -} - -proc quark_x10xx_tapdisable {} { - echo "disabling core tap" - irscan quark_x10xx.cltap 0x11 - drscan quark_x10xx.cltap 64 0 - runtest 10 -} - -proc quark_x10xx_setup {} { - jtag tapenable quark_x10xx.cpu -} - -jtag configure $_CHIPNAME.cpu -event tap-enable \ - "quark_x10xx_tapenable" - -jtag configure $_CHIPNAME.cpu -event tap-disable \ - "quark_x10xx_tapdisable" - -set _TARGETNAME $_CHIPNAME.cpu -target create quark_x10xx.cpu quark_x10xx -endian $_ENDIAN -chain-position quark_x10xx.cpu - -jtag configure $_CHIPNAME.cpu -event setup \ - "quark_x10xx_setup" diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt deleted file mode 100644 index f028b11..0000000 --- a/tcl/target/readme.txt +++ /dev/null @@ -1,41 +0,0 @@ -Prerequisites: -The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands -do the same thing across all the targets. - -Rules to follow when writing scripts: - -1. The configuration script should be defined such as , for example, the following sequences are working: - reset - flash info <bank> -and - reset - flash erase_address <start> <len> -and - reset init - load - -In most cases this can be accomplished by specifying the default startup mode as reset_init (target command -in the configuration file). - -2. If the target is correctly configured, flash must be writable without any other helper commands. It is -assumed that all write-protect mechanisms should be disabled. - -3. The configuration scripts should be defined such as the binary that was written to flash verifies -(turn off remapping, checksums, etc...) - -flash write_image [file] <parameters> -verify_image [file] <parameters> - -4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked -multiple times only the last setting is used. - -interface/xxx.cfg files are always executed *before* target/xxx.cfg -files, so any adapter_khz in interface/xxx.cfg will be overridden by -target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively, -set the default JTAG speed. - -Note that a target/xxx.cfg file can invoke another target/yyy.cfg file, -so one can create target subtype configurations where e.g. only -amount of DRAM, oscillator speeds differ and having a single -config file for the default/common settings. - diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg deleted file mode 100644 index a09377b..0000000 --- a/tcl/target/renesas_s7g2.cfg +++ /dev/null @@ -1,50 +0,0 @@ -# -# Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME s7g2 -} - -if { [info exists CPU_JTAG_TAPID] } { - set _CPU_JTAG_TAPID $CPU_JTAG_TAPID -} else { - set _CPU_JTAG_TAPID 0x5ba00477 -} - -if { [info exists CPU_SWD_TAPID] } { - set _CPU_SWD_TAPID $CPU_SWD_TAPID -} else { - set _CPU_SWD_TAPID 0x5ba02477 -} - -source [find target/swj-dp.tcl] - -if { [using_jtag] } { - set _CPU_TAPID $_CPU_JTAG_TAPID -} else { - set _CPU_TAPID $_CPU_SWD_TAPID -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - # 640 KB On-Chip SRAM - set _WORKAREASIZE 0xa0000 -} - -$_TARGETNAME configure -work-area-phys 0x1ffe0000 \ - -work-area-size $_WORKAREASIZE -work-area-backup 0 - -if { ![using_hla] } { - cortex_m reset_config sysresetreq -} - -adapter_khz 1000 diff --git a/tcl/target/samsung_s3c2410.cfg b/tcl/target/samsung_s3c2410.cfg deleted file mode 100644 index 017c104..0000000 --- a/tcl/target/samsung_s3c2410.cfg +++ /dev/null @@ -1,36 +0,0 @@ -# Found on the 'TinCanTools' Hammer board. - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME s3c2410 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # This config file was defaulting to big endian.. - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # Force an error until we get a good number. - set _CPUTAPID 0xffffffff -} - -#use combined on interfaces or targets that cannot set TRST/SRST separately -reset_config trst_and_srst - -#jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0 - -# speed up memory downloads -arm7_9 fast_memory_access enable -arm7_9 dcc_downloads enable diff --git a/tcl/target/samsung_s3c2440.cfg b/tcl/target/samsung_s3c2440.cfg deleted file mode 100644 index 2a0a915..0000000 --- a/tcl/target/samsung_s3c2440.cfg +++ /dev/null @@ -1,35 +0,0 @@ -# Target configuration for the Samsung 2440 system on chip -# Tested on a S3C2440 Evaluation board by keesj -# Processor : ARM920Tid(wb) rev 0 (v4l) -# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME s3c2440 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a bigendian - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0032409d -} - -#jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1 - -#reset configuration -reset_config trst_and_srst - diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg deleted file mode 100644 index 1bc4f2d..0000000 --- a/tcl/target/samsung_s3c2450.cfg +++ /dev/null @@ -1,48 +0,0 @@ -# Target configuration for the Samsung 2450 system on chip -# Processor : ARM926ejs (wb) rev 0 (v4l) -# Info: JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F - - -# FIX!!! what to use here? -# -# RCLK? -# -# adapter_khz 0 -# -# Really low clock during reset? -# -# adapter_khz 1 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME s3c2450 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a bigendian - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926f0f -} - -#jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -# FIX!!!!! should this really use srst_pulls_trst? -# With srst_pulls_trst "reset halt" will not reset into the -# halted mode, but rather "reset run" and then halt the target. -# -# However, without "srst_pulls_trst", then "reset halt" produces weird -# errors: -# WARNING: unknown debug reason: 0x0 -reset_config trst_and_srst diff --git a/tcl/target/samsung_s3c4510.cfg b/tcl/target/samsung_s3c4510.cfg deleted file mode 100644 index 461d047..0000000 --- a/tcl/target/samsung_s3c4510.cfg +++ /dev/null @@ -1,24 +0,0 @@ -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME s3c4510 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - - -# This appears to be a "Version 1" arm7tdmi. -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x1f0f0f0f -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg deleted file mode 100644 index 88fe966..0000000 --- a/tcl/target/samsung_s3c6410.cfg +++ /dev/null @@ -1,51 +0,0 @@ -# -*- tcl -*- -# Target configuration for the Samsung s3c6410 system on chip -# Tested on a SMDK6410 -# Processor : ARM1176 -# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) -# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places] -# [and I do not believe it to be accurate, hence the 0xffffffff below] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME s3c6410 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a bigendian - set _ENDIAN little -} - -# trace buffer -if { [info exists ETBTAPID] } { - set _ETBTAPID $ETBTAPID -} else { - set _ETBTAPID 0x2b900f0f -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07b76f0f -} - -#jtag scan chain - -jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETBTAPID -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME - -adapter_nsrst_delay 500 -jtag_ntrst_delay 500 - -#reset configuration -reset_config trst_and_srst - -# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/sharp_lh79532.cfg b/tcl/target/sharp_lh79532.cfg deleted file mode 100644 index 6f2cf22..0000000 --- a/tcl/target/sharp_lh79532.cfg +++ /dev/null @@ -1,26 +0,0 @@ -reset_config srst_only srst_pulls_trst - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lh79532 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # sharp changed the number! - set _CPUTAPID 0x00002061 -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - - diff --git a/tcl/target/sim3x.cfg b/tcl/target/sim3x.cfg deleted file mode 100755 index f721f36..0000000 --- a/tcl/target/sim3x.cfg +++ /dev/null @@ -1,55 +0,0 @@ -# -# Silicon Laboratories SiM3x Cortex-M3 -# - -# SiM3x devices support both JTAG and SWD transports. -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME SiM3x -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -if { [info exists CPURAMSIZE] } { - set _CPURAMSIZE $CPURAMSIZE -} else { -# Minimum size of RAM in the Silicon Labs product matrix (8KB) - set _CPURAMSIZE 0x2000 -} - -if { [info exists CPUROMSIZE] } { - set _CPUROMSIZE $CPUROMSIZE -} else { -# Minimum size of FLASH in the Silicon Labs product matrix (32KB) - set _CPUROMSIZE 0x8000 -} - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE $_CPURAMSIZE -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME - -adapter_khz 1000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} diff --git a/tcl/target/smp8634.cfg b/tcl/target/smp8634.cfg deleted file mode 100644 index c13414c..0000000 --- a/tcl/target/smp8634.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# script for Sigma Designs SMP8634 (eventually even SMP8635) - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME smp8634 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x08630001 -} - -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -reset_config trst_and_srst separate - -# jtag scan chain -# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian $_ENDIAN diff --git a/tcl/target/spear3xx.cfg b/tcl/target/spear3xx.cfg deleted file mode 100644 index a86a3c4..0000000 --- a/tcl/target/spear3xx.cfg +++ /dev/null @@ -1,41 +0,0 @@ -# Target configuration for the ST SPEAr3xx family of system on chip -# Supported SPEAr300, SPEAr310, SPEAr320 -# http://www.st.com/spear -# -# Processor: ARM926ejs -# Info: JTAG tap: spear3xx.cpu tap/device found: 0x07926041 -# Date: 2009-10-31 -# Author: Antonio Borneo <borneo.antonio@gmail.com> - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME spear3xx -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926041 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x03 \ - -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN \ - -chain-position $_TARGETNAME - -# SPEAr3xx has a 8K block of sram @ 0xd280.0000 -# REVISIT: what OS puts virtual address equal to phys? -$_TARGETNAME configure \ - -work-area-virt 0xd2800000 \ - -work-area-phys 0xd2800000 \ - -work-area-size 0x2000 \ - -work-area-backup 0 diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg deleted file mode 100644 index 4fe9939..0000000 --- a/tcl/target/stellaris.cfg +++ /dev/null @@ -1,176 +0,0 @@ -# TI/Luminary Stellaris LM3S chip family - -# Some devices have errata in returning their device class. -# DEVICECLASS is provided as a manual override -# Manual setting of a device class of 0xff is not allowed - -global _DEVICECLASS - -if { [info exists DEVICECLASS] } { - set _DEVICECLASS $DEVICECLASS -} else { - set _DEVICECLASS 0xff -} - -# Luminary chips support both JTAG and SWD transports. -# Adapt based on what transport is active. -source [find target/swj-dp.tcl] - -# For now we ignore the SPI and UART options, which -# are usable only for ISP style initial flash programming. - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lm3s -} - -# CPU TAP ID 0x1ba00477 for early Sandstorm parts -# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2 -# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil) -# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm) -# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard) -# ... we'll ignore the JTAG version field, rather than list every -# chip revision that turns up. -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0ba00477 -} - -# SWD DAP, and JTAG TAP, take same params for now; -# ... even though SWD ignores all except TAPID, and -# JTAG shouldn't need anything more then irlen. (and TAPID). -swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \ - -expected-id $_CPUTAPID -ignore-version - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - # default to 2K working area - set _WORKAREASIZE 0x800 -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu - -# 8K working area at base of ram, not backed up -# -# NOTE: you may need or want to reconfigure the work area; -# some parts have just 6K, and you may want to use other -# addresses (at end of mem not beginning) or back it up. -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE - -# JTAG speed ... slow enough to work with a 12 MHz RC oscillator; -# LM3S parts don't support RTCK -# -# NOTE: this may be increased by a reset-init handler, after it -# configures and enables the PLL. Or you might need to decrease -# this, if you're using a slower clock. -adapter_khz 500 - -source [find mem_helper.tcl] - -proc reset_peripherals {family} { - - source [find chip/ti/lm3s/lm3s.tcl] - - echo "Resetting Core Peripherals" - - # Disable the PLL and the system clock divider (nop if disabled) - mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV - mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0 - - # RCC and RCC2 to their reset values - mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))] - mww $SYSCTL_RCC2 0x07806810 - mww $SYSCTL_RCC 0x078e3ad1 - - # Reset the deep sleep clock configuration register - mww $SYSCTL_DSLPCLKCFG 0x07800000 - - # Reset the clock gating registers - mww $SYSCTL_RCGC0 0x00000040 - mww $SYSCTL_RCGC1 0 - mww $SYSCTL_RCGC2 0 - mww $SYSCTL_SCGC0 0x00000040 - mww $SYSCTL_SCGC1 0 - mww $SYSCTL_SCGC2 0 - mww $SYSCTL_DCGC0 0x00000040 - mww $SYSCTL_DCGC1 0 - mww $SYSCTL_DCGC2 0 - - # Reset the remaining SysCtl registers - mww $SYSCTL_PBORCTL 0 - mww $SYSCTL_IMC 0 - mww $SYSCTL_GPIOHBCTL 0 - mww $SYSCTL_MOSCCTL 0 - mww $SYSCTL_PIOSCCAL 0 - mww $SYSCTL_I2SMCLKCFG 0 - - # Reset the peripherals - mww $SYSCTL_SRCR0 0xffffffff - mww $SYSCTL_SRCR1 0xffffffff - mww $SYSCTL_SRCR2 0xffffffff - mww $SYSCTL_SRCR0 0 - mww $SYSCTL_SRCR1 0 - mww $SYSCTL_SRCR2 0 - - # Clear any pending SysCtl interrupts - mww $SYSCTL_MISC 0xffffffff - - # Wait for any pending flash operations to complete - while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 } - while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 } - - # Reset the flash controller registers - mww $FLASH_FMA 0 - mww $FLASH_FCIM 0 - mww $FLASH_FCMISC 0xffffffff - mww $FLASH_FWBVAL 0 -} - -$_TARGETNAME configure -event reset-start { - adapter_khz 500 - - # - # When nRST is asserted on most Stellaris devices, it clears some of - # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong; - # and OpenOCD depends on those TRMs. So we won't use SRST on those - # chips. (Only power-on reset should affect debug state, beyond a - # few specified bits; not the chip's nRST input, wired to SRST.) - # - # REVISIT current errata specs don't seem to cover this issue. - # Do we have more details than this email? - # https://lists.berlios.de/pipermail - # /openocd-development/2008-August/003065.html - # - - global _DEVICECLASS - - if {$_DEVICECLASS != 0xff} { - set device_class $_DEVICECLASS - } else { - set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)] - } - - if {$device_class == 0 || $device_class == 1 || - $device_class == 3 || $device_class == 5 || $device_class == 0xa} { - if {![using_hla]} { - # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ - cortex_m reset_config sysresetreq - } - } else { - if {![using_hla]} { - # Tempest and Firestorm default to using NVIC VECTRESET - # peripherals will need reseting manually, see proc reset_peripherals - cortex_m reset_config vectreset - } - # reset peripherals, based on code in - # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf - reset_peripherals $device_class - } -} - -# flash configuration ... autodetects sizes, autoprobed -flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME diff --git a/tcl/target/stellaris_icdi.cfg b/tcl/target/stellaris_icdi.cfg deleted file mode 100644 index f856a7a..0000000 --- a/tcl/target/stellaris_icdi.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/stellaris_icdi.cfg is deprecated, please switch to target/stellaris.cfg" -source [find target/stellaris.cfg] diff --git a/tcl/target/stm32_stlink.cfg b/tcl/target/stm32_stlink.cfg deleted file mode 100644 index 295292e..0000000 --- a/tcl/target/stm32_stlink.cfg +++ /dev/null @@ -1 +0,0 @@ -echo "WARNING: stm32_stlink.cfg is deprecated (and does nothing, you can safely remove it.)" diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg deleted file mode 100644 index 2b48cfc..0000000 --- a/tcl/target/stm32f0x.cfg +++ /dev/null @@ -1,86 +0,0 @@ -# script for stm32f0x family - -# -# stm32 devices support SWD transports only. -# -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32f0x -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# By default use 4kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x1000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # See STM Document RM0091 - # Section 29.5.3 - set _CPUTAPID 0x0bb11477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# flash size will be probed -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME - -# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -adapter_khz 1000 - -adapter_nsrst_delay 100 - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -proc stm32f0x_default_reset_start {} { - # Reset clock is HSI (8 MHz) - adapter_khz 1000 -} - -proc stm32f0x_default_examine_end {} { - # Enable debug during low power modes (uses more power) - mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP - - # Stop watchdog counters during halt - mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP -} - -proc stm32f0x_default_reset_init {} { - # Configure PLL to boost clock to HSI x 6 (48 MHz) - mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2] - mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON - mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0] - sleep 10 ;# Wait for PLL to lock - mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] - - # Boost JTAG frequency - adapter_khz 8000 -} - -# Default hooks -$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end } -$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start } -$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init } diff --git a/tcl/target/stm32f0x_stlink.cfg b/tcl/target/stm32f0x_stlink.cfg deleted file mode 100644 index cecfb7a..0000000 --- a/tcl/target/stm32f0x_stlink.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/stm32f0x_stlink.cfg is deprecated, please switch to target/stm32f0x.cfg" -source [find target/stm32f0x.cfg] diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg deleted file mode 100644 index bd02e95..0000000 --- a/tcl/target/stm32f1x.cfg +++ /dev/null @@ -1,109 +0,0 @@ -# script for stm32f1x family - -# -# stm32 devices support both JTAG and SWD transports. -# -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32f1x -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# By default use 4kB (as found on some STM32F100s) -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x1000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - # See STM Document RM0008 Section 26.6.3 - set _CPUTAPID 0x3ba00477 - } { - # this is the SW-DP tap id not the jtag tap id - set _CPUTAPID 0x1ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID] } { - # FIXME this never gets used to override defaults... - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0008 - # Section 29.6.2 - # Low density devices, Rev A - set _BSTAPID1 0x06412041 - # Medium density devices, Rev A - set _BSTAPID2 0x06410041 - # Medium density devices, Rev B and Rev Z - set _BSTAPID3 0x16410041 - set _BSTAPID4 0x06420041 - # High density devices, Rev A - set _BSTAPID5 0x06414041 - # Connectivity line devices, Rev A and Rev Z - set _BSTAPID6 0x06418041 - # XL line devices, Rev A - set _BSTAPID7 0x06430041 - # VL line devices, Rev A and Z In medium-density and high-density value line devices - set _BSTAPID8 0x06420041 - # VL line devices, Rev A - set _BSTAPID9 0x06428041 -} - -if {[using_jtag]} { - swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ - -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \ - -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \ - -expected-id $_BSTAPID8 -expected-id $_BSTAPID9 -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# flash size will be probed -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -adapter_khz 1000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -$_TARGETNAME configure -event examine-end { - # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP | - # DBG_STANDBY | DBG_STOP | DBG_SLEEP - mmw 0xE0042004 0x00000307 0 -} - -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment - mmw 0xE0042004 0x00000020 0 -} diff --git a/tcl/target/stm32f1x_stlink.cfg b/tcl/target/stm32f1x_stlink.cfg deleted file mode 100644 index 0a3e643..0000000 --- a/tcl/target/stm32f1x_stlink.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/stm32f1x_stlink.cfg is deprecated, please switch to target/stm32f1x.cfg" -source [find target/stm32f1x.cfg] diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg deleted file mode 100644 index 0e734de..0000000 --- a/tcl/target/stm32f2x.cfg +++ /dev/null @@ -1,96 +0,0 @@ -# script for stm32f2x family - -# -# stm32 devices support both JTAG and SWD transports. -# -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32f2x -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# By default use 64kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x10000 -} - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -# -# Since we may be running of an RC oscilator, we crank down the speed a -# bit more to be on the safe side. Perhaps superstition, but if are -# running off a crystal, we can run closer to the limit. Note -# that there can be a pretty wide band where things are more or less stable. -adapter_khz 1000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - # See STM Document RM0033 - # Section 32.6.3 - corresponds to Cortex-M3 r2p0 - set _CPUTAPID 0x4ba00477 - } { - set _CPUTAPID 0x2ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID] } { - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0033 - # Section 32.6.2 - # - set _BSTAPID 0x06411041 -} - -if {[using_jtag]} { - swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -$_TARGETNAME configure -event examine-end { - # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP - mmw 0xE0042004 0x00000007 0 - - # Stop watchdog counters during halt - # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP - mmw 0xE0042008 0x00001800 0 -} - -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment - mmw 0xE0042004 0x00000020 0 -} diff --git a/tcl/target/stm32f2x_stlink.cfg b/tcl/target/stm32f2x_stlink.cfg deleted file mode 100644 index 451b2b5..0000000 --- a/tcl/target/stm32f2x_stlink.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/stm32f2x_stlink.cfg is deprecated, please switch to target/stm32f2x.cfg" -source [find target/stm32f2x.cfg] diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg deleted file mode 100644 index f3ea40b..0000000 --- a/tcl/target/stm32f3x.cfg +++ /dev/null @@ -1,127 +0,0 @@ -# script for stm32f3x family - -# -# stm32 devices support both JTAG and SWD transports. -# -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32f3x -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# By default use 16kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -# -# Since we may be running of an RC oscilator, we crank down the speed a -# bit more to be on the safe side. Perhaps superstition, but if are -# running off a crystal, we can run closer to the limit. Note -# that there can be a pretty wide band where things are more or less stable. -adapter_khz 1000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - # See STM Document RM0316 - # Section 29.6.3 - corresponds to Cortex-M4 r0p1 - set _CPUTAPID 0x4ba00477 - } { - set _CPUTAPID 0x2ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID] } { - set _BSTAPID $BSTAPID -} else { - # STM Document RM0316 rev 5 for STM32F302/303 B/C size - set _BSTAPID1 0x06422041 - # STM Document RM0313 rev 3 for STM32F37x - set _BSTAPID2 0x06432041 - # STM Document RM364 rev 1 for STM32F334 - set _BSTAPID3 0x06438041 - # STM Document RM316 rev 5 for STM32F303 6/8 size - # STM Document RM365 rev 3 for STM32F302 6/8 size - # STM Document RM366 rev 2 for STM32F301 6/8 size - set _BSTAPID4 0x06439041 - # STM Document RM016 rev 5 for STM32F303 D/E size - set _BSTAPID5 0x06446041 -} - -if {[using_jtag]} { - swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ - -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -proc stm32f3x_default_reset_start {} { - # Reset clock is HSI (8 MHz) - adapter_khz 1000 -} - -proc stm32f3x_default_examine_end {} { - # Enable debug during low power modes (uses more power) - mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP - - # Stop watchdog counters during halt - mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP -} - -proc stm32f3x_default_reset_init {} { - # Configure PLL to boost clock to HSI x 8 (64 MHz) - mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] - mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON - mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] - sleep 10 ;# Wait for PLL to lock - mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] - - # Boost JTAG frequency - adapter_khz 8000 -} - -# Default hooks -$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end } -$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start } -$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init } - -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment - mmw 0xe0042004 0x00000020 0 -} diff --git a/tcl/target/stm32f3x_stlink.cfg b/tcl/target/stm32f3x_stlink.cfg deleted file mode 100644 index 8769358..0000000 --- a/tcl/target/stm32f3x_stlink.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/stm32f3x_stlink.cfg is deprecated, please switch to target/stm32f3x.cfg" -source [find target/stm32f3x.cfg] diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg deleted file mode 100644 index 2d5cf37..0000000 --- a/tcl/target/stm32f4x.cfg +++ /dev/null @@ -1,137 +0,0 @@ -# script for stm32f4x family - -# -# stm32 devices support both JTAG and SWD transports. -# -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32f4x -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# By default use 32kB (Available RAM in smallest device STM32F410) -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x8000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - # See STM Document RM0090 - # Section 38.6.3 - corresponds to Cortex-M4 r0p1 - set _CPUTAPID 0x4ba00477 - } { - set _CPUTAPID 0x2ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID] } { - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0090 - # Section 38.6.2 - # STM32F405xx/07xx and STM32F415xx/17xx - set _BSTAPID1 0x06413041 - # STM32F42xxx and STM32F43xxx - set _BSTAPID2 0x06419041 - # See STM Document RM0368 (Rev. 3) - # STM32F401B/C - set _BSTAPID3 0x06423041 - # STM32F401D/E - set _BSTAPID4 0x06433041 - # See STM Document RM0383 (Rev 2) - # STM32F411 - set _BSTAPID5 0x06431041 - # See STM Document RM0386 - # STM32F469 - set _BSTAPID6 0x06434041 - # See STM Document RM0401 - # STM32F410 - set _BSTAPID7 0x06458041 - # STM32F412 - set _BSTAPID8 0x06441041 -} - -if {[using_jtag]} { - swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ - -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \ - -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \ - -expected-id $_BSTAPID8 -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz -# -# Since we may be running of an RC oscilator, we crank down the speed a -# bit more to be on the safe side. Perhaps superstition, but if are -# running off a crystal, we can run closer to the limit. Note -# that there can be a pretty wide band where things are more or less stable. -adapter_khz 2000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -$_TARGETNAME configure -event examine-end { - # Enable debug during low power modes (uses more power) - # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP - mmw 0xE0042004 0x00000007 0 - - # Stop watchdog counters during halt - # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP - mmw 0xE0042008 0x00001800 0 -} - -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment - mmw 0xE0042004 0x00000020 0 -} - -$_TARGETNAME configure -event reset-init { - # Configure PLL to boost clock to HSI x 4 (64 MHz) - mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P) - mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency) - mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON - sleep 10 ;# Wait for PLL to lock - mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2 - mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL - - # Boost JTAG frequency - adapter_khz 8000 -} - -$_TARGETNAME configure -event reset-start { - # Reduce speed since CPU speed will slow down to 16MHz with the reset - adapter_khz 2000 -} diff --git a/tcl/target/stm32f4x_stlink.cfg b/tcl/target/stm32f4x_stlink.cfg deleted file mode 100644 index af3e8a0..0000000 --- a/tcl/target/stm32f4x_stlink.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/stm32f4x_stlink.cfg is deprecated, please switch to target/stm32f4x.cfg" -source [find target/stm32f4x.cfg] diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg deleted file mode 100755 index 05470d4..0000000 --- a/tcl/target/stm32f7x.cfg +++ /dev/null @@ -1,92 +0,0 @@ -# script for stm32f7x family - -# -# stm32f7 devices support both JTAG and SWD transports. -# -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32f7x -} - - set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# By default use 128kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x20000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - # See STM Document RM0385 - # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0 - set _CPUTAPID 0x5ba00477 - } { - set _CPUTAPID 0x5ba02477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID] } { - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0385 - # Section 40.6.1 - # STM32F75xxG - set _BSTAPID1 0x06449041 -} - -if {[using_jtag]} { - swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME - -# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz -adapter_khz 2000 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -# use hardware reset, connect under reset -reset_config srst_only srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -$_TARGETNAME configure -event examine-end { - # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP - mmw 0xE0042004 0x00000007 0 - - # Stop watchdog counters during halt - # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP - mmw 0xE0042008 0x00001800 0 -} - -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment - mmw 0xE0042004 0x00000020 0 -} diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg deleted file mode 100644 index fd8f951..0000000 --- a/tcl/target/stm32l0.cfg +++ /dev/null @@ -1,77 +0,0 @@ -# -# M0+ devices only have SW-DP, but swj-dp code works, just don't -# set any jtag related features -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32l0 -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# By default use 8kB (max ram on smallest part) -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x2000 -} - -# JTAG speed should be <= F_CPU/6. -# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz -adapter_khz 300 - -adapter_nsrst_delay 100 - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - # Arm, m0+, non-multidrop. - # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html - set _CPUTAPID 0x0bc11477 -} - -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# flash size will be probed -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -proc stm32l0_enable_HSI16 {} { - # Enable HSI16 as clock source - echo "STM32L0: Enabling HSI16" - - # Set HSI16ON in RCC_CR (leave MSI enabled) - mww 0x40021000 0x00000101 - - # Set HSI16 as SYSCLK (RCC_CFGR) - mww 0x4002100c 0x00000001 - - # Increase speed - adapter_khz 2500 -} - -$_TARGETNAME configure -event reset-init { - stm32l0_enable_HSI16 -} - -$_TARGETNAME configure -event reset-start { - adapter_khz 300 -} diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg deleted file mode 100644 index 790c495..0000000 --- a/tcl/target/stm32l1.cfg +++ /dev/null @@ -1,126 +0,0 @@ -# -# stm32l1 devices support both JTAG and SWD transports. -# - -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32l1 -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# By default use 10kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x2800 -} - -# JTAG speed should be <= F_CPU/6. -# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz -adapter_khz 300 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - # See STM Document RM0038 - # Section 30.6.3 - corresponds to Cortex-M3 r2p0 - set _CPUTAPID 0x4ba00477 - } else { - # SWD IDCODE (single drop, arm) - set _CPUTAPID 0x2ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID] } { - # FIXME this never gets used to override defaults... - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0038 Section 30.6.1 Rev. 12 - - # Low and medium density - set _BSTAPID1 0x06416041 - # Cat.2 device (medium+ density) - set _BSTAPID2 0x06429041 - # Cat.3 device (medium+ density) - set _BSTAPID3 0x06427041 - # Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models - set _BSTAPID4 0x06436041 - # Cat.5 device (high density), STM32L15/6xxE - set _BSTAPID5 0x06437041 -} - -if {[using_jtag]} { - swj_newdap $_CHIPNAME bs -irlen 5 \ - -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# flash size will be probed -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -proc stm32l_enable_HSI {} { - # Enable HSI as clock source - echo "STM32L: Enabling HSI" - - # Set HSION in RCC_CR - mww 0x40023800 0x00000101 - - # Set HSI as SYSCLK - mww 0x40023808 0x00000001 - - # Increase JTAG speed - adapter_khz 2000 -} - -$_TARGETNAME configure -event reset-init { - stm32l_enable_HSI -} - -$_TARGETNAME configure -event reset-start { - adapter_khz 300 -} - -$_TARGETNAME configure -event examine-end { - # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP - mmw 0xE0042004 0x00000007 0 - - # Stop watchdog counters during halt - # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP - mmw 0xE0042008 0x00001800 0 -} - -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment - mmw 0xE0042004 0x00000020 0 -} diff --git a/tcl/target/stm32l1x_dual_bank.cfg b/tcl/target/stm32l1x_dual_bank.cfg deleted file mode 100644 index a3f7413..0000000 --- a/tcl/target/stm32l1x_dual_bank.cfg +++ /dev/null @@ -1,8 +0,0 @@ -source [find target/stm32l1.cfg] - -# The stm32l1x 384kb have a dual bank flash. -# Let's add a definition for the second bank here. - -# Add the second flash bank. -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg deleted file mode 100644 index dec0069..0000000 --- a/tcl/target/stm32l4x.cfg +++ /dev/null @@ -1,111 +0,0 @@ -# script for stm32l4x family - -# -# stm32l4 devices support both JTAG and SWD transports. -# -source [find target/swj-dp.tcl] -source [find mem_helper.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32l4x -} - -set _ENDIAN little - -# Work-area is a space in RAM used for flash programming -# Smallest current target has 64kB ram, use 32kB by default to avoid surprises -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x8000 -} - -#jtag scan chain -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - # See STM Document RM0351 - # Section 44.6.3 - corresponds to Cortex-M4 r0p1 - set _CPUTAPID 0x4ba00477 - } { - set _CPUTAPID 0x2ba01477 - } -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID] } { - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0351 - # Section 44.6.3 - # STM32L4X6 - set _BSTAPID1 0x06415041 -} - -if {[using_jtag]} { - swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME - -# Common knowledges tells JTAG speed should be <= F_CPU/6. -# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on -# the safe side. -# -# Note that there is a pretty wide band where things are -# more or less stable, see http://openocd.zylin.com/#/c/3366/ -adapter_khz 500 - -adapter_nsrst_delay 100 -if {[using_jtag]} { - jtag_ntrst_delay 100 -} - -reset_config srst_nogate - -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} - -$_TARGETNAME configure -event reset-init { - # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz). - # Use MSI 24 MHz clock, compliant even with VOS == 2. - # 3 WS compliant with VOS == 2 and 24 MHz. - mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency) - mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10 - # Boost JTAG frequency - adapter_khz 4000 -} - -$_TARGETNAME configure -event reset-start { - # Reset clock is MSI (4 MHz) - adapter_khz 500 -} - -$_TARGETNAME configure -event examine-end { - # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP - mmw 0xE0042004 0x00000007 0 - - # Stop watchdog counters during halt - # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP - mmw 0xE0042008 0x00001800 0 -} - -$_TARGETNAME configure -event trace-config { - # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment - mmw 0xE0042004 0x00000020 0 -} diff --git a/tcl/target/stm32lx_stlink.cfg b/tcl/target/stm32lx_stlink.cfg deleted file mode 100644 index 5f694b5..0000000 --- a/tcl/target/stm32lx_stlink.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/stm32lx_stlink.cfg is deprecated, please switch to target/stm32l1.cfg" -source [find target/stm32l1.cfg] diff --git a/tcl/target/stm32w108_stlink.cfg b/tcl/target/stm32w108_stlink.cfg deleted file mode 100644 index 120feea..0000000 --- a/tcl/target/stm32w108_stlink.cfg +++ /dev/null @@ -1,2 +0,0 @@ -echo "WARNING: target/stm32w108xx_stlink.cfg is deprecated, please switch to target/stm32w108xx.cfg" -source [find target/stm32w108xx.cfg] diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg deleted file mode 100644 index d07afc4..0000000 --- a/tcl/target/stm32w108xx.cfg +++ /dev/null @@ -1,70 +0,0 @@ -# -# Target configuration for the ST STM32W108xx chips -# -# Processor: ARM Cortex-M3 -# Date: 2013-06-09 -# Author: Giuseppe Barba <giuseppe.barba@gmail.com> - -# -# stm32 devices support both JTAG and SWD transports. -# -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] == 0 } { - set _CHIPNAME stm32w108 -} else { - set _CHIPNAME $CHIPNAME -} - -# Work-area is a space in RAM used for flash programming -# By default use 8kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x2000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x3ba00477 - } { - set _CPUTAPID 0x1ba01477 - } -} - -set _ENDIAN little - -swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if {[using_jtag]} { - if { [info exists BSTAPID] } { - set _BSTAPID $BSTAPID - swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID - } else { - set _BSTAPID_1 0x169a862b - set _BSTAPID_2 0x269a862b - swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \ - -expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2 - } -} -# -# Set Target -# -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - - -# Use the flash driver from the EM357 -set _FLASHNAME $_CHIPNAME.flash - -# 64k (0x10000) of flash -flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME - -reset_config srst_nogate - -if {![using_hla]} { - cortex_m reset_config sysresetreq -} diff --git a/tcl/target/stm32xl.cfg b/tcl/target/stm32xl.cfg deleted file mode 100644 index f72896d..0000000 --- a/tcl/target/stm32xl.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# script for stm32xl family (dual flash bank) -source [find target/stm32f1x.cfg] - -# flash size will be probed -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg deleted file mode 100644 index d26a8b1..0000000 --- a/tcl/target/str710.cfg +++ /dev/null @@ -1,53 +0,0 @@ -#start slow, speed up after reset -adapter_khz 10 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME str710 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x3f0f0f0f -} - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst srst_pulls_trst - -#jtag scan chain - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -event reset-start { adapter_khz 10 } -$_TARGETNAME configure -event reset-init { - adapter_khz 6000 - -# Because the hardware cannot be interrogated for the protection state -# of sectors, initialize all the sectors to be unprotected. The initial -# state is reflected by the driver, too. - flash protect 0 0 last off - flash protect 1 0 last off -} -$_TARGETNAME configure -event gdb-flash-erase-start { - flash protect 0 0 7 off - flash protect 1 0 1 off -} - -$_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0 - -#flash bank str7x <base> <size> 0 0 <target#> <variant> -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 $_TARGETNAME STR71x diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg deleted file mode 100644 index 48d3134..0000000 --- a/tcl/target/str730.cfg +++ /dev/null @@ -1,54 +0,0 @@ -#STR730 CPU - -adapter_khz 3000 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME str730 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x3f0f0f0f -} - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst srst_pulls_trst - -#jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID - -#jtag nTRST and nSRST delay -adapter_nsrst_delay 500 -jtag_ntrst_delay 500 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 - -$_TARGETNAME configure -event reset-start { adapter_khz 10 } -$_TARGETNAME configure -event reset-init { - adapter_khz 3000 - -# Because the hardware cannot be interrogated for the protection state -# of sectors, initialize all the sectors to be unprotected. The initial -# state is reflected by the driver, too. - flash protect 0 0 last off -} -$_TARGETNAME configure -event gdb-flash-erase-start { - flash protect 0 0 7 off -} - -$_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-area-backup 0 - -#flash bank <driver> <base> <size> <chip_width> <bus_width> -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x - diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg deleted file mode 100644 index ef6e795..0000000 --- a/tcl/target/str750.cfg +++ /dev/null @@ -1,72 +0,0 @@ -#STR750 CPU - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME str750 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4f1f0041 -} - -# jtag speed -adapter_khz 10 - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst srst_pulls_trst - -#jtag scan chain - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID - -#jtag nTRST and nSRST delay -adapter_nsrst_delay 500 -jtag_ntrst_delay 500 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 - -$_TARGETNAME configure -event reset-start { adapter_khz 10 } -$_TARGETNAME configure -event reset-init { - adapter_khz 3000 - - init_smi -# Because the hardware cannot be interrogated for the protection state -# of sectors, initialize all the sectors to be unprotected. The initial -# state is reflected by the driver, too. - flash protect 0 0 last off - flash protect 1 0 last off -} -$_TARGETNAME configure -event gdb-flash-erase-start { - flash protect 0 0 7 off - flash protect 1 0 1 off -} - -$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 - -#flash bank <driver> <base> <size> <chip_width> <bus_width> -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x - -# Serial NOR on SMI CS0. -set _FLASHNAME $_CHIPNAME.snor -flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME - -source [find mem_helper.tcl] - -proc init_smi {} { - mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs - mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit - mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1 -} diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg deleted file mode 100644 index 36c0b2a..0000000 --- a/tcl/target/str912.cfg +++ /dev/null @@ -1,71 +0,0 @@ -# script for str9 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME str912 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# jtag speed. We need to stick to 16kHz until we've finished reset. -adapter_khz 16 - -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst - -if { [info exists FLASHTAPID] } { - set _FLASHTAPID $FLASHTAPID -} else { - set _FLASHTAPID 0x04570041 -} -jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x25966041 -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - - -if { [info exists BSTAPID] } { - set _BSTAPID $BSTAPID -} else { - # possible values: 0x1457f041, 0x2457f041 - # we ignore version in check below - set _BSTAPID 0x1457f041 -} -jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID -ignore-version - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -event reset-start { adapter_khz 16 } - -$_TARGETNAME configure -event reset-init { - # We can increase speed now that we know the target is halted. - #adapter_khz 3000 - - # -- Enable 96K RAM - # PFQBC enabled / DTCM & AHB wait-states disabled - mww 0x5C002034 0x0191 - - str9x flash_config 0 4 2 0 0x80000 - flash protect 0 0 7 off -} - -$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0 - -#flash bank str9x <base> <size> 0 0 <target#> <variant> -set _FLASHNAME $_CHIPNAME.flash0 -flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME -set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME diff --git a/tcl/target/swj-dp.tcl b/tcl/target/swj-dp.tcl deleted file mode 100644 index 1d274cb..0000000 --- a/tcl/target/swj-dp.tcl +++ /dev/null @@ -1,34 +0,0 @@ -# ARM Debug Interface V5 (ADI_V5) utility -# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since -# SW-DP and JTAG-DP targets don't need to switch based -# on which transport is active. -# -# declare a JTAG or SWD Debug Access Point (DAP) -# based on the transport in use with this session. -# You can't access JTAG ops when SWD is active, etc. - -# params are currently what "jtag newtap" uses -# because OpenOCD internals are still strongly biased -# to JTAG .... but for SWD, "irlen" etc are ignored, -# and the internals work differently - -# for now, ignore non-JTAG and non-SWD transports -# (e.g. initial flash programming via SPI or UART) - -# split out "chip" and "tag" so we can someday handle -# them more uniformly irlen too...) - -if [catch {transport select}] { - echo "Error: unable to select a session transport. Can't continue." - shutdown -} - -proc swj_newdap {chip tag args} { - if [using_hla] { - eval hla newtap $chip $tag $args - } elseif [using_jtag] { - eval jtag newtap $chip $tag $args - } elseif [using_swd] { - eval swd newdap $chip $tag $args - } -} diff --git a/tcl/target/test_reset_syntax_error.cfg b/tcl/target/test_reset_syntax_error.cfg deleted file mode 100644 index cb4e46f..0000000 --- a/tcl/target/test_reset_syntax_error.cfg +++ /dev/null @@ -1,17 +0,0 @@ -# Test script to check that syntax error in reset -# script is reported properly. - -# at91eb40a target - -#jtag scan chain -set _CHIPNAME syntaxtest -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf - -#target configuration -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -event reset-init { - - syntax error -} diff --git a/tcl/target/test_syntax_error.cfg b/tcl/target/test_syntax_error.cfg deleted file mode 100644 index d4f92fa..0000000 --- a/tcl/target/test_syntax_error.cfg +++ /dev/null @@ -1,4 +0,0 @@ -# This script tests a syntax error in the startup -# config script - -syntax error here diff --git a/tcl/target/ti-ar7.cfg b/tcl/target/ti-ar7.cfg deleted file mode 100644 index 19d8c6f..0000000 --- a/tcl/target/ti-ar7.cfg +++ /dev/null @@ -1,30 +0,0 @@ -# -# Texas Instruments AR7 SOC - used in many adsl modems. -# http://www.linux-mips.org/wiki/AR7 -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME ti-ar7 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0000100f -} - -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_CHIPNAME.cpu - -# use onboard 4k sram as working area -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000 diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti-cjtag.cfg deleted file mode 100755 index 7114b2a..0000000 --- a/tcl/target/ti-cjtag.cfg +++ /dev/null @@ -1,32 +0,0 @@ -# A start sequence to change from cJTAG to 4-pin JTAG -# This is needed for CC2538 and CC26xx to be able to communicate through JTAG -# Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information. -proc ti_cjtag_to_4pin_jtag {jrc} { - # Bypass - irscan $jrc 0x3f -endstate RUN/IDLE - # Two zero bit scans and a one bit drshift - pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE - pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE - pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRUPDATE RUN/IDLE - pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE - - # A two bit drhift and a 9 bit drshift - pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRUPDATE RUN/IDLE - pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE - pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE - pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE - - # Bypass - irscan $jrc 0x3f -endstate RUN/IDLE - - # Set ICEPick IDCODE in data register - irscan $jrc 0x04 -endstate RUN/IDLE -} diff --git a/tcl/target/ti_calypso.cfg b/tcl/target/ti_calypso.cfg deleted file mode 100644 index 9d3b293..0000000 --- a/tcl/target/ti_calypso.cfg +++ /dev/null @@ -1,57 +0,0 @@ -# -# TI Calypso (lite) G2 C035 Digital Base Band chip -# -# ARM7TDMIE + DSP subchip (S28C128) -# -# 512K SRAM Calypso -# 256K SRAM Calypso lite -# -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME calypso -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x3100e02f -} - -# Work-area is a space in RAM used for flash programming -# By default use 64kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x10000 -} - -adapter_khz 1000 - -reset_config trst_and_srst - -jtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 8 -jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# target - -set _TARGETNAME $_CHIPNAME.arm -target create $_TARGETNAME arm7tdmi -endian little -chain-position $_TARGETNAME - -# workarea - -$_TARGETNAME configure -work-area-phys 0x00800000 -work-area-size $_WORKAREASIZE -work-area-backup 1 - -arm7_9 dcc_downloads enable -arm7_9 fast_memory_access enable - -$_TARGETNAME configure -event examine-start { - irscan calypso.arm 0x0b -endstate DRPAUSE - drscan calypso.arm 2 2 -endstate RUN/IDLE -} diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg deleted file mode 100644 index 4f8f523..0000000 --- a/tcl/target/ti_dm355.cfg +++ /dev/null @@ -1,109 +0,0 @@ -# -# Texas Instruments DaVinci family: TMS320DM355 -# -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dm355 -} - -# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* -# after JTAG reset until ICEpick is used to route them in. -set EMU01 "-disable" - -# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without -# needing any ICEpick interaction. -#set EMU01 "-enable" - -source [find target/icepick.cfg] - -# -# Also note: when running without RTCK before the PLLs are set up, you -# may need to slow the JTAG clock down quite a lot (under 2 MHz). -# - -# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID] } { - set _ETB_TAPID $ETB_TAPID -} else { - set _ETB_TAPID 0x2b900f0f -} -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01 -jtag configure $_CHIPNAME.etb -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 1" - -# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID] } { - set _CPU_TAPID $CPU_TAPID -} else { - set _CPU_TAPID 0x07926001 -} -jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01 -jtag configure $_CHIPNAME.arm -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 0" - -# Primary TAP: ICEpick (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0b73b02f -} -jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID - -jtag configure $_CHIPNAME.jrc -event setup \ - "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" - -################ - -# various symbol definitions, to avoid hard-wiring addresses -# and enable some sharing of DaVinci-family utility code -global dm355 -set dm355 [ dict create ] - -# Physical addresses for controllers and memory -# (Some of these are valid for many DaVinci family chips) -dict set dm355 sram0 0x00010000 -dict set dm355 sram1 0x00014000 -dict set dm355 sysbase 0x01c40000 -dict set dm355 pllc1 0x01c40800 -dict set dm355 pllc2 0x01c40c00 -dict set dm355 psc 0x01c41000 -dict set dm355 gpio 0x01c67000 -dict set dm355 a_emif 0x01e10000 -dict set dm355 a_emif_cs0 0x02000000 -dict set dm355 a_emif_cs1 0x04000000 -dict set dm355 ddr_emif 0x20000000 -dict set dm355 ddr 0x80000000 -dict set dm355 uart0 0x01c20000 -dict set dm355 uart1 0x01c20400 -dict set dm355 uart2 0x01e06000 - -source [find target/davinci.cfg] - -################ -# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) -# and the ETB memory (4K) are other options, while trace is unused. -set _TARGETNAME $_CHIPNAME.arm - -target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME - -# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, -# and that the work area is used only with a kernel mmu context ... -$_TARGETNAME configure \ - -work-area-virt [expr 0xfffe0000 + 0x4000] \ - -work-area-phys [dict get $dm355 sram1] \ - -work-area-size 0x4000 \ - -work-area-backup 0 - -# be absolutely certain the JTAG clock will work with the worst-case -# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns -# on the PLL and starts using it. OK to speed up after clock setup. -adapter_khz 1500 -$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 } - -arm7_9 fast_memory_access enable -arm7_9 dcc_downloads enable - -# trace setup -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg deleted file mode 100644 index 0db83db..0000000 --- a/tcl/target/ti_dm365.cfg +++ /dev/null @@ -1,101 +0,0 @@ -# -# Texas Instruments DaVinci family: TMS320DM365 -# -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dm365 -} - -# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* -# after JTAG reset until ICEpick is used to route them in. -set EMU01 "-disable" - -# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without -# needing any ICEpick interaction. -#set EMU01 "-enable" - -source [find target/icepick.cfg] - -# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID] } { - set _ETB_TAPID $ETB_TAPID -} else { - set _ETB_TAPID 0x2b900f0f -} -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01 -jtag configure $_CHIPNAME.etb -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 1" - -# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID] } { - set _CPU_TAPID $CPU_TAPID -} else { - set _CPU_TAPID 0x0792602f -} -jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01 -jtag configure $_CHIPNAME.arm -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 0" - -# Primary TAP: ICEpick (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0b83e02f -} -jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID - -jtag configure $_CHIPNAME.jrc -event setup \ - "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" - -################ - -# various symbol definitions, to avoid hard-wiring addresses -# and enable some sharing of DaVinci-family utility code -global dm365 -set dm365 [ dict create ] - -# Physical addresses for controllers and memory -# (Some of these are valid for many DaVinci family chips) -dict set dm365 sram0 0x00010000 -dict set dm365 sram1 0x00014000 -dict set dm365 sysbase 0x01c40000 -dict set dm365 pllc1 0x01c40800 -dict set dm365 pllc2 0x01c40c00 -dict set dm365 psc 0x01c41000 -dict set dm365 gpio 0x01c67000 -dict set dm365 a_emif 0x01d10000 -dict set dm365 a_emif_cs0 0x02000000 -dict set dm365 a_emif_cs1 0x04000000 -dict set dm365 ddr_emif 0x20000000 -dict set dm365 ddr 0x80000000 - -source [find target/davinci.cfg] - -################ -# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) -# and the ETB memory (4K) are other options, while trace is unused. -set _TARGETNAME $_CHIPNAME.arm - -target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME - -# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, -# and that the work area is used only with a kernel mmu context ... -$_TARGETNAME configure \ - -work-area-virt [expr 0xfffe0000 + 0x4000] \ - -work-area-phys [dict get $dm365 sram1] \ - -work-area-size 0x4000 \ - -work-area-backup 0 - -# be absolutely certain the JTAG clock will work with the worst-case -# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns -# on the PLL and starts using it. OK to speed up after clock setup. -adapter_khz 1500 -$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 } - -arm7_9 fast_memory_access enable -arm7_9 dcc_downloads enable - -# trace setup -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg deleted file mode 100644 index fa1e6e9..0000000 --- a/tcl/target/ti_dm6446.cfg +++ /dev/null @@ -1,81 +0,0 @@ -# -# Texas Instruments DaVinci family: TMS320DM6446 -# -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dm6446 -} - -# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* -# after JTAG reset until ICEpick is used to route them in. -set EMU01 "-disable" - -# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without -# needing any ICEpick interaction. -#set EMU01 "-enable" - -source [find target/icepick.cfg] - -# Subsidiary TAP: unknown ... must enable via ICEpick -jtag newtap $_CHIPNAME unknown -irlen 8 -disable -jtag configure $_CHIPNAME.unknown -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 3" - -# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick -jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable -jtag configure $_CHIPNAME.dsp -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 2" - -# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID] } { - set _ETB_TAPID $ETB_TAPID -} else { - set _ETB_TAPID 0x2b900f0f -} -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01 -jtag configure $_CHIPNAME.etb -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 1" - -# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID] } { - set _CPU_TAPID $CPU_TAPID -} else { - set _CPU_TAPID 0x07926001 -} -jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01 -jtag configure $_CHIPNAME.arm -event tap-enable \ - "icepick_c_tapenable $_CHIPNAME.jrc 0" - -# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0b70002f -} -jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID - -jtag configure $_CHIPNAME.jrc -event setup \ - "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" - -################ -# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) -# and the ETB memory (4K) are other options, while trace is unused. -# Little-endian; use the OpenOCD default. -set _TARGETNAME $_CHIPNAME.arm - -target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000 - -# be absolutely certain the JTAG clock will work with the worst-case -# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns -# on the PLL and starts using it. OK to speed up after clock setup. -adapter_khz 1500 -$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 } - -arm7_9 fast_memory_access enable -arm7_9 dcc_downloads enable - -# trace setup -etm config $_TARGETNAME 16 normal full etb -etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/tcl/target/ti_msp432p4xx.cfg b/tcl/target/ti_msp432p4xx.cfg deleted file mode 100644 index 8600867..0000000 --- a/tcl/target/ti_msp432p4xx.cfg +++ /dev/null @@ -1,52 +0,0 @@ -# -# Texas Instruments MSP432P4xx - ARM Cortex-M4F @ up to 48 MHz -# -# http://www.ti.com/MSP432 -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME msp432p4xx -} - -if { [info exists CPUTAPID] } { - set _DAP_TAPID $CPUTAPID -} else { - set _DAP_TAPID 0x4ba00477 -} - -if { [info exists DAP_SWD_ID] } { - set _DAP_SWD_ID $DAP_SWD_ID -} else { - set _DAP_SWD_ID 0x2ba01477 -} - -source [find target/swj-dp.tcl] - -if { [using_jtag] } { - set _DAP_ID $_DAP_TAPID -} else { - set _DAP_ID $_DAP_SWD_ID -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - # On MSP432P401x Bank0 (8k) is always powered - set _WORKAREASIZE 0x2000 -} - -$_TARGETNAME configure -work-area-phys 0x20000000 \ - -work-area-size $_WORKAREASIZE -work-area-backup 0 - -if { ![using_hla] } { - cortex_m reset_config sysresetreq -} - -adapter_khz 500 diff --git a/tcl/target/ti_rm4x.cfg b/tcl/target/ti_rm4x.cfg deleted file mode 100644 index 85c3e81..0000000 --- a/tcl/target/ti_rm4x.cfg +++ /dev/null @@ -1 +0,0 @@ -source [find target/ti_tms570.cfg] diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg deleted file mode 100644 index 21da6c0..0000000 --- a/tcl/target/ti_tms570.cfg +++ /dev/null @@ -1,74 +0,0 @@ -adapter_khz 1500 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME tms570 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN big -} - -# TMS570 has an ICEpick-C on which we need the router commands. -source [find target/icepick.cfg] - -# Main DAP -# DAP_TAPID should be set before source-ing this file -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" - -# ICEpick-C (JTAG route controller) -# JRC_TAPID should be set before source-ing this file -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} - -set _JRC_TAPID2 0x0B7B302F -set _JRC_TAPID3 0x0B95502F -set _JRC_TAPID4 0x0B97102F -set _JRC_TAPID5 0x0D8A002F -set _JRC_TAPID6 0x2B8A002F -set _JRC_TAPID7 0x2D8A002F -set _JRC_TAPID8 0x3B8A002F -set _JRC_TAPID9 0x3D8A002F - - -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ - -expected-id $_JRC_TAPID \ - -expected-id $_JRC_TAPID2 \ - -expected-id $_JRC_TAPID3 \ - -expected-id $_JRC_TAPID4 \ - -expected-id $_JRC_TAPID5 \ - -expected-id $_JRC_TAPID6 \ - -expected-id $_JRC_TAPID7 \ - -expected-id $_JRC_TAPID8 \ - -expected-id $_JRC_TAPID9 \ - -ignore-version -jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" -jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" - -# Cortex-R4 target -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \ - -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003 - -# TMS570 uses quirky BE-32 mode -$_TARGETNAME dap ti_be_32_quirks 1 - -$_TARGETNAME configure -event gdb-attach { - cortex_r4 dbginit - halt -} - -$_TARGETNAME configure -event "reset-assert" { - global _CHIPNAME - - # assert warm system reset through ICEPick - icepick_c_wreset $_CHIPNAME.jrc -} diff --git a/tcl/target/ti_tms570ls20xxx.cfg b/tcl/target/ti_tms570ls20xxx.cfg deleted file mode 100644 index ef45b7a..0000000 --- a/tcl/target/ti_tms570ls20xxx.cfg +++ /dev/null @@ -1,6 +0,0 @@ -# TMS570LS20216, TMS570LS20206, TMS570LS10216 -# TMS570LS10206, TMS570LS10116, TMS570LS10106 -set DAP_TAPID 0x0B7B302F -set JRC_TAPID 0x0B7B302F - -source [find target/ti_tms570.cfg] diff --git a/tcl/target/ti_tms570ls3137.cfg b/tcl/target/ti_tms570ls3137.cfg deleted file mode 100644 index f291803..0000000 --- a/tcl/target/ti_tms570ls3137.cfg +++ /dev/null @@ -1,5 +0,0 @@ -# TMS570LS3137 -set DAP_TAPID 0x0B8A002F -set JRC_TAPID 0x0B8A002F - -source [find target/ti_tms570.cfg] diff --git a/tcl/target/tmpa900.cfg b/tcl/target/tmpa900.cfg deleted file mode 100644 index 3ba3591..0000000 --- a/tcl/target/tmpa900.cfg +++ /dev/null @@ -1,46 +0,0 @@ -###################################### -# Target: Toshiba TMPA900 -###################################### - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME tmpa900 -} - -# Toshiba TMPA900 series MCUs are always little endian as per datasheet. -set _ENDIAN little - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926031 -} - -#TMPA900 has following IDs: -# CP15.0 register 0x41069265 -# CP15.1 register 0x1d152152 -# ARM core 0x07926031 - - -# -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst -adapter_nsrst_delay 20 -jtag_ntrst_delay 20 - -###################### -# Target configuration -###################### - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -# Internal RAM-0 (16kB): 0xf8004000 -# Internal RAM-1 (8kB): 0xf8008000 - -# Use internal RAM-0 and RAM-1 as working area (24kB total). -$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0x6000 \ --work-area-backup 0 diff --git a/tcl/target/tmpa910.cfg b/tcl/target/tmpa910.cfg deleted file mode 100644 index 5d41c8c..0000000 --- a/tcl/target/tmpa910.cfg +++ /dev/null @@ -1,47 +0,0 @@ -###################################### -# Target: Toshiba TMPA910 -###################################### - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME tmpa910 -} - -# Toshiba TMPA910 series MCUs are always little endian as per datasheet. -set _ENDIAN little - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926031 -} - -#TMPA910 has following IDs: -# CP15.0 register 0x41069265 -# CP15.1 register 0x1d152152 -# ARM core 0x07926031 - - -# -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst -adapter_nsrst_delay 20 -jtag_ntrst_delay 20 - -###################### -# Target configuration -###################### - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -# Internal RAM-0 (16kB): 0xf8004000 -# Internal RAM-1 (16kB): 0xf8008000 -# Internal RAM-2 (16kB): 0xf800c000 - -# Use internal RAM-0, RAM-1, and RAM-2 as working area (48kB total). -$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0xc000 \ --work-area-backup 0 diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg deleted file mode 100644 index 66fc075..0000000 --- a/tcl/target/u8500.cfg +++ /dev/null @@ -1,332 +0,0 @@ -# Copyright (C) ST-Ericsson SA 2011 -# Author : michel.jaouen@stericsson.com -# U8500 target - -proc mmu_off {} { - set cp [arm mrc 15 0 1 0 0] - set cp [expr ($cp & ~1)] - arm mcr 15 0 1 0 0 $cp -} - -proc mmu_on {} { - set cp [arm mrc 15 0 1 0 0] - set cp [expr ($cp | 1)] - arm mcr 15 0 1 0 0 $cp -} - -proc ocd_gdb_restart {target_id} { - global _TARGETNAME_1 - global _SMP - targets $_TARGETNAME_1 - if { [expr ($_SMP == 1)] } { - cortex_a smp_off - } - rst_run - halt - if { [expr ($_SMP == 1)]} { - cortex_a smp_on - } -} - -proc smp_reg {} { - global _TARGETNAME_1 - global _TARGETNAME_2 - targets $_TARGETNAME_1 - echo "$_TARGETNAME_1" - set pc1 [reg pc] - set stck1 [reg sp_svc] - targets $_TARGETNAME_2 - echo "$_TARGETNAME_1" - set pc2 [reg pc] - set stck2 [reg sp_svc] -} - - -proc u8500_tapenable {chip val} { - echo "JTAG tap enable $chip" -} - - -proc pwrsts { } { - global _CHIPNAME - irscan $_CHIPNAME.jrc 0x3a - drscan $_CHIPNAME.jrc 4 0 - set pwrsts [drscan $_CHIPNAME.jrc 16 0] - echo "pwrsts ="$pwrsts - set a9 [expr (0x$pwrsts & 0xc)] - set ape [expr (0x$pwrsts & 0x3)] - if {[string equal "0" $ape]} { - echo "ape off" - } else { - echo "ape on" - } - echo "$a9" - switch $a9 { - 4 { - echo "A9 in retention" - } - 8 { - echo "A9 100% DVFS" - } - c { - echo "A9 50% DVFS" - } - } -} - -proc poll_pwrsts { } { - global _CHIPNAME - set result 1 - set i 0 - irscan $_CHIPNAME.jrc 0x3a - drscan $_CHIPNAME.jrc 4 0 - set pwrsts [drscan $_CHIPNAME.jrc 16 0] - set pwrsts [expr (0x$pwrsts & 0xc)] - while {[string equal "4" $pwrsts] && $i<20} { - irscan $_CHIPNAME.jrc 0x3a - drscan $_CHIPNAME.jrc 4 0; - set pwrsts [drscan $_CHIPNAME.jrc 16 0] - set pwrsts [expr (0x$pwrsts & 0xc)] - if {![string equal "4" $pwrsts]} { - set result 1 - } else { - set result 0 - sleep 200 - echo "loop $i" - } - incr i - } - return $result -} - -proc halt_ { } { - if {[poll_pwrsts]==1} { - halt - } else { - echo "halt failed : target in retention" - } -} - - -proc u8500_dapenable {chip} { -} - -proc u8500_tapdisable {chip val} { - echo "JTAG tap disable $chip" -} - - -proc enable_apetap {} { - global _CHIPNAME - global _TARGETNAME_2 - global _TARGETNAME_1 - poll off - irscan $_CHIPNAME.jrc 0x3e - drscan $_CHIPNAME.jrc 8 0xcf - jtag tapenable $_CHIPNAME.dap - irscan $_CHIPNAME.jrc 0x6 - drscan $_CHIPNAME.jrc 32 0 - irscan $_CHIPNAME.jrc 0x6 - drscan $_CHIPNAME.jrc 32 0 - set status [$_TARGETNAME_1 curstate] - if {[string equal "unknown" $status]} { - $_TARGETNAME_1 arp_examine - cache_config l2x 0xa0412000 8 - } - - set status [$_TARGETNAME_2 curstate] - if {[string equal "unknown" $status]} { - $_TARGETNAME_2 arp_examine - } - } - -tcl_port 5555 -telnet_port 4444 -gdb_port 3333 - -if { [info exists CHIPNAME] } { -global _CHIPNAME - set _CHIPNAME $CHIPNAME -} else { -global _CHIPNAME - set _CHIPNAME u8500 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - # this defaults to a bigendian - set _ENDIAN little -} - - - -# Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT, -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable -jtag configure $_CHIPNAME.dap -event tap-enable \ - "u8500_dapenable $_CHIPNAME.dap" -jtag configure $_CHIPNAME.dap -event tap-disable \ - "u8500_tapdisable $_CHIPNAME.dap 0xc0" - - -#CLTAPC TAP JRC equivalent -if { [info exists CLTAPC_ID] } { - set _CLTAPC_ID $CLTAPC_ID -} else { - set _CLTAPC_ID 0x22286041 -} -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version - - -if { ![info exists TARGETNAME_1] } { -global _TARGETNAME_1 -set _TARGETNAME_1 $_CHIPNAME.cpu1 -} else { -global _TARGETNAME_1 -set _TARGETNAME_1 $TARGETNAME_1 -} - -if { [info exists DAP_DBG1] } { - set _DAP_DBG1 $DAP_DBG1 -} else { - set _DAP_DBG1 0x801A8000 -} -if { [info exists DAP_DBG2] } { - set _DAP_DBG2 $DAP_DBG2 -} else { - set _DAP_DBG2 0x801AA000 -} - -target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux - -$_TARGETNAME_1 configure -event gdb-attach { - halt -} - - -if { ![info exists TARGETNAME_2] } { -global _TARGETNAME_2 -set _TARGETNAME_2 $_CHIPNAME.cpu2 -} else { -global _TARGETNAME_2 -set _TARGETNAME_2 $TARGETNAME_2 -} - -target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux - -$_TARGETNAME_2 configure -event gdb-attach { - halt -} - - -if {![info exists SMP]} { -global _SMP -set _SMP 1 -} else { -global _SMP -set _SMP $SMP -} -global SMP -if { $_SMP == 1} { -target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1 -} - - - - -proc secsts1 { } { - global _CHIPNAME - irscan $_CHIPNAME.jrc 0x3a - drscan $_CHIPNAME.jrc 4 4 - set secsts1 [drscan $_CHIPNAME.jrc 16 0] - echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] - if {![string equal "4" $secsts1]} { - echo "APE target secured" - } else { - echo "APE target not secured" - } -} - -proc att { } { - global _CHIPNAME - jtag arp_init - irscan $_CHIPNAME.jrc 0x3a - drscan $_CHIPNAME.jrc 4 4 - set secsts1 [drscan $_CHIPNAME.jrc 16 0] - echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] - if {[string equal "4" $secsts1]} { - if {[poll_pwrsts]==1} { - enable_apetap - } else { - echo "target in retention" - } - } else { - echo "target secured" - } - -} - - - -proc rst_run { } { - global _CHIPNAME - global _TARGETNAME_2 - global _TARGETNAME_1 - set status [$_TARGETNAME_1 curstate] - if {[string equal "halted" $status]} { - resume - targets $_TARGETNAME_1 - } - set status [$_TARGETNAME_2 curstate] - if {[string equal "halted" $status]} { - resume - targets $_TARGETNAME_2 - } - poll off - jtag arp_init - reset - sleep 20 - irscan $_CHIPNAME.jrc 0x3a - drscan $_CHIPNAME.jrc 4 4 - set secsts1 [drscan $_CHIPNAME.jrc 16 0] - echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] - while {![string equal "4" $secsts1]} { - irscan u8500.jrc 0x3a - drscan u8500.jrc 4 4 - set secsts1 [drscan $_CHIPNAME.jrc 16 0] - echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] - } - echo "ape debugable" - enable_apetap - poll on - targets $_TARGETNAME_1 - dap apsel 1 -} - -if {![info exists MAXSPEED]} { -global _MAXSPEED -set _MAXSPEED 15000 -} else { -global _MAXSPEED -set _MAXSPEED $MAXSPEED -} -global _MAXSPEED -adapter_khz $_MAXSPEED - - -gdb_breakpoint_override hard -set mem inaccessible-by-default-off - -jtag_ntrst_delay 100 -reset_config trst_and_srst combined - - diff --git a/tcl/target/vybrid_vf6xx.cfg b/tcl/target/vybrid_vf6xx.cfg deleted file mode 100644 index 6ec4b35..0000000 --- a/tcl/target/vybrid_vf6xx.cfg +++ /dev/null @@ -1,36 +0,0 @@ -# -# Freescale Vybrid VF610 -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME vf610 -} - -if { [info exists A5_JTAG_TAPID] } { - set _A5_JTAG_TAPID $A5_JTAG_TAPID -} else { - set _A5_JTAG_TAPID 0x4BA00477 -} - -if { [info exists A5_SWD_TAPID] } { - set _A5_SWD_TAPID $A5_SWD_TAPID -} else { - set _A5_SWD_TAPID 0x3BA02477 -} - -if { [using_jtag] } { - set _A5_TAPID $_A5_JTAG_TAPID -} else { - set _A5_TAPID $_A5_SWD_TAPID -} - -source [find target/swj-dp.tcl] - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.cpu -dbgbase 0xc0088000 - -adapter_khz 1000 diff --git a/tcl/target/xmc1xxx.cfg b/tcl/target/xmc1xxx.cfg deleted file mode 100644 index d3123c4..0000000 --- a/tcl/target/xmc1xxx.cfg +++ /dev/null @@ -1,40 +0,0 @@ -# -# Infineon XMC1100/XMC1200/XMC1300 family (ARM Cortex-M0 @ 32 MHz) -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME xmc1000 -} - -# -# Only SWD and SPD supported -# -source [find target/swj-dp.tcl] - -if { [info exists CPUTAPID] } { - set _CPU_SWD_TAPID $CPUTAPID -} else { - set _CPU_SWD_TAPID 0x0BB11477 -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -$_TARGETNAME configure -work-area-phys 0x20000000 \ - -work-area-size $_WORKAREASIZE \ - -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME - -adapter_khz 1000 diff --git a/tcl/target/xmc4xxx.cfg b/tcl/target/xmc4xxx.cfg deleted file mode 100644 index bc00777..0000000 --- a/tcl/target/xmc4xxx.cfg +++ /dev/null @@ -1,59 +0,0 @@ -# -# Infineon XMC4100/XMC4200/XMC4400/XMC4500 family (ARM Cortex-M4 @ 80-120 MHz) -# - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME xmc4000 -} - -source [find target/swj-dp.tcl] - -# -# SWJ-DP -# -if { [info exists CPU_JTAG_TAPID] } { - set _CPU_JTAG_TAPID $CPU_JTAG_TAPID -} else { - set _CPU_JTAG_TAPID 0x4BA00477 -} - -# -# SW_DP -# -if { [info exists CPU_SWD_TAPID] } { - set _CPU_SWD_TAPID $CPU_SWD_TAPID -} else { - set _CPU_SWD_TAPID 0x2BA01477 -} - -if { [using_jtag] } { - set _CPU_TAPID $_CPU_JTAG_TAPID -} else { - set _CPU_TAPID $_CPU_SWD_TAPID -} - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -# Work-area is a space in RAM used for flash programming -# By default use 16 kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x1000 -} - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME xmc4xxx 0x0C000000 0 0 0 $_TARGETNAME - -if { ![using_hla] } { - cortex_m reset_config sysresetreq -} - -adapter_khz 1000 diff --git a/tcl/target/xmos_xs1-xau8a-10_arm.cfg b/tcl/target/xmos_xs1-xau8a-10_arm.cfg deleted file mode 100644 index 3fc197a..0000000 --- a/tcl/target/xmos_xs1-xau8a-10_arm.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# -# XMOS xCORE-XA XS1-XAU8A-10: ARM Cortex-M3 @ 48 MHz -# -# http://www.xmos.com/products/silicon/xcore-xa/xa-series -# - -if { ![info exists CHIPNAME] } { - set CHIPNAME xcorexa -} - -if { ![info exists WORKAREASIZE] } { - # XS1-XAU8A-10-FB265: 128 KB SRAM - set WORKAREASIZE 0x20000 -} - -source [find target/efm32.cfg] diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg deleted file mode 100644 index b11de32..0000000 --- a/tcl/target/zynq_7000.cfg +++ /dev/null @@ -1,26 +0,0 @@ -# -# Xilinx Zynq-7000 All Programmable SoC -# -# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm -# - -set _CHIPNAME zynq -set _TARGETNAME $_CHIPNAME.cpu - -jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \ - -expected-id 0x23727093 \ - -expected-id 0x13722093 \ - -expected-id 0x03727093 - -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477 - -target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \ - -coreid 0 -dbgbase 0x80090000 -target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \ - -coreid 1 -dbgbase 0x80092000 -target smp ${_TARGETNAME}0 ${_TARGETNAME}1 - -adapter_khz 1000 - -${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit" -${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit" diff --git a/tcl/target/к1879xб1я.cfg b/tcl/target/к1879xб1я.cfg deleted file mode 100644 index 7d8c113..0000000 --- a/tcl/target/к1879xб1я.cfg +++ /dev/null @@ -1,35 +0,0 @@ -# СБИС К1879ХБ1Я -# http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/ - -adapter_khz 1000 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME к1879хб1я -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists DSP_TAPID] } { - set _DSP_TAPID $DSP_TAPID -} else { - set _DSP_TAPID 0x2b900f0f -} - -jtag newtap $_CHIPNAME dsp -irlen 4 -expected-id $_DSP_TAPID - -if { [info exists CPU_TAPID] } { - set _CPU_TAPID $CPU_TAPID -} else { - set _CPU_TAPID 0x07b76f0f -} - -jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID - -set _TARGETNAME $_CHIPNAME.arm -target create $_TARGETNAME arm11 -chain-position $_CHIPNAME.arm |