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-rw-r--r--tcl/fpga/altera-arriaii.cfg27
-rw-r--r--tcl/fpga/altera-cyclone10.cfg44
-rw-r--r--tcl/fpga/altera-cycloneiii.cfg43
-rw-r--r--tcl/fpga/altera-cycloneiv.cfg53
-rw-r--r--tcl/fpga/altera-cyclonev.cfg58
-rw-r--r--tcl/fpga/altera_common_init.cfg9
-rw-r--r--tcl/fpga/xilinx-dna.cfg6
-rw-r--r--tcl/fpga/xilinx-xc3s.cfg43
8 files changed, 175 insertions, 108 deletions
diff --git a/tcl/fpga/altera-arriaii.cfg b/tcl/fpga/altera-arriaii.cfg
index d59c182..9cf680d 100644
--- a/tcl/fpga/altera-arriaii.cfg
+++ b/tcl/fpga/altera-arriaii.cfg
@@ -21,11 +21,26 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME arriaii
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x025120dd -expected-id 0x025040dd \
- -expected-id 0x025020dd -expected-id 0x024810dd \
- -expected-id 0x025130dd -expected-id 0x0240a0dd \
- -expected-id 0x025030dd -expected-id 0x024820dd \
- -expected-id 0x025140dd
+array set _ARRIA_2_DATA {
+ 0x025120dd {1227 1174 EP2AGX45}
+ 0x025020dd {1227 -1 EP2AGX65}
+ 0x025130dd {1467 -1 EP2AGX95}
+ 0x025030dd {1467 -1 EP2AGX125}
+ 0x025140dd {1971 -1 EP2AGX190}
+ 0x025040dd {1971 -1 EP2AGX260}
+ 0x024810dd {2274 -1 EP2AGZ225}
+ 0x0240a0dd {2682 -1 EP2AGZ300}
+ 0x024820dd {2682 -1 EP2AGZ350}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _ARRIA_2_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_ARRIA_2_DATA}"
+
diff --git a/tcl/fpga/altera-cyclone10.cfg b/tcl/fpga/altera-cyclone10.cfg
index 3a1bc1f..0898c74 100644
--- a/tcl/fpga/altera-cyclone10.cfg
+++ b/tcl/fpga/altera-cyclone10.cfg
@@ -4,31 +4,33 @@
# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html
# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
-# GX085: 0x02e120dd
-# GX105: 0x02e320dd
-# GX150: 0x02e720dd
-# GX220: 0x02ef20dd
-# 10cl006: 0x020f10dd
-# 10cl010: 0x020f10dd
-# 10cl016: 0x020f20dd
-# 10cl025: 0x020f30dd
-# 10cl040: 0x020f40dd
-# 10cl055: 0x020f50dd
-# 10cl080: 0x020f60dd
-# 10cl120: 0x020f70dd
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cyclone10
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x02e720dd -expected-id 0x02e120dd \
- -expected-id 0x02ef20dd -expected-id 0x02e320dd \
- -expected-id 0x020f10dd -expected-id 0x020f20dd \
- -expected-id 0x020f30dd -expected-id 0x020f40dd \
- -expected-id 0x020f50dd -expected-id 0x020f60dd \
- -expected-id 0x020f70dd
+array set _CYCLONE_10_DATA {
+ 0x020f10dd { 603 226 10cl006_10cl010}
+ 0x020f20dd {1080 409 10cl016}
+ 0x020f30dd { 732 286 10cl025}
+ 0x020f40dd {1632 604 10cl040}
+ 0x020f50dd {1164 442 10cl055}
+ 0x020f60dd {1314 502 10cl080}
+ 0x020f70dd {1620 613 10cl120}
+ 0x02e120dd {1339 -1 GX085}
+ 0x02e320dd {1339 -1 GX105}
+ 0x02e720dd {1339 -1 GX150}
+ 0x02ef20dd {1339 -1 GX220}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_10_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
-pld device intel $_CHIPNAME.tap cyclone10
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclone10
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_10_DATA}"
diff --git a/tcl/fpga/altera-cycloneiii.cfg b/tcl/fpga/altera-cycloneiii.cfg
index d9be645..b0da418 100644
--- a/tcl/fpga/altera-cycloneiii.cfg
+++ b/tcl/fpga/altera-cycloneiii.cfg
@@ -4,32 +4,33 @@
# see Cyclone III Device Handbook
# Table 12-2: Device IDCODE for Cyclone III Device Family
-#EP3C5 0x020f10dd
-#EP3C10 0x020f10dd
-#EP3C16 0x020f20dd
-#EP3C25 0x020f30dd
-#EP3C40 0x020f40dd
-#EP3C55 0x020f50dd
-#EP3C80 0x020f60dd
-#EP3C120 0x020f70dd
-#Cyclone III LS
-#EP3CLS70 0x027010dd
-#EP3CLS100 0x027000dd
-#EP3CLS150 0x027030dd
-#EP3CLS200 0x027020dd
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cycloneiii
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x020f10dd -expected-id 0x020f20dd \
- -expected-id 0x020f30dd -expected-id 0x020f40dd \
- -expected-id 0x020f50dd -expected-id 0x020f60dd \
- -expected-id 0x020f70dd -expected-id 0x027010dd \
- -expected-id 0x027000dd -expected-id 0x027030dd \
- -expected-id 0x027020dd
+array set _CYCLONE_3_DATA {
+ 0x020f10dd { 603 226 EP3C5_EP3C10}
+ 0x020f20dd {1080 409 EP3C16}
+ 0x020f30dd { 732 286 EP3C25}
+ 0x020f40dd {1632 604 EP3C40}
+ 0x020f50dd {1164 442 EP3C55}
+ 0x020f60dd {1314 502 EP3C80}
+ 0x020f70dd {1620 613 EP3C120}
+ 0x027010dd {1314 226 EP3CLS70}
+ 0x027000dd {1314 226 EP3CLS100}
+ 0x027030dd {1314 409 EP3CLS150}
+ 0x027020dd {1314 409 EP3CLS200}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_3_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_3_DATA}"
diff --git a/tcl/fpga/altera-cycloneiv.cfg b/tcl/fpga/altera-cycloneiv.cfg
index 6a908e8..44eb89d 100644
--- a/tcl/fpga/altera-cycloneiv.cfg
+++ b/tcl/fpga/altera-cycloneiv.cfg
@@ -4,38 +4,37 @@
# see Cyclone IV Device Handbook
# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices
-#EP4CE6 0x020f10dd
-#EP4CE10 0x020f10dd
-#EP4CE15 0x020f20dd
-#EP4CE22 0x020f30dd
-#EP4CE30 0x020f40dd
-#EP4CE40 0x020f40dd
-#EP4CE55 0x020f50dd
-#EP4CE75 0x020f60dd
-#EP4CE115 0x020f70dd
-#EP4CGX15 0x028010dd
-#EP4CGX22 0x028120dd
-#EP4CGX30 (3) 0x028020dd
-#EP4CGX30 (4) 0x028230dd
-#EP4CGX50 0x028130dd
-#EP4CGX75 0x028030dd
-#EP4CGX110 0x028140dd
-#EP4CGX150 0x028040dd
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cycloneiv
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x020f10dd -expected-id 0x020f20dd \
- -expected-id 0x020f30dd -expected-id 0x020f40dd \
- -expected-id 0x020f50dd -expected-id 0x020f60dd \
- -expected-id 0x020f70dd -expected-id 0x028010dd \
- -expected-id 0x028120dd -expected-id 0x028020dd \
- -expected-id 0x028230dd -expected-id 0x028130dd \
- -expected-id 0x028030dd -expected-id 0x028140dd \
- -expected-id 0x028040dd
+array set _CYCLON_4_DATA {
+ 0x020f10dd { 603 226 EP4CE6_EP4CE10}
+ 0x020f20dd {1080 409 EP4CE15}
+ 0x020f30dd { 732 286 EP4CE22}
+ 0x020f40dd {1632 604 EP4CE30_EP4CE40}
+ 0x020f50dd {1164 442 EP4CE55}
+ 0x020f60dd {1314 502 EP4CE75}
+ 0x020f70dd {1620 613 EP4CE115}
+ 0x028010dd { 260 229 EP4CGX15}
+ 0x028120dd { 494 463 EP4CGX22}
+ 0x028020dd { 494 463 EP4CGX30}
+ 0x028230dd {1006 943 EP4CGX30}
+ 0x028130dd {1006 943 EP4CGX50}
+ 0x028030dd {1006 943 EP4CGX75}
+ 0x028140dd {1495 1438 EP4CGX110}
+ 0x028040dd {1495 1438 EP4CGX150}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLON_4_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_4_DATA}"
diff --git a/tcl/fpga/altera-cyclonev.cfg b/tcl/fpga/altera-cyclonev.cfg
index 46532a5..8d19cd8 100644
--- a/tcl/fpga/altera-cyclonev.cfg
+++ b/tcl/fpga/altera-cyclonev.cfg
@@ -4,44 +4,36 @@
# see Cyclone V Device Handbook
# Table 9-1: IDCODE Information for Cyclone V Devices
-#5CEA2 0x02b150dd
-#5CEA4 0x02b050dd
-#5CEA5 0x02b220dd
-#5CEA7 0x02b130dd
-#5CEA9 0x02b140dd
-#5CGXC3 0x02b010dd
-#5CGXC4 0x02b120dd
-#5CGXC5 0x02b020dd
-#5CGXC7 0x02b030dd
-#5CGXC9 0x02b040dd
-#5CGTD5 0x02b020dd
-#5CGTD7 0x02b030dd
-#5CGTD9 0x02b040dd
-#5CSEA2 0x02d110dd
-#5CSEA4 0x02d010dd
-#5CSEA5 0x02d120dd
-#5CSEA6 0x02d020dd
-#5CSXC2 0x02d110dd
-#5CSXC4 0x02d010dd
-#5CSXC5 0x02d120dd
-#5CSXC6 0x02d020dd
-#5CSTD5 0x02d120dd
-#5CSTD6 0x02d020dd
-
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cyclonev
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x02b150dd -expected-id 0x02b050dd \
- -expected-id 0x02b220dd -expected-id 0x02b130dd \
- -expected-id 0x02b140dd -expected-id 0x02b010dd \
- -expected-id 0x02b120dd -expected-id 0x02b020dd \
- -expected-id 0x02b030dd -expected-id 0x02b040dd \
- -expected-id 0x02d110dd -expected-id 0x02d010dd \
- -expected-id 0x02d120dd -expected-id 0x02d020dd
+array set _CYCLONE_5_DATA {
+ 0x02b150dd { 864 163 5CEA2}
+ 0x02d020dd {1485 19 5CSEA6_5CSXC6_5CSTD6}
+ 0x02b040dd {1728 -1 5CGXC9_5CGTD9}
+ 0x02b050dd { 864 163 5CEA4}
+ 0x02b030dd {1488 19 5CGXC7_5CGTD7}
+ 0x02d120dd {1485 -1 5CSEA5_5CSXC5_5CSTD5}
+ 0x02b220dd {1104 19 5CEA5}
+ 0x02b020dd {1104 19 5CGXC5_5CGTD5}
+ 0x02d010dd {1197 -1 5CSEA4_5CSXC4}
+ 0x02b120dd {1104 19 5CGXC4}
+ 0x02b140dd {1728 -1 5CEA9}
+ 0x02b010dd { 720 19 5CGXC3}
+ 0x02b130dd {1488 19 5CEA7}
+ 0x02d110dd {1197 -1 5CSEA2_5CSXC2}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_5_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_5_DATA}"
diff --git a/tcl/fpga/altera_common_init.cfg b/tcl/fpga/altera_common_init.cfg
new file mode 100644
index 0000000..683a844
--- /dev/null
+++ b/tcl/fpga/altera_common_init.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc set_bscan_checkpos_on_setup {chipname data} {
+ set tapid_w_version [jtag cget $chipname.tap -idcode]
+ set version_mask 0x0fffffff
+ set tapid [format 0x%08x [expr {$tapid_w_version & $version_mask}]]
+ intel set_bscan $chipname.pld [lindex $data($tapid) 0]
+ intel set_check_pos $chipname.pld [lindex $data($tapid) 1]
+}
diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg
index 56f8c14..6b16b78 100644
--- a/tcl/fpga/xilinx-dna.cfg
+++ b/tcl/fpga/xilinx-dna.cfg
@@ -1,7 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+# Spartan3: Table 9-5 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
proc xilinx_dna_addr {chip} {
array set addrs {
+ Spartan3 0x31
Spartan6 0x30
Series7 0x17
}
@@ -43,3 +45,7 @@ proc xc7_get_dna {tap} {
proc xc6s_get_dna {tap} {
return [xilinx_get_dna $tap Spartan6]
}
+
+proc xc3s_get_dna {tap} {
+ return [xilinx_get_dna $tap Spartan3]
+}
diff --git a/tcl/fpga/xilinx-xc3s.cfg b/tcl/fpga/xilinx-xc3s.cfg
new file mode 100644
index 0000000..7c17206
--- /dev/null
+++ b/tcl/fpga/xilinx-xc3s.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx Spartan3 generation
+# https://www.xilinx.com/support/documentation/user_guides/ug331.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME xc3s
+}
+
+# Table 12-4 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
+# the 4 top bits (28:31) are the die stepping, ignore them.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+ -expected-id 0x02210093 \
+ -expected-id 0x02218093 \
+ -expected-id 0x02220093 \
+ -expected-id 0x02228093 \
+ -expected-id 0x02230093 \
+ -expected-id 0x02610093 \
+ -expected-id 0x02618093 \
+ -expected-id 0x02620093 \
+ -expected-id 0x02628093 \
+ -expected-id 0x02630093 \
+ -expected-id 0x03840093 \
+ -expected-id 0x0384E093 \
+ -expected-id 0x01C10093 \
+ -expected-id 0x01C1A093 \
+ -expected-id 0x01C22093 \
+ -expected-id 0x01C2E093 \
+ -expected-id 0x01C3A093 \
+ -expected-id 0x0140C093 \
+ -expected-id 0x01414093 \
+ -expected-id 0x0141C093 \
+ -expected-id 0x01428093 \
+ -expected-id 0x01434093 \
+ -expected-id 0x01440093 \
+ -expected-id 0x01448093 \
+ -expected-id 0x01450093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+
+source [find fpga/xilinx-dna.cfg]
generated by cgit v1.1 at 2024-08-16 19:37:53 +0000