diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/armv7a_cache.c | 21 | ||||
| -rw-r--r-- | src/target/armv7a_cache.h | 2 | ||||
| -rw-r--r-- | src/target/cortex_a.c | 3 |
3 files changed, 0 insertions, 26 deletions
diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c index e1f0dfa..681c06a 100644 --- a/src/target/armv7a_cache.c +++ b/src/target/armv7a_cache.c @@ -391,27 +391,6 @@ int armv7a_cache_flush_virt(struct target *target, uint32_t virt, return ERROR_OK; } -/* - * We assume that target core was chosen correctly. It means if same data - * was handled by two cores, other core will loose the changes. Since it - * is impossible to know (FIXME) which core has correct data, keep in mind - * that some kind of data lost or corruption is possible. - * Possible scenario: - * - core1 loaded and changed data on 0x12345678 - * - we halted target and modified same data on core0 - * - data on core1 will be lost. - */ -int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt, - uint32_t size) -{ - struct armv7a_common *armv7a = target_to_armv7a(target); - - if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) - return ERROR_OK; - - return armv7a_cache_flush_virt(target, virt, size); -} - COMMAND_HANDLER(arm7a_l1_cache_info_cmd) { struct target *target = get_current_target(CMD_CTX); diff --git a/src/target/armv7a_cache.h b/src/target/armv7a_cache.h index 17ec5e6..3e3eae5 100644 --- a/src/target/armv7a_cache.h +++ b/src/target/armv7a_cache.h @@ -20,8 +20,6 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt, int armv7a_l1_i_cache_inval_all(struct target *target); int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size); -int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt, - uint32_t size); int armv7a_cache_auto_flush_all_data(struct target *target); int armv7a_cache_flush_virt(struct target *target, uint32_t virt, uint32_t size); diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 78fd448..f90c02a 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2791,9 +2791,6 @@ static int cortex_a_write_memory(struct target *target, target_addr_t address, LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32, address, size, count); - /* memory writes bypass the caches, must flush before writing */ - armv7a_cache_auto_flush_on_write(target, address, size * count); - cortex_a_prep_memaccess(target, 0); retval = cortex_a_write_cpu_memory(target, address, size, count, buffer); cortex_a_post_memaccess(target, 0); |