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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2011-01-21 14:49:47 +0800 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2011-11-21 22:05:39 +0000 |
| commit | 03fc47a79e90337085517e79dd5540e1fd9eb871 (patch) | |
| tree | 02c007836cb41afe42722503f5613ef630cd0511 /tcl/chip | |
| parent | c44293b0f88f7df100f94759bfc95ffa3915b3d3 (diff) | |
| download | riscv-openocd-03fc47a79e90337085517e79dd5540e1fd9eb871.zip riscv-openocd-03fc47a79e90337085517e79dd5540e1fd9eb871.tar.gz riscv-openocd-03fc47a79e90337085517e79dd5540e1fd9eb871.tar.bz2 | |
TCL/SPEAr: move device generic code
The initialization of RAS enable and clock is required by
all SPEAr3xx devices
Change-Id: Iea4cd0902e4da219475d7f35b4c25fc87ec6b902
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/226
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl/chip')
| -rw-r--r-- | tcl/chip/st/spear/spear310.tcl | 2 | ||||
| -rw-r--r-- | tcl/chip/st/spear/spear3xx.tcl | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/tcl/chip/st/spear/spear310.tcl b/tcl/chip/st/spear/spear310.tcl index 3aaa10d..8956bdb 100644 --- a/tcl/chip/st/spear/spear310.tcl +++ b/tcl/chip/st/spear/spear310.tcl @@ -6,8 +6,6 @@ proc sp310_init {} { - mww 0xfca80034 0x0000ffff ;# enable all RAS clocks - mww 0xfca80040 0x00000000 ;# remove all RAS resets mww 0xb4000008 0x00002ff4 ;# RAS function enable mww 0xfca80050 0x00000001 ;# Enable clk mem port 1 diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl index 4c6f436..f807c25 100644 --- a/tcl/chip/st/spear/spear3xx.tcl +++ b/tcl/chip/st/spear/spear3xx.tcl @@ -57,6 +57,9 @@ proc sp3xx_common_init {} { mww 0xfca8002c 0xfffffff8 ;# enable clock of all peripherals mww 0xfca80038 0x00000000 ;# remove reset of all peripherals + mww 0xfca80034 0x0000ffff ;# enable all RAS clocks + mww 0xfca80040 0x00000000 ;# remove all RAS resets + mww 0xfca800e4 0x78000008 ;# COMP1V8_REG mww 0xfca800ec 0x78000008 ;# COMP3V3_REG |