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authorAntonio Borneo <borneo.antonio@gmail.com>2011-01-21 12:53:19 +0800
committerSpencer Oliver <spen@spen-soft.co.uk>2011-11-21 22:04:46 +0000
commitc44293b0f88f7df100f94759bfc95ffa3915b3d3 (patch)
treec755e06b9b68f3473d31bf6bbc027969c7fa58f9 /tcl/chip
parent218a4b4e20ba8c993ba10c63be5a089c63c49896 (diff)
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TCL/SPEAr: move device specific code
The initialization of memory port 1 is required by SPEAr310 only Change-Id: I9d655da1026795f02ff2f82aed36441068cf266d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/225 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl/chip')
-rw-r--r--tcl/chip/st/spear/spear310.tcl2
-rw-r--r--tcl/chip/st/spear/spear3xx.tcl2
2 files changed, 2 insertions, 2 deletions
diff --git a/tcl/chip/st/spear/spear310.tcl b/tcl/chip/st/spear/spear310.tcl
index 95df51d..3aaa10d 100644
--- a/tcl/chip/st/spear/spear310.tcl
+++ b/tcl/chip/st/spear/spear310.tcl
@@ -10,6 +10,8 @@ proc sp310_init {} {
mww 0xfca80040 0x00000000 ;# remove all RAS resets
mww 0xb4000008 0x00002ff4 ;# RAS function enable
+ mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
+
mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
mww 0xfca80140 0x017bdef6
}
diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl
index 660dab3..4c6f436 100644
--- a/tcl/chip/st/spear/spear3xx.tcl
+++ b/tcl/chip/st/spear/spear3xx.tcl
@@ -60,8 +60,6 @@ proc sp3xx_common_init {} {
mww 0xfca800e4 0x78000008 ;# COMP1V8_REG
mww 0xfca800ec 0x78000008 ;# COMP3V3_REG
- mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
-
mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode
mww 0xfc000000 0x00000f5f