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| author | Tomas Vanek <vanekt@fbl.cz> | 2021-04-22 08:40:02 +0200 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2021-04-30 08:20:54 +0100 |
| commit | ef0aa38c108be536deff73c299ba542e215a892f (patch) | |
| tree | 4cfab312c1f6bdfd95ea17414c024318c2ccbe15 /src | |
| parent | ab337d05f432465fdfedb694ac862fb22f80d7a6 (diff) | |
| download | riscv-openocd-ef0aa38c108be536deff73c299ba542e215a892f.zip riscv-openocd-ef0aa38c108be536deff73c299ba542e215a892f.tar.gz riscv-openocd-ef0aa38c108be536deff73c299ba542e215a892f.tar.bz2 | |
target/armv7m: change FPv4_SP and FPv5_SP/DP identifiers to uppercase
Change-Id: Ia421a973e5fb4767715c9f95c91745f8ca1de1da
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6177
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/rtos/FreeRTOS.c | 2 | ||||
| -rw-r--r-- | src/rtos/nuttx.c | 2 | ||||
| -rw-r--r-- | src/target/armv7m.h | 6 | ||||
| -rw-r--r-- | src/target/cortex_m.c | 6 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c index 4d520b9..f04b0a2 100644 --- a/src/rtos/FreeRTOS.c +++ b/src/rtos/FreeRTOS.c @@ -438,7 +438,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, int cm4_fpu_enabled = 0; struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); if (is_armv7m(armv7m_target)) { - if (armv7m_target->fp_feature == FPv4_SP) { + if (armv7m_target->fp_feature == FPV4_SP) { /* Found ARM v7m target which includes a FPU */ uint32_t cpacr; diff --git a/src/rtos/nuttx.c b/src/rtos/nuttx.c index 6569e38..0705b17 100644 --- a/src/rtos/nuttx.c +++ b/src/rtos/nuttx.c @@ -352,7 +352,7 @@ static int nuttx_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, bool cm4_fpu_enabled = false; struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); if (is_armv7m(armv7m_target)) { - if (armv7m_target->fp_feature == FPv4_SP) { + if (armv7m_target->fp_feature == FPV4_SP) { /* Found ARM v7m target which includes a FPU */ uint32_t cpacr; diff --git a/src/target/armv7m.h b/src/target/armv7m.h index db6f8bc..f5679b9 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -169,9 +169,9 @@ enum { enum { FP_NONE = 0, - FPv4_SP, - FPv5_SP, - FPv5_DP, + FPV4_SP, + FPV5_SP, + FPV5_DP, }; #define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1) diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 6dc33c8..e7a2fad 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -2019,7 +2019,7 @@ int cortex_m_examine(struct target *target) /* test for floating point feature on Cortex-M4 */ if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) { LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i); - armv7m->fp_feature = FPv4_SP; + armv7m->fp_feature = FPV4_SP; } } else if (i == 7 || i == 33 || i == 35 || i == 55) { target_read_u32(target, MVFR0, &mvfr0); @@ -2028,10 +2028,10 @@ int cortex_m_examine(struct target *target) /* test for floating point features on Cortex-M7 */ if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) { LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i); - armv7m->fp_feature = FPv5_SP; + armv7m->fp_feature = FPV5_SP; } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) { LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i); - armv7m->fp_feature = FPv5_DP; + armv7m->fp_feature = FPV5_DP; } } else if (i == 0) { /* Cortex-M0 does not support unaligned memory access */ |