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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2024-04-13 18:54:12 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2024-05-04 08:35:00 +0000 |
| commit | c72afedce794a7251fd9c822e3bfc89f870b9fc1 (patch) | |
| tree | a44d38701230033e9e96d8fe4273cc9a22c2683d /src | |
| parent | 42e31d75b443e369597669b5ff7901de902ad35e (diff) | |
| download | riscv-openocd-c72afedce794a7251fd9c822e3bfc89f870b9fc1.zip riscv-openocd-c72afedce794a7251fd9c822e3bfc89f870b9fc1.tar.gz riscv-openocd-c72afedce794a7251fd9c822e3bfc89f870b9fc1.tar.bz2 | |
target: cortex_a: fix regs invalidation when -defer-examine
The code for cortex_a allocates the register cache during the very
first examine of the target.
To prevent a segmentation fault in assert_reset(), the call to
register_cache_invalidate() is guarded by target_was_examined().
But for targets with -defer-examine, the target is set as not
examined in handle_target_reset() just before entering in
assert_reset().
This causes registers to not be invalidated while reset a target
examined but with -defer-examine.
Change the condition and invalidate the register cache if it has
been already allocated.
Change-Id: I81ae782ddce07431d5f2c1bea3e2f19dfcd6d1ce
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8215
Tested-by: jenkins
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/cortex_a.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 7fa0c4e..78fd448 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1932,7 +1932,7 @@ static int cortex_a_assert_reset(struct target *target) } /* registers are now invalid */ - if (target_was_examined(target)) + if (armv7a->arm.core_cache) register_cache_invalidate(armv7a->arm.core_cache); target->state = TARGET_RESET; |