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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2021-10-20 12:13:01 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-11-13 10:53:26 +0000 |
| commit | 9d574aa3fab6e6d802fab4ededb24b73542ef2b9 (patch) | |
| tree | f9bc2fe3736f9595273419990975a9a8e689c09a /src | |
| parent | 50f977b0581408891ef8dbeeda3fc64e3ef0619a (diff) | |
| download | riscv-openocd-9d574aa3fab6e6d802fab4ededb24b73542ef2b9.zip riscv-openocd-9d574aa3fab6e6d802fab4ededb24b73542ef2b9.tar.gz riscv-openocd-9d574aa3fab6e6d802fab4ededb24b73542ef2b9.tar.bz2 | |
flash/stm32h7x: don't read flash size using the H74/H75x CPU2
CPU2 (Cortex-M4) cannot read flash size register.
assume the maximum flash size without triggering an error message
Change-Id: I5c3328b7cc42e3aa57165075021227d7936f3d26
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6670
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/flash/nor/stm32h7x.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c index e6a4efc..a3e3043 100644 --- a/src/flash/nor/stm32h7x.c +++ b/src/flash/nor/stm32h7x.c @@ -21,7 +21,7 @@ #include "imp.h" #include <helper/binarybuffer.h> #include <target/algorithm.h> -#include <target/armv7m.h> +#include <target/cortex_m.h> /* Erase time can be as high as 1000ms, 10x this and it's toast... */ @@ -759,6 +759,7 @@ static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id) static int stm32x_probe(struct flash_bank *bank) { struct target *target = bank->target; + struct cortex_m_common *cortex_m = target_to_cm(target); struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv; uint16_t flash_size_in_kb; uint32_t device_id; @@ -797,15 +798,19 @@ static int stm32x_probe(struct flash_bank *bank) LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base); /* get flash size from target */ - retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb); + /* STM32H74x/H75x, the second core (Cortex-M4) cannot read the flash size */ + retval = ERROR_FAIL; + if (device_id == DEVID_STM32H74_H75XX && cortex_m->core_info->partno == CORTEX_M4_PARTNO) + LOG_WARNING("%s cannot read the flash size register", target_name(target)); + else + retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb); + if (retval != ERROR_OK) { /* read error when device has invalid value, set max flash size */ flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb; + LOG_INFO("assuming %" PRIu16 "k flash", flash_size_in_kb); } else - LOG_INFO("flash size probed value %" PRIu16, flash_size_in_kb); - - - + LOG_INFO("flash size probed value %" PRIu16 "k", flash_size_in_kb); /* setup bank size */ const uint32_t bank1_base = FLASH_BANK0_ADDRESS; |