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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2020-08-11 15:23:19 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-09-20 14:35:48 +0100 |
| commit | 762ddcb74948852b0dfb25fcbca0965b09249a2f (patch) | |
| tree | 37faaea2ca9dc6c51d94704714d20bf83a2ad861 /src | |
| parent | f2c83fade3ea7e51e5c9283aa3ff94632a41cc55 (diff) | |
| download | riscv-openocd-762ddcb74948852b0dfb25fcbca0965b09249a2f.zip riscv-openocd-762ddcb74948852b0dfb25fcbca0965b09249a2f.tar.gz riscv-openocd-762ddcb74948852b0dfb25fcbca0965b09249a2f.tar.bz2 | |
cortex_m: add detection of Cortex M35P and M55
Change-Id: I52599b2b09c2dc50c95d64059213c832d380ea31
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5799
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/cortex_m.c | 10 | ||||
| -rw-r--r-- | src/target/cortex_m.h | 2 |
2 files changed, 9 insertions, 3 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 4b0ea50..e52332d 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -2176,11 +2176,15 @@ int cortex_m_examine(struct target *target) case CORTEX_M23_PARTNO: i = 23; break; - case CORTEX_M33_PARTNO: i = 33; break; - + case CORTEX_M35P_PARTNO: + i = 35; + break; + case CORTEX_M55_PARTNO: + i = 55; + break; default: armv7m->arm.is_armv8m = false; break; @@ -2213,7 +2217,7 @@ int cortex_m_examine(struct target *target) LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i); armv7m->fp_feature = FPv4_SP; } - } else if (i == 7 || i == 33) { + } else if (i == 7 || i == 33 || i == 35 || i == 55) { target_read_u32(target, MVFR0, &mvfr0); target_read_u32(target, MVFR1, &mvfr1); diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 3545328..415a6c2 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -44,6 +44,8 @@ #define CORTEX_M23_PARTNO 0xD200 #define CORTEX_M33_PARTNO 0xD210 +#define CORTEX_M35P_PARTNO 0xD310 +#define CORTEX_M55_PARTNO 0xD220 /* Debug Control Block */ #define DCB_DHCSR 0xE000EDF0 |