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| author | Ian Thompson <ianst@cadence.com> | 2022-09-15 14:14:15 -0700 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-09-18 08:12:02 +0000 |
| commit | 61d0757acf222fdd5669b471cc251e03101db273 (patch) | |
| tree | f944aec9c424613a83598195f28d857b44e246de /src | |
| parent | 27e7f5df5ff691a78ca7530892ee5dc05820a947 (diff) | |
| download | riscv-openocd-61d0757acf222fdd5669b471cc251e03101db273.zip riscv-openocd-61d0757acf222fdd5669b471cc251e03101db273.tar.gz riscv-openocd-61d0757acf222fdd5669b471cc251e03101db273.tar.bz2 | |
target/xtensa: invalidate register cache on reset
Resolves issues where registers are accessed when poll() logic is inactive or has not yet been triggered.
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: If7a4d00938fb188b008325249627f7773c3484c5
Reviewed-on: https://review.openocd.org/c/openocd/+/7197
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/xtensa/xtensa.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c index 50658e9..d3be8b4 100644 --- a/src/target/xtensa/xtensa.c +++ b/src/target/xtensa/xtensa.c @@ -959,7 +959,6 @@ int xtensa_assert_reset(struct target *target) struct xtensa *xtensa = target_to_xtensa(target); LOG_TARGET_DEBUG(target, "target_number=%i, begin", target->target_number); - target->state = TARGET_RESET; xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, PWRCTL_JTAGDEBUGUSE(xtensa) | PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | @@ -968,8 +967,12 @@ int xtensa_assert_reset(struct target *target) int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) return res; + + /* registers are now invalid */ xtensa->reset_asserted = true; - return res; + register_cache_invalidate(xtensa->core_cache); + target->state = TARGET_RESET; + return ERROR_OK; } int xtensa_deassert_reset(struct target *target) |