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| author | Aurélien Martin <martaurel@gmail.com> | 2019-07-22 23:13:29 +0200 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2020-04-21 16:40:35 +0100 |
| commit | 3c8aa12859e909b4d14162bd7578bf84571bac20 (patch) | |
| tree | 78c37720cf53ccfca60438164304de75c6a69ab3 /src | |
| parent | 65d8fdf0d1e7aa931dd70cb2b0784473fe7834e1 (diff) | |
| download | riscv-openocd-3c8aa12859e909b4d14162bd7578bf84571bac20.zip riscv-openocd-3c8aa12859e909b4d14162bd7578bf84571bac20.tar.gz riscv-openocd-3c8aa12859e909b4d14162bd7578bf84571bac20.tar.bz2 | |
nrf5: Refresh the watchdog while flashing
If watchdog is enabled, there's no way we can disable it while the flashing firmware
is running. (Halt disables it, but software reset doesn't.) So let's have the flashing
firmware refresh the watchdog regularly, in case it has been enabled by previously
running software. Failure to do so could lead to a watchdog reset in the middle of
the chip bieng programmed.
Change-Id: I79d41593948aae0080480e891552e1c2ee3ccbd0
Signed-off-by: Aurélien Martin <martaurel@gmail.com>
Reviewed-on: http://openocd.zylin.com/5266
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/flash/nor/nrf5.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c index c569c18..fa67e2b 100644 --- a/src/flash/nor/nrf5.c +++ b/src/flash/nor/nrf5.c @@ -28,6 +28,10 @@ #include <helper/types.h> #include <helper/time_support.h> +/* Both those values are constant across the current spectrum ofr nRF5 devices */ +#define WATCHDOG_REFRESH_REGISTER 0x40010600 +#define WATCHDOG_REFRESH_VALUE 0x6e524635 + enum { NRF5_FLASH_BASE = 0x00000000, }; @@ -907,7 +911,7 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u uint32_t buffer_size = 8192; struct working_area *write_algorithm; struct working_area *source; - struct reg_param reg_params[4]; + struct reg_param reg_params[6]; struct armv7m_algorithm armv7m_info; int retval = ERROR_OK; @@ -965,15 +969,19 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer start */ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer end */ init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT); /* target address */ + init_reg_param(®_params[4], "r6", 32, PARAM_OUT); /* watchdog refresh value */ + init_reg_param(®_params[5], "r7", 32, PARAM_OUT); /* watchdog refresh register address */ buf_set_u32(reg_params[0].value, 0, 32, bytes); buf_set_u32(reg_params[1].value, 0, 32, source->address); buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size); buf_set_u32(reg_params[3].value, 0, 32, address); + buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE); + buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER); retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4, 0, NULL, - 4, reg_params, + ARRAY_SIZE(reg_params), reg_params, source->address, source->size, write_algorithm->address, 0, &armv7m_info); @@ -985,6 +993,8 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u destroy_reg_param(®_params[1]); destroy_reg_param(®_params[2]); destroy_reg_param(®_params[3]); + destroy_reg_param(®_params[4]); + destroy_reg_param(®_params[5]); return retval; } |