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| author | Tomas Vanek <vanekt@fbl.cz> | 2022-08-02 11:44:43 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-08-15 13:23:57 +0000 |
| commit | 3adbec9aab95808222071eb09014f28fbb6ad1be (patch) | |
| tree | 1995a67427809f1c686a899b8242550b6e02669c /src | |
| parent | 7e8ea96345d58ad4d1f6da1a2c952560fe78fc60 (diff) | |
| download | riscv-openocd-3adbec9aab95808222071eb09014f28fbb6ad1be.zip riscv-openocd-3adbec9aab95808222071eb09014f28fbb6ad1be.tar.gz riscv-openocd-3adbec9aab95808222071eb09014f28fbb6ad1be.tar.bz2 | |
target/cortex_m: supress historical reset detection
The S_RESET_ST sticky bit is reset after DHCSR read.
It is set at power-on reset and keeps active until the debuger reads DHCSR.
Ignore S_RESET_ST at the very first read after OpenOCD start
and suppress possibly misleading message "external reset detected"
if we cannot guarantee the reset happened recently.
While on it add a TODO comment.
Change-Id: I15217c2ca6f69ac97aff8be86bce67cba94a42cd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7109
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/cortex_m.c | 19 | ||||
| -rw-r--r-- | src/target/cortex_m.h | 2 |
2 files changed, 21 insertions, 0 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 9497aa0..aeaeb18 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -652,6 +652,11 @@ static int cortex_m_endreset_event(struct target *target) register_cache_invalidate(armv7m->arm.core_cache); + /* TODO: invalidate also working areas (needed in the case of detected reset). + * Doing so will require flash drivers to test if working area + * is still valid in all target algo calling loops. + */ + /* make sure we have latest dhcsr flags */ retval = cortex_m_read_dhcsr_atomic_sticky(target); if (retval != ERROR_OK) @@ -2396,6 +2401,20 @@ int cortex_m_examine(struct target *target) retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) return retval; + + /* Don't cumulate sticky S_RESET_ST at the very first read of DHCSR + * as S_RESET_ST may indicate a reset that happened long time ago + * (most probably the power-on reset before OpenOCD was started). + * As we are just initializing the debug system we do not need + * to call cortex_m_endreset_event() in the following poll. + */ + if (!cortex_m->dcb_dhcsr_sticky_is_recent) { + cortex_m->dcb_dhcsr_sticky_is_recent = true; + if (cortex_m->dcb_dhcsr & S_RESET_ST) { + LOG_TARGET_DEBUG(target, "reset happened some time ago, ignore"); + cortex_m->dcb_dhcsr &= ~S_RESET_ST; + } + } cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr); if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) { diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 1686135..69368a9 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -206,6 +206,8 @@ struct cortex_m_common { /* Context information */ uint32_t dcb_dhcsr; uint32_t dcb_dhcsr_cumulated_sticky; + /* DCB DHCSR has been at least once read, so the sticky bits have been reset */ + bool dcb_dhcsr_sticky_is_recent; uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */ uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */ |