diff options
| author | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2014-03-02 20:33:54 +0100 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2014-06-28 09:32:41 +0000 |
| commit | 003f8a1d04f4e82c32d11f86ef32173048ab610c (patch) | |
| tree | 1f25dee44edd5694c73e36173a8f717b1df0e607 /src | |
| parent | 5a7eae940b8ed47f79ec433d6fcc3494fa0fae5b (diff) | |
| download | riscv-openocd-003f8a1d04f4e82c32d11f86ef32173048ab610c.zip riscv-openocd-003f8a1d04f4e82c32d11f86ef32173048ab610c.tar.gz riscv-openocd-003f8a1d04f4e82c32d11f86ef32173048ab610c.tar.bz2 | |
adi_v5: Make sure all bit masks are unsigned and wide enough.
Also align them with spaces instead of tabs.
Change-Id: I1c01412a3ea77b29e8e133f5c92d05ed79d7c0f3
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2133
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/arm_adi_v5.h | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 002e60f..047900a 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -66,28 +66,28 @@ #define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */ /* Fields of the DP's AP ABORT register */ -#define DAPABORT (1 << 0) -#define STKCMPCLR (1 << 1) /* SWD-only */ -#define STKERRCLR (1 << 2) /* SWD-only */ -#define WDERRCLR (1 << 3) /* SWD-only */ -#define ORUNERRCLR (1 << 4) /* SWD-only */ +#define DAPABORT (1UL << 0) +#define STKCMPCLR (1UL << 1) /* SWD-only */ +#define STKERRCLR (1UL << 2) /* SWD-only */ +#define WDERRCLR (1UL << 3) /* SWD-only */ +#define ORUNERRCLR (1UL << 4) /* SWD-only */ /* Fields of the DP's CTRL/STAT register */ -#define CORUNDETECT (1 << 0) -#define SSTICKYORUN (1 << 1) +#define CORUNDETECT (1UL << 0) +#define SSTICKYORUN (1UL << 1) /* 3:2 - transaction mode (e.g. pushed compare) */ -#define SSTICKYCMP (1 << 4) -#define SSTICKYERR (1 << 5) -#define READOK (1 << 6) /* SWD-only */ -#define WDATAERR (1 << 7) /* SWD-only */ +#define SSTICKYCMP (1UL << 4) +#define SSTICKYERR (1UL << 5) +#define READOK (1UL << 6) /* SWD-only */ +#define WDATAERR (1UL << 7) /* SWD-only */ /* 11:8 - mask lanes for pushed compare or verify ops */ /* 21:12 - transaction counter */ -#define CDBGRSTREQ (1 << 26) -#define CDBGRSTACK (1 << 27) -#define CDBGPWRUPREQ (1 << 28) -#define CDBGPWRUPACK (1 << 29) -#define CSYSPWRUPREQ (1 << 30) -#define CSYSPWRUPACK (1 << 31) +#define CDBGRSTREQ (1UL << 26) +#define CDBGRSTACK (1UL << 27) +#define CDBGPWRUPREQ (1UL << 28) +#define CDBGPWRUPACK (1UL << 29) +#define CSYSPWRUPREQ (1UL << 30) +#define CSYSPWRUPACK (1UL << 31) /* MEM-AP register addresses */ /* TODO: rename as MEM_AP_REG_* */ @@ -108,18 +108,18 @@ #define CSW_8BIT 0 #define CSW_16BIT 1 #define CSW_32BIT 2 -#define CSW_ADDRINC_MASK (3 << 4) -#define CSW_ADDRINC_OFF 0 -#define CSW_ADDRINC_SINGLE (1 << 4) -#define CSW_ADDRINC_PACKED (2 << 4) -#define CSW_DEVICE_EN (1 << 6) -#define CSW_TRIN_PROG (1 << 7) -#define CSW_SPIDEN (1 << 23) +#define CSW_ADDRINC_MASK (3UL << 4) +#define CSW_ADDRINC_OFF 0UL +#define CSW_ADDRINC_SINGLE (1UL << 4) +#define CSW_ADDRINC_PACKED (2UL << 4) +#define CSW_DEVICE_EN (1UL << 6) +#define CSW_TRIN_PROG (1UL << 7) +#define CSW_SPIDEN (1UL << 23) /* 30:24 - implementation-defined! */ -#define CSW_HPROT (1 << 25) /* ? */ -#define CSW_MASTER_DEBUG (1 << 29) /* ? */ -#define CSW_SPROT (1 << 30) -#define CSW_DBGSWENABLE (1 << 31) +#define CSW_HPROT (1UL << 25) /* ? */ +#define CSW_MASTER_DEBUG (1UL << 29) /* ? */ +#define CSW_SPROT (1UL << 30) +#define CSW_DBGSWENABLE (1UL << 31) /** * This represents an ARM Debug Interface (v5) Debug Access Port (DAP). |