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| author | Walter Ji <walter.ji@oss.cipunited.com> | 2023-11-17 11:27:56 +0800 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2024-03-09 11:08:21 +0000 |
| commit | 561ea48d83ae4b83ff823888a80cbcc282b61333 (patch) | |
| tree | 3a22979e80f9c506eb9c21719f00409dd49fb223 /doc | |
| parent | fcda9f1561bfc413e3723e5b4552bc7e91eb4a8d (diff) | |
| download | riscv-openocd-561ea48d83ae4b83ff823888a80cbcc282b61333.zip riscv-openocd-561ea48d83ae4b83ff823888a80cbcc282b61333.tar.gz riscv-openocd-561ea48d83ae4b83ff823888a80cbcc282b61333.tar.bz2 | |
target/mips32: add dsp access support
Add access to dsp registers and a command for dsp related operations.
Checkpatch-ignore: MACRO_ARG_REUSE
Change-Id: I30aec0b9e4984896965edb1663f74216ad41101e
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7867
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 4297258d..bf4e0ad 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -11070,6 +11070,11 @@ EJTAG Register Specification could be found in MIPS Document MD00047F, for core specific EJTAG Register definition, please check Core Specific SUM manual. @end deffn +@deffn {Command} {mips32 dsp} [[register_name] [value]] +Displays all DSP registers' contents or get/set value by register name. Will display +an error if current CPU does not support DSP. +@end deffn + @section RISC-V Architecture @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG |