From 561ea48d83ae4b83ff823888a80cbcc282b61333 Mon Sep 17 00:00:00 2001 From: Walter Ji Date: Fri, 17 Nov 2023 11:27:56 +0800 Subject: target/mips32: add dsp access support Add access to dsp registers and a command for dsp related operations. Checkpatch-ignore: MACRO_ARG_REUSE Change-Id: I30aec0b9e4984896965edb1663f74216ad41101e Signed-off-by: Walter Ji Reviewed-on: https://review.openocd.org/c/openocd/+/7867 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Antonio Borneo --- doc/openocd.texi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'doc') diff --git a/doc/openocd.texi b/doc/openocd.texi index 4297258d..bf4e0ad 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -11070,6 +11070,11 @@ EJTAG Register Specification could be found in MIPS Document MD00047F, for core specific EJTAG Register definition, please check Core Specific SUM manual. @end deffn +@deffn {Command} {mips32 dsp} [[register_name] [value]] +Displays all DSP registers' contents or get/set value by register name. Will display +an error if current CPU does not support DSP. +@end deffn + @section RISC-V Architecture @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG -- cgit v1.1