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| author | Tim Newsome <tim@sifive.com> | 2019-01-25 14:17:32 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2019-01-25 14:17:32 -0800 |
| commit | 49dd7ded87052fcdd819392b84e59ee6c64e0950 (patch) | |
| tree | 670d4e80eba54921951d6afa780da6331e0ad36e /doc | |
| parent | 82cf37d36c6b91b1fd5f27fe4df7f80928153c8c (diff) | |
| parent | eb7af6cba0b42ea6d0990f4360a32ca90b7902fb (diff) | |
| download | riscv-openocd-49dd7ded87052fcdd819392b84e59ee6c64e0950.zip riscv-openocd-49dd7ded87052fcdd819392b84e59ee6c64e0950.tar.gz riscv-openocd-49dd7ded87052fcdd819392b84e59ee6c64e0950.tar.bz2 | |
Merge branch 'riscv' into hwthread
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index d79664f..168e660 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9145,6 +9145,17 @@ When on, prefer to use System Bus Access to access memory. When off, prefer to use the Program Buffer to access memory. @end deffn +@deffn Command {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value] +Set the IR value for the specified JTAG register. This is useful, for +example, when using the existing JTAG interface on a Xilinx FPGA by +way of BSCANE2 primitives that only permit a limited selection of IR +values. + +When utilizing version 0.11 of the RISC-V Debug Specification, +@option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL +and DBUS registers, respectively. +@end deffn + @subsection RISC-V Authentication Commands The following commands can be used to authenticate to a RISC-V system. Eg. a |