From 00b591a09a6a56adb5e33381a3803a973bd50ef0 Mon Sep 17 00:00:00 2001 From: Darius Rad Date: Tue, 8 Jan 2019 13:30:26 -0500 Subject: Add 'riscv set_ir' command to set IR value for JTAG registers. This allows using different TAP addresses, for example, if using BSCANE2 primitives on a Xilinx FPGA. --- doc/openocd.texi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'doc') diff --git a/doc/openocd.texi b/doc/openocd.texi index 5992320..7914515 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9145,6 +9145,17 @@ When on, prefer to use System Bus Access to access memory. When off, prefer to use the Program Buffer to access memory. @end deffn +@deffn Command {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value] +Set the IR value for the specified JTAG register. This is useful, for +example, when using the existing JTAG interface on a Xilinx FPGA by +way of BSCANE2 primitives that only permit a limited selection of IR +values. + +When utilizing version 0.11 of the RISC-V Debug Specification, +@option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL +and DBUS registers, respectively. +@end deffn + @subsection RISC-V Authentication Commands The following commands can be used to authenticate to a RISC-V system. Eg. a -- cgit v1.1