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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2020-03-25 16:33:30 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2020-11-15 21:55:20 +0000 |
| commit | 3d736e0488bc498358e3d49d7ce728b17955c8fe (patch) | |
| tree | 94881dbfbc971328d7455c65200ec9e1ce9367b0 /doc | |
| parent | dc43ecce5a7ee5722ea851707ad3acd08a42b5aa (diff) | |
| download | riscv-openocd-3d736e0488bc498358e3d49d7ce728b17955c8fe.zip riscv-openocd-3d736e0488bc498358e3d49d7ce728b17955c8fe.tar.gz riscv-openocd-3d736e0488bc498358e3d49d7ce728b17955c8fe.tar.bz2 | |
flash/stm32l4x: STM32L55/L56xx basic support (non-secure mode)
STM32L5 have 512 Kbytes of Flash memory with dual bank architecture.
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
NON-SECURE flash is located at 0x8000000 like L4 devices, so no
big change is needed (secure flash will be subject of another change).
Note: flash driver name is set stm32l5x, in order to extend the commands
with specific L5 commands (to manage TZEN for example ...)
Note: this works only when TZEN=0
Change-Id: Ie758abb4aa19a3f29eeb0702d7dcb43992e4c639
Signed-off-by: Michael Jung <mijung@gmx.net>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5510
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 292bbd7..65b5d65 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -7134,10 +7134,9 @@ The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @deffn {Flash Driver} stm32l4x -All members of the STM32L4, STM32L4+, STM32WB, STM32WL and STM32G4 +All members of the STM32 G0, G4, L4, L4+, L5, WB and WL microcontroller families from STMicroelectronics include internal flash -and use ARM Cortex-M4 cores. -Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core. +and use ARM Cortex-M0+, M4 and M33 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. |