flash/stm32l4x: STM32L55/L56xx basic support (non-secure mode)

STM32L5 have 512 Kbytes of Flash memory with dual bank architecture.
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
NON-SECURE flash is located at 0x8000000 like L4 devices, so no
big change is needed (secure flash will be subject of another change).

Note: flash driver name is set stm32l5x, in order to extend the commands
with specific L5 commands (to manage TZEN for example ...)

Note: this works only when TZEN=0

Change-Id: Ie758abb4aa19a3f29eeb0702d7dcb43992e4c639
Signed-off-by: Michael Jung <mijung@gmx.net>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5510
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

5 files changed, 209 insertions, 15 deletions

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 292bbd7..65b5d65 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7134,10 +7134,9 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 
 @deffn {Flash Driver} stm32l4x
-All members of the STM32L4, STM32L4+, STM32WB, STM32WL and STM32G4
+All members of the STM32 G0, G4, L4, L4+, L5, WB and WL
 microcontroller families from STMicroelectronics include internal flash
-and use ARM Cortex-M4 cores.
-Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core.
+and use ARM Cortex-M0+, M4 and M33 cores.
 The driver automatically recognizes a number of these chips using
 the chip identification register, and autoconfigures itself.
 
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index ca8a3b8..2bf2913 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -106,6 +106,12 @@
  * Cat. 4 devices have single bank only, page size is 2kByte.
  */
 
+/* STM32L5xxx series for reference.
+ *
+ * RM0428 (STM32L552xx/STM32L562xx)
+ * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
+ */
+
 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
 
 #define FLASH_ERASE_TIMEOUT 250
@@ -137,6 +143,19 @@ static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
 	[STM32_FLASH_WRP2BR_INDEX]   = 0x050,
 };
 
+static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
+	[STM32_FLASH_ACR_INDEX]      = 0x000,
+	[STM32_FLASH_KEYR_INDEX]     = 0x008,
+	[STM32_FLASH_OPTKEYR_INDEX]  = 0x010,
+	[STM32_FLASH_SR_INDEX]       = 0x020,
+	[STM32_FLASH_CR_INDEX]       = 0x028,
+	[STM32_FLASH_OPTR_INDEX]     = 0x040,
+	[STM32_FLASH_WRP1AR_INDEX]   = 0x058,
+	[STM32_FLASH_WRP1BR_INDEX]   = 0x05C,
+	[STM32_FLASH_WRP2AR_INDEX]   = 0x068,
+	[STM32_FLASH_WRP2BR_INDEX]   = 0x06C,
+};
+
 struct stm32l4_rev {
 	const uint16_t rev;
 	const char *str;
@@ -167,7 +186,7 @@ struct stm32l4_flash_bank {
 };
 
 /* human readable list of families this drivers supports (sorted alphabetically) */
-static const char *device_families = "STM32G0/G4/L4/L4+/WB/WL";
+static const char *device_families = "STM32G0/G4/L4/L4+/L5/WB/WL";
 
 static const struct stm32l4_rev stm32_415_revs[] = {
 	{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
@@ -213,6 +232,10 @@ static const struct stm32l4_rev stm32_471_revs[] = {
 	{ 0x1001, "Z" },
 };
 
+static const struct stm32l4_rev stm32_472_revs[] = {
+	{ 0x1000, "A" }, { 0x2000, "B" },
+};
+
 static const struct stm32l4_rev stm32_479_revs[] = {
 	{ 0x1000, "A" },
 };
@@ -352,6 +375,17 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .fsize_addr            = 0x1FFF75E0,
 	},
 	{
+	  .id                    = 0x472,
+	  .revs                  = stm32_472_revs,
+	  .num_revs              = ARRAY_SIZE(stm32_472_revs),
+	  .device_str            = "STM32L55/L56xx",
+	  .max_flash_size_kb     = 512,
+	  .has_dual_bank         = true,
+	  .flash_regs_base       = 0x40022000,
+	  .default_flash_regs    = stm32l5_ns_flash_regs,
+	  .fsize_addr            = 0x0BFA05E0,
+	},
+	{
 	  .id                    = 0x479,
 	  .revs                  = stm32_479_revs,
 	  .num_revs              = ARRAY_SIZE(stm32_479_revs),
@@ -477,7 +511,6 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 		alive_sleep(1);
 	}
 
-
 	if (status & FLASH_WRPERR) {
 		LOG_ERROR("stm32x device protected");
 		retval = ERROR_FAIL;
@@ -917,17 +950,17 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
 {
 	int retval;
 
-	/* try stm32l4/l4+/wb/g4 id register first, then stm32g0 id register */
-	retval = target_read_u32(bank->target, DBGMCU_IDCODE_L4_G4, id);
-	if ((retval != ERROR_OK) || ((*id & 0xfff) == 0) || ((*id & 0xfff) == 0xfff)) {
-		retval = target_read_u32(bank->target, DBGMCU_IDCODE_G0, id);
-		if ((retval != ERROR_OK) || ((*id & 0xfff) == 0) || ((*id & 0xfff) == 0xfff)) {
-			LOG_ERROR("can't get device id");
-			return (retval == ERROR_OK) ? ERROR_FAIL : retval;
-		}
+	/* try reading possible IDCODE registers, in the following order */
+	uint32_t DBGMCU_IDCODE[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
+
+	for (unsigned int i = 0; i < ARRAY_SIZE(DBGMCU_IDCODE); i++) {
+		retval = target_read_u32(bank->target, DBGMCU_IDCODE[i], id);
+		if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
+			return ERROR_OK;
 	}
 
-	return retval;
+	LOG_ERROR("can't get the device id");
+	return (retval == ERROR_OK) ? ERROR_FAIL : retval;
 }
 
 static int stm32l4_probe(struct flash_bank *bank)
@@ -1004,6 +1037,7 @@ static int stm32l4_probe(struct flash_bank *bank)
 	int page_size_kb = 0;
 
 	stm32l4_info->dual_bank_mode = false;
+	bool use_dbank_bit = false;
 
 	switch (device_id) {
 	case 0x415: /* STM32L47/L48xx */
@@ -1070,7 +1104,7 @@ static int stm32l4_probe(struct flash_bank *bank)
 		page_size_kb = 8;
 		num_pages = flash_size_kb / page_size_kb;
 		stm32l4_info->bank1_sectors = num_pages;
-		const bool use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
+		use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
 		if ((use_dbank_bit && (options & BIT(22))) ||
 			(!use_dbank_bit && (options & BIT(21)))) {
 			stm32l4_info->dual_bank_mode = true;
@@ -1079,6 +1113,23 @@ static int stm32l4_probe(struct flash_bank *bank)
 			stm32l4_info->bank1_sectors = num_pages / 2;
 		}
 		break;
+	case 0x472: /* STM32L55/L56xx */
+		/* STM32L55/L56xx can be single/dual bank:
+		 *   if size = 512K check DBANK bit(22)
+		 *   if size = 256K check DB256K bit(21)
+		 */
+		page_size_kb = 4;
+		num_pages = flash_size_kb / page_size_kb;
+		stm32l4_info->bank1_sectors = num_pages;
+		use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
+		if ((use_dbank_bit && (options & BIT(22))) ||
+			(!use_dbank_bit && (options & BIT(21)))) {
+			stm32l4_info->dual_bank_mode = true;
+			page_size_kb = 2;
+			num_pages = flash_size_kb / page_size_kb;
+			stm32l4_info->bank1_sectors = num_pages / 2;
+		}
+		break;
 	case 0x495: /* STM32WB5x */
 	case 0x496: /* STM32WB3x */
 		/* single bank flash */
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index aafb939..280a059 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -116,6 +116,7 @@ proc stm32l1x args { eval stm32lx $args }
 # stm32[g0|g4|wb|wl] uses the same flash driver as the stm32l4x
 proc stm32g0x args { eval stm32l4x $args }
 proc stm32g4x args { eval stm32l4x $args }
+proc stm32l5x args { eval stm32l4x $args }
 proc stm32wbx args { eval stm32l4x $args }
 proc stm32wlx args { eval stm32l4x $args }
 
diff --git a/tcl/board/st_nucleo_l5.cfg b/tcl/board/st_nucleo_l5.cfg
new file mode 100644
index 0000000..6450f08
--- /dev/null
+++ b/tcl/board/st_nucleo_l5.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is for STM32L5 Nucleo Dev Boards.
+# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html
+
+source [find interface/stlink-dap.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32l5x.cfg]
+
+# use hardware reset
+reset_config srst_only srst_nogate
diff --git a/tcl/target/stm32l5x.cfg b/tcl/target/stm32l5x.cfg
new file mode 100644
index 0000000..bf56360
--- /dev/null
+++ b/tcl/target/stm32l5x.cfg
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32l5x family
+
+#
+# stm32l5 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32l5x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# See STM Document RM0438
+		# RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
+		# Corresponds to Cortex®-M33 JTAG debug port ID code
+		set _CPUTAPID 0x0ba04477
+	} {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x0be12477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# use non-secure RAM by default
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# declare non-secure flash
+flash bank $_CHIPNAME.flash_ns stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc clock_config_110_mhz {} {
+	# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
+	# RCC_APB1ENR1 = PWREN
+	mww 0x40021058 0x10000000
+	# delay for register clock enable (read back reg)
+	mrw 0x40021058
+	# PWR_CR1 : VOS Range 0
+	mww 0x40007000 0
+	# while (PWR_SR2 & VOSF)
+	while {([mrw 0x40007014] & 0x0400)} {}
+	# FLASH_ACR : 5 WS for 110 MHz HCLK
+	mww 0x40022000 0x00000005
+	# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
+	# fVCO = 4 x 55 /1 = 220
+	# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
+	mww 0x4002100C 0x01003711
+	# RCC_CR |= PLLON
+	mmw 0x40021000 0x01000000 0
+	# while !(RCC_CR & PLLRDY)
+	while {!([mrw 0x40021000] & 0x02000000)} {}
+	# RCC_CFGR |= SW_PLL
+	mmw 0x40021008 0x00000003 0
+	# while ((RCC_CFGR & SWS) != PLL)
+	while {([mrw 0x40021008] & 0x0C) != 0x0C} {}
+}
+
+$_TARGETNAME configure -event reset-init {
+	clock_config_110_mhz
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 480
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0xE0044004 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0044008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0044004 0x00000020 0
+}